2 * FreeRTOS Kernel V10.3.0
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3 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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28 #include "FreeRTOS.h"
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30 /*-----------------------------------------------------------*/
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32 /* Called by the startup code to initialise the run time system. */
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33 unsigned char __low_level_init(void);
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35 /*-----------------------------------------------------------*/
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37 unsigned char __low_level_init(void)
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39 unsigned char resetflag = RESF;
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40 unsigned char psval = 0;
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41 unsigned portBASE_TYPE i = 0;
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43 /* Setup provided by NEC. */
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45 portDISABLE_INTERRUPTS(); /* disable global interrupts */
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47 PRCMD = 0x00; /* On-chip debug mode */
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49 VSWC = 0x00; /* set system wait control register */
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50 WDTM2 = 0x00; /* WDT2 setting */
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51 PLLON = 0; /* PLL stop mode */
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52 psval = 0x0A | 0x00;
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53 PRCMD = psval; /* set Command Register */
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54 CKC = psval; /* set Clock Control Register */
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56 psval = 0x80; /* Set fXX and fCPU */
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59 PLLON = 1; /* activate PLL */
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60 for( i = 0; i <= 2000; i++ ) /* Wait for stabilisation */
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64 while( LOCK ) /* Wait for PLL frequency stabiliasation */
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68 SELPLL = 1; /* Set PLL mode active */
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69 RSTOP = 0; /* Set fR (enable) */
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70 BGCE0 = 0; /* Set fBRG(disable) */
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71 psval = 0x00; /* Stand-by setting */
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72 PRCMD = psval; /* set Command Register */
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73 PSC = psval; /* set Power Save Control Register */
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77 /*-----------------------------------------------------------*/
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