git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/NiosII_CycloneIII_DBC3C40_GCC/cpu.ptf

   1 SYSTEM cpu\r
   2 {\r
   3    System_Wizard_Version = "8.00";\r
   4    System_Wizard_Build = "215";\r
   5    Builder_Application = "sopc_builder_ca";\r
   6    WIZARD_SCRIPT_ARGUMENTS \r
   7    {\r
   8       hdl_language = "vhdl";\r
   9       device_family = "CYCLONEIII";\r
  10       device_family_id = "CYCLONEIII";\r
  11       generate_sdk = "0";\r
  12       do_build_sim = "0";\r
  13       hardcopy_compatible = "0";\r
  14       CLOCKS \r
  15       {\r
  16          CLOCK clk\r
  17          {\r
  18             frequency = "75000000";\r
  19             source = "External";\r
  20             Is_Clock_Source = "0";\r
  21             display_name = "clk";\r
  22             pipeline = "0";\r
  23             clock_module_connection_point_for_c2h = "clk.clk";\r
  24          }\r
  25       }\r
  26       clock_freq = "75000000";\r
  27       clock_freq = "75000000";\r
  28       board_class = "";\r
  29       view_master_columns = "1";\r
  30       view_master_priorities = "0";\r
  31       generate_hdl = "";\r
  32       bustype_column_width = "0";\r
  33       clock_column_width = "80";\r
  34       name_column_width = "75";\r
  35       desc_column_width = "75";\r
  36       base_column_width = "75";\r
  37       end_column_width = "75";\r
  38       BOARD_INFO \r
  39       {\r
  40          altera_avalon_epcs_flash_controller \r
  41          {\r
  42             reference_designators = "";\r
  43          }\r
  44          altera_avalon_cfi_flash \r
  45          {\r
  46             reference_designators = "";\r
  47          }\r
  48       }\r
  49       do_log_history = "0";\r
  50    }\r
  51    MODULE cpu_0\r
  52    {\r
  53       MASTER instruction_master\r
  54       {\r
  55          PORT_WIRING \r
  56          {\r
  57             PORT clk\r
  58             {\r
  59                type = "clk";\r
  60                width = "1";\r
  61                direction = "input";\r
  62                Is_Enabled = "1";\r
  63             }\r
  64             PORT reset_n\r
  65             {\r
  66                type = "reset_n";\r
  67                width = "1";\r
  68                direction = "input";\r
  69                Is_Enabled = "0";\r
  70             }\r
  71             PORT i_address\r
  72             {\r
  73                type = "address";\r
  74                width = "25";\r
  75                direction = "output";\r
  76                Is_Enabled = "1";\r
  77             }\r
  78             PORT i_read\r
  79             {\r
  80                type = "read";\r
  81                width = "1";\r
  82                direction = "output";\r
  83                Is_Enabled = "1";\r
  84             }\r
  85             PORT i_readdata\r
  86             {\r
  87                type = "readdata";\r
  88                width = "32";\r
  89                direction = "input";\r
  90                Is_Enabled = "1";\r
  91             }\r
  92             PORT i_readdatavalid\r
  93             {\r
  94                type = "readdatavalid";\r
  95                width = "1";\r
  96                direction = "input";\r
  97                Is_Enabled = "1";\r
  98             }\r
  99             PORT i_waitrequest\r
 100             {\r
 101                type = "waitrequest";\r
 102                width = "1";\r
 103                direction = "input";\r
 104                Is_Enabled = "1";\r
 105             }\r
 106          }\r
 107          SYSTEM_BUILDER_INFO \r
 108          {\r
 109             Bus_Type = "avalon";\r
 110             Is_Asynchronous = "0";\r
 111             DBS_Big_Endian = "0";\r
 112             Adapts_To = "";\r
 113             Do_Stream_Reads = "0";\r
 114             Do_Stream_Writes = "0";\r
 115             Max_Address_Width = "32";\r
 116             Data_Width = "32";\r
 117             Address_Width = "25";\r
 118             Maximum_Burst_Size = "1";\r
 119             Register_Incoming_Signals = "0";\r
 120             Register_Outgoing_Signals = "0";\r
 121             Interleave_Bursts = "";\r
 122             Linewrap_Bursts = "";\r
 123             Burst_On_Burst_Boundaries_Only = "";\r
 124             Always_Burst_Max_Burst = "";\r
 125             Is_Big_Endian = "0";\r
 126             Is_Enabled = "1";\r
 127             Is_Instruction_Master = "1";\r
 128             Is_Readable = "1";\r
 129             Is_Writeable = "0";\r
 130             Address_Group = "0";\r
 131             Has_IRQ = "0";\r
 132             Irq_Scheme = "individual_requests";\r
 133             Interrupt_Range = "0-0";\r
 134          }\r
 135          MEMORY_MAP \r
 136          {\r
 137             Entry cpu_0/jtag_debug_module\r
 138             {\r
 139                address = "0x00901800";\r
 140                span = "0x00000800";\r
 141                is_bridge = "0";\r
 142             }\r
 143             Entry onchip_memory/s1\r
 144             {\r
 145                address = "0x00904000";\r
 146                span = "0x00002000";\r
 147                is_bridge = "0";\r
 148             }\r
 149             Entry sdram/s1\r
 150             {\r
 151                address = "0x01000000";\r
 152                span = "0x01000000";\r
 153                is_bridge = "0";\r
 154             }\r
 155             Entry epcs_controller/epcs_control_port\r
 156             {\r
 157                address = "0x00906000";\r
 158                span = "0x00000800";\r
 159                is_bridge = "0";\r
 160             }\r
 161             Entry cfi_flash/s1\r
 162             {\r
 163                address = "0x00000000";\r
 164                span = "0x00800000";\r
 165                is_bridge = "0";\r
 166             }\r
 167             Entry DBC3C40_SRAM_inst/avalon_tristate_slave\r
 168             {\r
 169                address = "0x00800000";\r
 170                span = "0x00100000";\r
 171                is_bridge = "0";\r
 172             }\r
 173          }\r
 174       }\r
 175       MASTER custom_instruction_master\r
 176       {\r
 177          SYSTEM_BUILDER_INFO \r
 178          {\r
 179             Bus_Type = "nios_custom_instruction";\r
 180             Data_Width = "32";\r
 181             Address_Width = "8";\r
 182             Is_Custom_Instruction = "1";\r
 183             Is_Enabled = "0";\r
 184             Max_Address_Width = "8";\r
 185             Base_Address = "N/A";\r
 186             Is_Visible = "0";\r
 187          }\r
 188          PORT_WIRING \r
 189          {\r
 190             PORT dataa\r
 191             {\r
 192                type = "dataa";\r
 193                width = "32";\r
 194                direction = "output";\r
 195             }\r
 196             PORT datab\r
 197             {\r
 198                type = "datab";\r
 199                width = "32";\r
 200                direction = "output";\r
 201             }\r
 202             PORT result\r
 203             {\r
 204                type = "result";\r
 205                width = "32";\r
 206                direction = "input";\r
 207             }\r
 208             PORT clk_en\r
 209             {\r
 210                type = "clk_en";\r
 211                width = "1";\r
 212                direction = "output";\r
 213             }\r
 214             PORT reset\r
 215             {\r
 216                type = "reset";\r
 217                width = "1";\r
 218                direction = "output";\r
 219             }\r
 220             PORT start\r
 221             {\r
 222                type = "start";\r
 223                width = "1";\r
 224                direction = "output";\r
 225             }\r
 226             PORT done\r
 227             {\r
 228                type = "done";\r
 229                width = "1";\r
 230                direction = "input";\r
 231             }\r
 232             PORT n\r
 233             {\r
 234                type = "n";\r
 235                width = "8";\r
 236                direction = "output";\r
 237             }\r
 238             PORT a\r
 239             {\r
 240                type = "a";\r
 241                width = "5";\r
 242                direction = "output";\r
 243             }\r
 244             PORT b\r
 245             {\r
 246                type = "b";\r
 247                width = "5";\r
 248                direction = "output";\r
 249             }\r
 250             PORT c\r
 251             {\r
 252                type = "c";\r
 253                width = "5";\r
 254                direction = "output";\r
 255             }\r
 256             PORT readra\r
 257             {\r
 258                type = "readra";\r
 259                width = "1";\r
 260                direction = "output";\r
 261             }\r
 262             PORT readrb\r
 263             {\r
 264                type = "readrb";\r
 265                width = "1";\r
 266                direction = "output";\r
 267             }\r
 268             PORT writerc\r
 269             {\r
 270                type = "writerc";\r
 271                width = "1";\r
 272                direction = "output";\r
 273             }\r
 274          }\r
 275       }\r
 276       SLAVE jtag_debug_module\r
 277       {\r
 278          SYSTEM_BUILDER_INFO \r
 279          {\r
 280             Bus_Type = "avalon";\r
 281             Write_Wait_States = "0cycles";\r
 282             Read_Wait_States = "1cycles";\r
 283             Hold_Time = "0cycles";\r
 284             Setup_Time = "0cycles";\r
 285             Is_Printable_Device = "0";\r
 286             Address_Alignment = "dynamic";\r
 287             Well_Behaved_Waitrequest = "0";\r
 288             Is_Nonvolatile_Storage = "0";\r
 289             Address_Span = "2048";\r
 290             Read_Latency = "0";\r
 291             Is_Memory_Device = "1";\r
 292             Maximum_Pending_Read_Transactions = "0";\r
 293             Minimum_Uninterrupted_Run_Length = "1";\r
 294             Accepts_Internal_Connections = "1";\r
 295             Write_Latency = "0";\r
 296             Is_Flash = "0";\r
 297             Data_Width = "32";\r
 298             Address_Width = "9";\r
 299             Maximum_Burst_Size = "1";\r
 300             Register_Incoming_Signals = "0";\r
 301             Register_Outgoing_Signals = "0";\r
 302             Interleave_Bursts = "0";\r
 303             Linewrap_Bursts = "0";\r
 304             Burst_On_Burst_Boundaries_Only = "0";\r
 305             Always_Burst_Max_Burst = "0";\r
 306             Is_Big_Endian = "0";\r
 307             Is_Enabled = "1";\r
 308             Accepts_External_Connections = "1";\r
 309             Requires_Internal_Connections = "";\r
 310             MASTERED_BY cpu_0/instruction_master\r
 311             {\r
 312                priority = "1";\r
 313                Offset_Address = "0x00901800";\r
 314             }\r
 315             MASTERED_BY cpu_0/data_master\r
 316             {\r
 317                priority = "1";\r
 318                Offset_Address = "0x00901800";\r
 319             }\r
 320             Base_Address = "0x00901800";\r
 321             Is_Readable = "1";\r
 322             Is_Writeable = "1";\r
 323             Uses_Tri_State_Data_Bus = "0";\r
 324             Has_IRQ = "0";\r
 325             JTAG_Hub_Base_Id = "1118278";\r
 326             JTAG_Hub_Instance_Id = "0";\r
 327             Address_Group = "0";\r
 328             IRQ_MASTER cpu_0/data_master\r
 329             {\r
 330                IRQ_Number = "NC";\r
 331             }\r
 332          }\r
 333          PORT_WIRING \r
 334          {\r
 335             PORT jtag_debug_module_address\r
 336             {\r
 337                type = "address";\r
 338                width = "9";\r
 339                direction = "input";\r
 340                Is_Enabled = "1";\r
 341             }\r
 342             PORT jtag_debug_module_begintransfer\r
 343             {\r
 344                type = "begintransfer";\r
 345                width = "1";\r
 346                direction = "input";\r
 347                Is_Enabled = "1";\r
 348             }\r
 349             PORT jtag_debug_module_byteenable\r
 350             {\r
 351                type = "byteenable";\r
 352                width = "4";\r
 353                direction = "input";\r
 354                Is_Enabled = "1";\r
 355             }\r
 356             PORT jtag_debug_module_clk\r
 357             {\r
 358                type = "clk";\r
 359                width = "1";\r
 360                direction = "input";\r
 361                Is_Enabled = "1";\r
 362             }\r
 363             PORT jtag_debug_module_debugaccess\r
 364             {\r
 365                type = "debugaccess";\r
 366                width = "1";\r
 367                direction = "input";\r
 368                Is_Enabled = "1";\r
 369             }\r
 370             PORT jtag_debug_module_readdata\r
 371             {\r
 372                type = "readdata";\r
 373                width = "32";\r
 374                direction = "output";\r
 375                Is_Enabled = "1";\r
 376             }\r
 377             PORT jtag_debug_module_reset\r
 378             {\r
 379                type = "reset";\r
 380                width = "1";\r
 381                direction = "input";\r
 382                Is_Enabled = "1";\r
 383             }\r
 384             PORT jtag_debug_module_resetrequest\r
 385             {\r
 386                type = "resetrequest";\r
 387                width = "1";\r
 388                direction = "output";\r
 389                Is_Enabled = "1";\r
 390             }\r
 391             PORT jtag_debug_module_select\r
 392             {\r
 393                type = "chipselect";\r
 394                width = "1";\r
 395                direction = "input";\r
 396                Is_Enabled = "1";\r
 397             }\r
 398             PORT jtag_debug_module_write\r
 399             {\r
 400                type = "write";\r
 401                width = "1";\r
 402                direction = "input";\r
 403                Is_Enabled = "1";\r
 404             }\r
 405             PORT jtag_debug_module_writedata\r
 406             {\r
 407                type = "writedata";\r
 408                width = "32";\r
 409                direction = "input";\r
 410                Is_Enabled = "1";\r
 411             }\r
 412             PORT reset_n\r
 413             {\r
 414                Is_Enabled = "1";\r
 415                direction = "input";\r
 416                type = "reset_n";\r
 417                width = "1";\r
 418             }\r
 419          }\r
 420       }\r
 421       MASTER data_master\r
 422       {\r
 423          SYSTEM_BUILDER_INFO \r
 424          {\r
 425             Has_IRQ = "1";\r
 426             Irq_Scheme = "individual_requests";\r
 427             Bus_Type = "avalon";\r
 428             Is_Asynchronous = "0";\r
 429             DBS_Big_Endian = "0";\r
 430             Adapts_To = "";\r
 431             Do_Stream_Reads = "0";\r
 432             Do_Stream_Writes = "0";\r
 433             Max_Address_Width = "32";\r
 434             Data_Width = "32";\r
 435             Address_Width = "25";\r
 436             Maximum_Burst_Size = "1";\r
 437             Register_Incoming_Signals = "1";\r
 438             Register_Outgoing_Signals = "0";\r
 439             Interleave_Bursts = "0";\r
 440             Linewrap_Bursts = "0";\r
 441             Burst_On_Burst_Boundaries_Only = "";\r
 442             Always_Burst_Max_Burst = "0";\r
 443             Is_Big_Endian = "0";\r
 444             Is_Enabled = "1";\r
 445             Is_Data_Master = "1";\r
 446             Address_Group = "0";\r
 447             Is_Readable = "1";\r
 448             Is_Writeable = "1";\r
 449             Interrupt_Range = "0-31";\r
 450          }\r
 451          PORT_WIRING \r
 452          {\r
 453             PORT d_irq\r
 454             {\r
 455                type = "irq";\r
 456                width = "32";\r
 457                direction = "input";\r
 458                Is_Enabled = "1";\r
 459             }\r
 460             PORT d_address\r
 461             {\r
 462                type = "address";\r
 463                width = "25";\r
 464                direction = "output";\r
 465                Is_Enabled = "1";\r
 466             }\r
 467             PORT d_byteenable\r
 468             {\r
 469                type = "byteenable";\r
 470                width = "4";\r
 471                direction = "output";\r
 472                Is_Enabled = "1";\r
 473             }\r
 474             PORT d_read\r
 475             {\r
 476                type = "read";\r
 477                width = "1";\r
 478                direction = "output";\r
 479                Is_Enabled = "1";\r
 480             }\r
 481             PORT d_readdata\r
 482             {\r
 483                type = "readdata";\r
 484                width = "32";\r
 485                direction = "input";\r
 486                Is_Enabled = "1";\r
 487             }\r
 488             PORT d_readdatavalid\r
 489             {\r
 490                type = "readdatavalid";\r
 491                width = "1";\r
 492                direction = "input";\r
 493                Is_Enabled = "0";\r
 494             }\r
 495             PORT d_waitrequest\r
 496             {\r
 497                type = "waitrequest";\r
 498                width = "1";\r
 499                direction = "input";\r
 500                Is_Enabled = "1";\r
 501             }\r
 502             PORT d_write\r
 503             {\r
 504                type = "write";\r
 505                width = "1";\r
 506                direction = "output";\r
 507                Is_Enabled = "1";\r
 508             }\r
 509             PORT d_writedata\r
 510             {\r
 511                type = "writedata";\r
 512                width = "32";\r
 513                direction = "output";\r
 514                Is_Enabled = "1";\r
 515             }\r
 516             PORT jtag_debug_module_debugaccess_to_roms\r
 517             {\r
 518                type = "debugaccess";\r
 519                width = "1";\r
 520                direction = "output";\r
 521                Is_Enabled = "1";\r
 522             }\r
 523          }\r
 524          MEMORY_MAP \r
 525          {\r
 526             Entry cpu_0/jtag_debug_module\r
 527             {\r
 528                address = "0x00901800";\r
 529                span = "0x00000800";\r
 530                is_bridge = "0";\r
 531             }\r
 532             Entry onchip_memory/s1\r
 533             {\r
 534                address = "0x00904000";\r
 535                span = "0x00002000";\r
 536                is_bridge = "0";\r
 537             }\r
 538             Entry jtag_uart_0/avalon_jtag_slave\r
 539             {\r
 540                address = "0x009000d0";\r
 541                span = "0x00000008";\r
 542                is_bridge = "0";\r
 543             }\r
 544             Entry sdram/s1\r
 545             {\r
 546                address = "0x01000000";\r
 547                span = "0x01000000";\r
 548                is_bridge = "0";\r
 549             }\r
 550             Entry sysid/control_slave\r
 551             {\r
 552                address = "0x009000d8";\r
 553                span = "0x00000008";\r
 554                is_bridge = "0";\r
 555             }\r
 556             Entry LED_Pio/s1\r
 557             {\r
 558                address = "0x00900080";\r
 559                span = "0x00000010";\r
 560                is_bridge = "0";\r
 561             }\r
 562             Entry SG_Pio/s1\r
 563             {\r
 564                address = "0x00900090";\r
 565                span = "0x00000010";\r
 566                is_bridge = "0";\r
 567             }\r
 568             Entry IO_Pio/s1\r
 569             {\r
 570                address = "0x009000a0";\r
 571                span = "0x00000010";\r
 572                is_bridge = "0";\r
 573             }\r
 574             Entry Button_Pio/s1\r
 575             {\r
 576                address = "0x009000b0";\r
 577                span = "0x00000010";\r
 578                is_bridge = "0";\r
 579             }\r
 580             Entry uart/s1\r
 581             {\r
 582                address = "0x00900040";\r
 583                span = "0x00000020";\r
 584                is_bridge = "0";\r
 585             }\r
 586             Entry LM74_Pio/s1\r
 587             {\r
 588                address = "0x009000c0";\r
 589                span = "0x00000010";\r
 590                is_bridge = "0";\r
 591             }\r
 592             Entry epcs_controller/epcs_control_port\r
 593             {\r
 594                address = "0x00906000";\r
 595                span = "0x00000800";\r
 596                is_bridge = "0";\r
 597             }\r
 598             Entry cfi_flash/s1\r
 599             {\r
 600                address = "0x00000000";\r
 601                span = "0x00800000";\r
 602                is_bridge = "0";\r
 603             }\r
 604             Entry DBC3C40_SRAM_inst/avalon_tristate_slave\r
 605             {\r
 606                address = "0x00800000";\r
 607                span = "0x00100000";\r
 608                is_bridge = "0";\r
 609             }\r
 610             Entry sys_clk/s1\r
 611             {\r
 612                address = "0x00900060";\r
 613                span = "0x00000020";\r
 614                is_bridge = "0";\r
 615             }\r
 616             Entry nios_vga_inst/vga_regs\r
 617             {\r
 618                address = "0x00900000";\r
 619                span = "0x00000040";\r
 620                is_bridge = "0";\r
 621             }\r
 622          }\r
 623       }\r
 624       WIZARD_SCRIPT_ARGUMENTS \r
 625       {\r
 626          cache_has_dcache = "0";\r
 627          cache_dcache_size = "0";\r
 628          cache_dcache_line_size = "0";\r
 629          cache_dcache_bursts = "0";\r
 630          cache_dcache_ram_block_type = "AUTO";\r
 631          num_tightly_coupled_data_masters = "0";\r
 632          gui_num_tightly_coupled_data_masters = "0";\r
 633          gui_include_tightly_coupled_data_masters = "0";\r
 634          gui_omit_avalon_data_master = "0";\r
 635          cache_has_icache = "1";\r
 636          cache_icache_size = "16384";\r
 637          cache_icache_line_size = "32";\r
 638          cache_icache_ram_block_type = "AUTO";\r
 639          cache_icache_bursts = "0";\r
 640          num_tightly_coupled_instruction_masters = "0";\r
 641          gui_num_tightly_coupled_instruction_masters = "0";\r
 642          gui_include_tightly_coupled_instruction_masters = "0";\r
 643          debug_level = "3";\r
 644          include_oci = "1";\r
 645          oci_sbi_enabled = "1";\r
 646          oci_num_xbrk = "2";\r
 647          oci_num_dbrk = "2";\r
 648          oci_dbrk_trace = "0";\r
 649          oci_dbrk_pairs = "1";\r
 650          oci_onchip_trace = "0";\r
 651          oci_offchip_trace = "0";\r
 652          oci_data_trace = "0";\r
 653          include_third_party_debug_port = "0";\r
 654          oci_trace_addr_width = "7";\r
 655          oci_trigger_arming = "1";\r
 656          oci_debugreq_signals = "0";\r
 657          oci_embedded_pll = "0";\r
 658          oci_num_pm = "0";\r
 659          oci_pm_width = "32";\r
 660          performance_counters_present = "0";\r
 661          performance_counters_width = "32";\r
 662          always_encrypt = "1";\r
 663          debug_simgen = "0";\r
 664          activate_model_checker = "0";\r
 665          activate_test_end_checker = "0";\r
 666          activate_trace = "1";\r
 667          activate_monitors = "1";\r
 668          clear_x_bits_ld_non_bypass = "1";\r
 669          bit_31_bypass_dcache = "1";\r
 670          hdl_sim_caches_cleared = "1";\r
 671          hbreak_test = "0";\r
 672          allow_full_address_range = "0";\r
 673          extra_exc_info = "0";\r
 674          branch_prediction_type = "Static";\r
 675          bht_ptr_sz = "8";\r
 676          bht_index_pc_only = "0";\r
 677          gui_branch_prediction_type = "Static";\r
 678          full_waveform_signals = "0";\r
 679          export_pcb = "0";\r
 680          avalon_debug_port_present = "0";\r
 681          illegal_instructions_trap = "0";\r
 682          illegal_memory_access_detection = "0";\r
 683          illegal_mem_exc = "0";\r
 684          slave_access_error_exc = "0";\r
 685          division_error_exc = "0";\r
 686          advanced_exc = "0";\r
 687          gui_mmu_present = "0";\r
 688          mmu_present = "0";\r
 689          process_id_num_bits = "8";\r
 690          tlb_ptr_sz = "7";\r
 691          tlb_num_ways = "16";\r
 692          udtlb_num_entries = "6";\r
 693          uitlb_num_entries = "4";\r
 694          fast_tlb_miss_exc_slave = "";\r
 695          fast_tlb_miss_exc_offset = "0x00000000";\r
 696          mpu_present = "0";\r
 697          mpu_num_data_regions = "8";\r
 698          mpu_num_inst_regions = "8";\r
 699          mpu_min_data_region_size_log2 = "12";\r
 700          mpu_min_inst_region_size_log2 = "12";\r
 701          mpu_use_limit = "0";\r
 702          hardware_divide_present = "0";\r
 703          gui_hardware_divide_setting = "0";\r
 704          hardware_multiply_present = "1";\r
 705          hardware_multiply_impl = "embedded_mul";\r
 706          shift_rot_impl = "fast_le_shift";\r
 707          gui_hardware_multiply_setting = "embedded_mul_fast_le_shift";\r
 708          reset_slave = "cfi_flash/s1";\r
 709          break_slave = "cpu_0/jtag_debug_module";\r
 710          exc_slave = "sdram/s1";\r
 711          reset_offset = "0x00000000";\r
 712          break_offset = "0x00000020";\r
 713          exc_offset = "0x00000020";\r
 714          cpu_reset = "0";\r
 715          CPU_Implementation = "small";\r
 716          cpu_selection = "s";\r
 717          device_family_id = "CYCLONEIII";\r
 718          address_stall_present = "1";\r
 719          dsp_block_supports_shift = "0";\r
 720          mrams_present = "0";\r
 721          do_generate = "1";\r
 722          cpuid_value = "0";\r
 723          cpuid_sz = "1";\r
 724          dont_overwrite_cpuid = "1";\r
 725          allow_legacy_sdk = "1";\r
 726          legacy_sdk_support = "1";\r
 727          inst_addr_width = "25";\r
 728          data_addr_width = "25";\r
 729          asp_debug = "0";\r
 730          asp_core_debug = "0";\r
 731          CPU_Architecture = "nios2";\r
 732          cache_icache_burst_type = "none";\r
 733          include_debug = "0";\r
 734          include_trace = "0";\r
 735          hardware_multiply_uses_les = "0";\r
 736          hardware_multiply_omits_msw = "1";\r
 737          big_endian = "0";\r
 738          break_slave_override = "";\r
 739          break_offset_override = "0x20";\r
 740          altera_show_unreleased_features = "0";\r
 741          altera_show_unpublished_features = "0";\r
 742          altera_internal_test = "0";\r
 743          alt_log_port_base = "";\r
 744          alt_log_port_type = "";\r
 745          gui_illegal_instructions_trap = "0";\r
 746          atomic_mem_present = "0";\r
 747          nmi_present = "0";\r
 748          fast_intr_present = "0";\r
 749          num_shadow_regs = "0";\r
 750          gui_illegal_memory_access_detection = "0";\r
 751          cache_omit_dcache = "0";\r
 752          cache_omit_icache = "0";\r
 753          omit_instruction_master = "0";\r
 754          omit_data_master = "0";\r
 755          ras_ptr_sz = "4";\r
 756          jtb_ptr_sz = "5";\r
 757          ibuf_ptr_sz = "4";\r
 758          always_bypass_dcache = "0";\r
 759          iss_trace_on = "0";\r
 760          iss_trace_warning = "1";\r
 761          iss_trace_info = "1";\r
 762          iss_trace_disassembly = "0";\r
 763          iss_trace_registers = "0";\r
 764          iss_trace_instr_count = "0";\r
 765          iss_software_debug = "0";\r
 766          iss_software_debug_port = "9996";\r
 767          iss_memory_dump_start = "";\r
 768          iss_memory_dump_end = "";\r
 769          Boot_Copier = "boot_loader_cfi.srec";\r
 770          Boot_Copier_EPCS = "boot_loader_epcs.srec";\r
 771          Boot_Copier_EPCS_SII_SIII_CIII = "boot_loader_epcs_sii_siii_ciii.srec";\r
 772          Boot_Copier_BE = "boot_loader_cfi_be.srec";\r
 773          Boot_Copier_EPCS_BE = "boot_loader_epcs_be.srec";\r
 774          Boot_Copier_EPCS_SII_SIII_CIII_BE = "boot_loader_epcs_sii_siii_ciii_be.srec";\r
 775          CONSTANTS \r
 776          {\r
 777             CONSTANT __nios_catch_irqs__\r
 778             {\r
 779                value = "1";\r
 780                comment = "Include panic handler for all irqs (needs uart)";\r
 781             }\r
 782             CONSTANT __nios_use_constructors__\r
 783             {\r
 784                value = "1";\r
 785                comment = "Call c++ static constructors";\r
 786             }\r
 787             CONSTANT __nios_use_small_printf__\r
 788             {\r
 789                value = "1";\r
 790                comment = "Smaller non-ANSI printf, with no floating point";\r
 791             }\r
 792             CONSTANT nasys_has_icache\r
 793             {\r
 794                value = "1";\r
 795                comment = "True if instruction cache present";\r
 796             }\r
 797             CONSTANT nasys_icache_size\r
 798             {\r
 799                value = "16384";\r
 800                comment = "Size in bytes of instruction cache";\r
 801             }\r
 802             CONSTANT nasys_icache_line_size\r
 803             {\r
 804                value = "32";\r
 805                comment = "Size in bytes of each icache line";\r
 806             }\r
 807             CONSTANT nasys_icache_line_size_log2\r
 808             {\r
 809                value = "5";\r
 810                comment = "Log2 size in bytes of each icache line";\r
 811             }\r
 812             CONSTANT nasys_has_dcache\r
 813             {\r
 814                value = "0";\r
 815                comment = "True if instruction cache present";\r
 816             }\r
 817             CONSTANT nasys_dcache_size\r
 818             {\r
 819                value = "0";\r
 820                comment = "Size in bytes of data cache";\r
 821             }\r
 822             CONSTANT nasys_dcache_line_size\r
 823             {\r
 824                value = "0";\r
 825                comment = "Size in bytes of each dcache line";\r
 826             }\r
 827             CONSTANT nasys_dcache_line_size_log2\r
 828             {\r
 829                value = "-Infinity";\r
 830                comment = "Log2 size in bytes of each dcache line";\r
 831             }\r
 832          }\r
 833          license_status = "encrypted";\r
 834          mainmem_slave = "DBC3C40_SRAM_inst/avalon_tristate_slave";\r
 835          datamem_slave = "DBC3C40_SRAM_inst/avalon_tristate_slave";\r
 836          maincomm_slave = "uart/s1";\r
 837          germs_monitor_id = "";\r
 838       }\r
 839       class = "altera_nios2";\r
 840       class_version = "7.08";\r
 841       SYSTEM_BUILDER_INFO \r
 842       {\r
 843          Is_Enabled = "1";\r
 844          Clock_Source = "clk";\r
 845          Has_Clock = "1";\r
 846          Parameters_Signature = "";\r
 847          Is_CPU = "1";\r
 848          Instantiate_In_System_Module = "1";\r
 849          Required_Device_Family = "STRATIX,STRATIXGX,STRATIXII,STRATIXIIGX,STRATIXIIGXLITE,STRATIXIII,STRATIXIV,CYCLONE,CYCLONEII,CYCLONEIII";\r
 850          Default_Module_Name = "cpu";\r
 851          Top_Level_Ports_Are_Enumerated = "1";\r
 852          View \r
 853          {\r
 854             Settings_Summary = "Nios II/s
 855             <br>&nbsp;&nbsp;16-Kbyte Instruction Cache
 856
 857             <br>&nbsp;&nbsp;JTAG Debug Module
 858             ";\r
 859             MESSAGES \r
 860             {\r
 861             }\r
 862          }\r
 863       }\r
 864       iss_model_name = "altera_nios2";\r
 865       HDL_INFO \r
 866       {\r
 867          PLI_Files = "";\r
 868          Precompiled_Simulation_Library_Files = "";\r
 869          Simulation_HDL_Files = "";\r
 870          Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/cpu_0_test_bench.vhd, __PROJECT_DIRECTORY__/cpu_0_mult_cell.vhd, __PROJECT_DIRECTORY__/cpu_0_jtag_debug_module_tck.vhd, __PROJECT_DIRECTORY__/cpu_0_jtag_debug_module_sysclk.vhd, __PROJECT_DIRECTORY__/cpu_0_jtag_debug_module_wrapper.vhd, __PROJECT_DIRECTORY__/cpu_0.vhd";\r
 871          Synthesis_Only_Files = "";\r
 872       }\r
 873       MASTER tightly_coupled_instruction_master_0\r
 874       {\r
 875          PORT_WIRING \r
 876          {\r
 877          }\r
 878          SYSTEM_BUILDER_INFO \r
 879          {\r
 880             Register_Incoming_Signals = "0";\r
 881             Bus_Type = "avalon";\r
 882             Data_Width = "32";\r
 883             Max_Address_Width = "31";\r
 884             Address_Width = "8";\r
 885             Is_Instruction_Master = "1";\r
 886             Has_IRQ = "0";\r
 887             Is_Enabled = "0";\r
 888             Is_Big_Endian = "0";\r
 889             Connection_Limit = "1";\r
 890             Is_Channel = "1";\r
 891          }\r
 892       }\r
 893       MASTER tightly_coupled_instruction_master_1\r
 894       {\r
 895          PORT_WIRING \r
 896          {\r
 897          }\r
 898          SYSTEM_BUILDER_INFO \r
 899          {\r
 900             Register_Incoming_Signals = "0";\r
 901             Bus_Type = "avalon";\r
 902             Data_Width = "32";\r
 903             Max_Address_Width = "31";\r
 904             Address_Width = "8";\r
 905             Address_Group = "0";\r
 906             Is_Instruction_Master = "1";\r
 907             Is_Readable = "1";\r
 908             Is_Writeable = "0";\r
 909             Has_IRQ = "0";\r
 910             Is_Enabled = "0";\r
 911             Is_Big_Endian = "0";\r
 912             Connection_Limit = "1";\r
 913             Is_Channel = "1";\r
 914          }\r
 915       }\r
 916       MASTER tightly_coupled_instruction_master_2\r
 917       {\r
 918          PORT_WIRING \r
 919          {\r
 920          }\r
 921          SYSTEM_BUILDER_INFO \r
 922          {\r
 923             Register_Incoming_Signals = "0";\r
 924             Bus_Type = "avalon";\r
 925             Data_Width = "32";\r
 926             Max_Address_Width = "31";\r
 927             Address_Width = "8";\r
 928             Address_Group = "0";\r
 929             Is_Instruction_Master = "1";\r
 930             Is_Readable = "1";\r
 931             Is_Writeable = "0";\r
 932             Has_IRQ = "0";\r
 933             Is_Enabled = "0";\r
 934             Is_Big_Endian = "0";\r
 935             Connection_Limit = "1";\r
 936             Is_Channel = "1";\r
 937          }\r
 938       }\r
 939       MASTER tightly_coupled_instruction_master_3\r
 940       {\r
 941          PORT_WIRING \r
 942          {\r
 943          }\r
 944          SYSTEM_BUILDER_INFO \r
 945          {\r
 946             Register_Incoming_Signals = "0";\r
 947             Bus_Type = "avalon";\r
 948             Data_Width = "32";\r
 949             Max_Address_Width = "31";\r
 950             Address_Width = "8";\r
 951             Address_Group = "0";\r
 952             Is_Instruction_Master = "1";\r
 953             Is_Readable = "1";\r
 954             Is_Writeable = "0";\r
 955             Has_IRQ = "0";\r
 956             Is_Enabled = "0";\r
 957             Is_Big_Endian = "0";\r
 958             Connection_Limit = "1";\r
 959             Is_Channel = "1";\r
 960          }\r
 961       }\r
 962       MASTER data_master2\r
 963       {\r
 964          PORT_WIRING \r
 965          {\r
 966          }\r
 967          SYSTEM_BUILDER_INFO \r
 968          {\r
 969             Register_Incoming_Signals = "1";\r
 970             Bus_Type = "avalon";\r
 971             Data_Width = "32";\r
 972             Max_Address_Width = "31";\r
 973             Address_Width = "8";\r
 974             Address_Group = "0";\r
 975             Is_Data_Master = "1";\r
 976             Is_Readable = "1";\r
 977             Is_Writeable = "1";\r
 978             Has_IRQ = "0";\r
 979             Is_Enabled = "0";\r
 980             Is_Big_Endian = "0";\r
 981          }\r
 982       }\r
 983       MASTER tightly_coupled_data_master_0\r
 984       {\r
 985          PORT_WIRING \r
 986          {\r
 987          }\r
 988          SYSTEM_BUILDER_INFO \r
 989          {\r
 990             Register_Incoming_Signals = "0";\r
 991             Bus_Type = "avalon";\r
 992             Data_Width = "32";\r
 993             Max_Address_Width = "31";\r
 994             Address_Width = "8";\r
 995             Address_Group = "0";\r
 996             Is_Data_Master = "1";\r
 997             Is_Readable = "1";\r
 998             Is_Writeable = "1";\r
 999             Has_IRQ = "0";\r
1000             Is_Enabled = "0";\r
1001             Is_Big_Endian = "0";\r
1002             Connection_Limit = "1";\r
1003             Is_Channel = "1";\r
1004          }\r
1005       }\r
1006       MASTER tightly_coupled_data_master_1\r
1007       {\r
1008          PORT_WIRING \r
1009          {\r
1010          }\r
1011          SYSTEM_BUILDER_INFO \r
1012          {\r
1013             Register_Incoming_Signals = "0";\r
1014             Bus_Type = "avalon";\r
1015             Data_Width = "32";\r
1016             Max_Address_Width = "31";\r
1017             Address_Width = "8";\r
1018             Address_Group = "0";\r
1019             Is_Data_Master = "1";\r
1020             Is_Readable = "1";\r
1021             Is_Writeable = "1";\r
1022             Has_IRQ = "0";\r
1023             Is_Enabled = "0";\r
1024             Is_Big_Endian = "0";\r
1025             Connection_Limit = "1";\r
1026             Is_Channel = "1";\r
1027          }\r
1028       }\r
1029       MASTER tightly_coupled_data_master_2\r
1030       {\r
1031          PORT_WIRING \r
1032          {\r
1033          }\r
1034          SYSTEM_BUILDER_INFO \r
1035          {\r
1036             Register_Incoming_Signals = "0";\r
1037             Bus_Type = "avalon";\r
1038             Data_Width = "32";\r
1039             Max_Address_Width = "31";\r
1040             Address_Width = "8";\r
1041             Address_Group = "0";\r
1042             Is_Data_Master = "1";\r
1043             Is_Readable = "1";\r
1044             Is_Writeable = "1";\r
1045             Has_IRQ = "0";\r
1046             Is_Enabled = "0";\r
1047             Is_Big_Endian = "0";\r
1048             Connection_Limit = "1";\r
1049             Is_Channel = "1";\r
1050          }\r
1051       }\r
1052       MASTER tightly_coupled_data_master_3\r
1053       {\r
1054          PORT_WIRING \r
1055          {\r
1056          }\r
1057          SYSTEM_BUILDER_INFO \r
1058          {\r
1059             Register_Incoming_Signals = "0";\r
1060             Bus_Type = "avalon";\r
1061             Data_Width = "32";\r
1062             Max_Address_Width = "31";\r
1063             Address_Width = "8";\r
1064             Address_Group = "0";\r
1065             Is_Data_Master = "1";\r
1066             Is_Readable = "1";\r
1067             Is_Writeable = "1";\r
1068             Has_IRQ = "0";\r
1069             Is_Enabled = "0";\r
1070             Is_Big_Endian = "0";\r
1071             Connection_Limit = "1";\r
1072             Is_Channel = "1";\r
1073          }\r
1074       }\r
1075       PORT_WIRING \r
1076       {\r
1077          PORT jtag_debug_trigout\r
1078          {\r
1079             width = "1";\r
1080             direction = "output";\r
1081             Is_Enabled = "0";\r
1082          }\r
1083          PORT jtag_debug_offchip_trace_clk\r
1084          {\r
1085             width = "1";\r
1086             direction = "output";\r
1087             Is_Enabled = "0";\r
1088          }\r
1089          PORT jtag_debug_offchip_trace_data\r
1090          {\r
1091             width = "18";\r
1092             direction = "output";\r
1093             Is_Enabled = "0";\r
1094          }\r
1095          PORT clkx2\r
1096          {\r
1097             width = "1";\r
1098             direction = "input";\r
1099             Is_Enabled = "0";\r
1100             visible = "0";\r
1101          }\r
1102       }\r
1103       SIMULATION \r
1104       {\r
1105          DISPLAY \r
1106          {\r
1107             SIGNAL aaa\r
1108             {\r
1109                format = "Logic";\r
1110                name = "i_readdata";\r
1111                radix = "hexadecimal";\r
1112             }\r
1113             SIGNAL aab\r
1114             {\r
1115                format = "Logic";\r
1116                name = "i_readdatavalid";\r
1117                radix = "hexadecimal";\r
1118             }\r
1119             SIGNAL aac\r
1120             {\r
1121                format = "Logic";\r
1122                name = "i_waitrequest";\r
1123                radix = "hexadecimal";\r
1124             }\r
1125             SIGNAL aad\r
1126             {\r
1127                format = "Logic";\r
1128                name = "i_address";\r
1129                radix = "hexadecimal";\r
1130             }\r
1131             SIGNAL aae\r
1132             {\r
1133                format = "Logic";\r
1134                name = "i_read";\r
1135                radix = "hexadecimal";\r
1136             }\r
1137             SIGNAL aaf\r
1138             {\r
1139                format = "Logic";\r
1140                name = "clk";\r
1141                radix = "hexadecimal";\r
1142             }\r
1143             SIGNAL aag\r
1144             {\r
1145                format = "Logic";\r
1146                name = "reset_n";\r
1147                radix = "hexadecimal";\r
1148             }\r
1149             SIGNAL aah\r
1150             {\r
1151                format = "Logic";\r
1152                name = "d_readdata";\r
1153                radix = "hexadecimal";\r
1154             }\r
1155             SIGNAL aai\r
1156             {\r
1157                format = "Logic";\r
1158                name = "d_waitrequest";\r
1159                radix = "hexadecimal";\r
1160             }\r
1161             SIGNAL aaj\r
1162             {\r
1163                format = "Logic";\r
1164                name = "d_irq";\r
1165                radix = "hexadecimal";\r
1166             }\r
1167             SIGNAL aak\r
1168             {\r
1169                format = "Logic";\r
1170                name = "d_address";\r
1171                radix = "hexadecimal";\r
1172             }\r
1173             SIGNAL aal\r
1174             {\r
1175                format = "Logic";\r
1176                name = "d_byteenable";\r
1177                radix = "hexadecimal";\r
1178             }\r
1179             SIGNAL aam\r
1180             {\r
1181                format = "Logic";\r
1182                name = "d_read";\r
1183                radix = "hexadecimal";\r
1184             }\r
1185             SIGNAL aan\r
1186             {\r
1187                format = "Logic";\r
1188                name = "d_write";\r
1189                radix = "hexadecimal";\r
1190             }\r
1191             SIGNAL aao\r
1192             {\r
1193                format = "Logic";\r
1194                name = "d_writedata";\r
1195                radix = "hexadecimal";\r
1196             }\r
1197             SIGNAL aap\r
1198             {\r
1199                format = "Divider";\r
1200                name = "base pipeline";\r
1201                radix = "";\r
1202             }\r
1203             SIGNAL aaq\r
1204             {\r
1205                format = "Logic";\r
1206                name = "clk";\r
1207                radix = "hexadecimal";\r
1208             }\r
1209             SIGNAL aar\r
1210             {\r
1211                format = "Logic";\r
1212                name = "reset_n";\r
1213                radix = "hexadecimal";\r
1214             }\r
1215             SIGNAL aas\r
1216             {\r
1217                format = "Logic";\r
1218                name = "M_stall";\r
1219                radix = "hexadecimal";\r
1220             }\r
1221             SIGNAL aat\r
1222             {\r
1223                format = "Logic";\r
1224                name = "F_pcb_nxt";\r
1225                radix = "hexadecimal";\r
1226             }\r
1227             SIGNAL aau\r
1228             {\r
1229                format = "Logic";\r
1230                name = "F_pcb";\r
1231                radix = "hexadecimal";\r
1232             }\r
1233             SIGNAL aav\r
1234             {\r
1235                format = "Logic";\r
1236                name = "D_pcb";\r
1237                radix = "hexadecimal";\r
1238             }\r
1239             SIGNAL aaw\r
1240             {\r
1241                format = "Logic";\r
1242                name = "E_pcb";\r
1243                radix = "hexadecimal";\r
1244             }\r
1245             SIGNAL aax\r
1246             {\r
1247                format = "Logic";\r
1248                name = "M_pcb";\r
1249                radix = "hexadecimal";\r
1250             }\r
1251             SIGNAL aay\r
1252             {\r
1253                format = "Logic";\r
1254                name = "W_pcb";\r
1255                radix = "hexadecimal";\r
1256             }\r
1257             SIGNAL aaz\r
1258             {\r
1259                format = "Logic";\r
1260                name = "F_vinst";\r
1261                radix = "ascii";\r
1262             }\r
1263             SIGNAL aba\r
1264             {\r
1265                format = "Logic";\r
1266                name = "D_vinst";\r
1267                radix = "ascii";\r
1268             }\r
1269             SIGNAL abb\r
1270             {\r
1271                format = "Logic";\r
1272                name = "E_vinst";\r
1273                radix = "ascii";\r
1274             }\r
1275             SIGNAL abc\r
1276             {\r
1277                format = "Logic";\r
1278                name = "M_vinst";\r
1279                radix = "ascii";\r
1280             }\r
1281             SIGNAL abd\r
1282             {\r
1283                format = "Logic";\r
1284                name = "W_vinst";\r
1285                radix = "ascii";\r
1286             }\r
1287             SIGNAL abe\r
1288             {\r
1289                format = "Logic";\r
1290                name = "F_inst_ram_hit";\r
1291                radix = "hexadecimal";\r
1292             }\r
1293             SIGNAL abf\r
1294             {\r
1295                format = "Logic";\r
1296                name = "F_issue";\r
1297                radix = "hexadecimal";\r
1298             }\r
1299             SIGNAL abg\r
1300             {\r
1301                format = "Logic";\r
1302                name = "F_kill";\r
1303                radix = "hexadecimal";\r
1304             }\r
1305             SIGNAL abh\r
1306             {\r
1307                format = "Logic";\r
1308                name = "D_kill";\r
1309                radix = "hexadecimal";\r
1310             }\r
1311             SIGNAL abi\r
1312             {\r
1313                format = "Logic";\r
1314                name = "D_refetch";\r
1315                radix = "hexadecimal";\r
1316             }\r
1317             SIGNAL abj\r
1318             {\r
1319                format = "Logic";\r
1320                name = "D_issue";\r
1321                radix = "hexadecimal";\r
1322             }\r
1323             SIGNAL abk\r
1324             {\r
1325                format = "Logic";\r
1326                name = "D_valid";\r
1327                radix = "hexadecimal";\r
1328             }\r
1329             SIGNAL abl\r
1330             {\r
1331                format = "Logic";\r
1332                name = "E_valid";\r
1333                radix = "hexadecimal";\r
1334             }\r
1335             SIGNAL abm\r
1336             {\r
1337                format = "Logic";\r
1338                name = "M_valid";\r
1339                radix = "hexadecimal";\r
1340             }\r
1341             SIGNAL abn\r
1342             {\r
1343                format = "Logic";\r
1344                name = "W_valid";\r
1345                radix = "hexadecimal";\r
1346             }\r
1347             SIGNAL abo\r
1348             {\r
1349                format = "Logic";\r
1350                name = "W_wr_dst_reg";\r
1351                radix = "hexadecimal";\r
1352             }\r
1353             SIGNAL abp\r
1354             {\r
1355                format = "Logic";\r
1356                name = "W_dst_regnum";\r
1357                radix = "hexadecimal";\r
1358             }\r
1359             SIGNAL abq\r
1360             {\r
1361                format = "Logic";\r
1362                name = "W_wr_data";\r
1363                radix = "hexadecimal";\r
1364             }\r
1365             SIGNAL abr\r
1366             {\r
1367                format = "Logic";\r
1368                name = "F_en";\r
1369                radix = "hexadecimal";\r
1370             }\r
1371             SIGNAL abs\r
1372             {\r
1373                format = "Logic";\r
1374                name = "D_en";\r
1375                radix = "hexadecimal";\r
1376             }\r
1377             SIGNAL abt\r
1378             {\r
1379                format = "Logic";\r
1380                name = "E_en";\r
1381                radix = "hexadecimal";\r
1382             }\r
1383             SIGNAL abu\r
1384             {\r
1385                format = "Logic";\r
1386                name = "M_en";\r
1387                radix = "hexadecimal";\r
1388             }\r
1389             SIGNAL abv\r
1390             {\r
1391                format = "Logic";\r
1392                name = "F_iw";\r
1393                radix = "hexadecimal";\r
1394             }\r
1395             SIGNAL abw\r
1396             {\r
1397                format = "Logic";\r
1398                name = "D_iw";\r
1399                radix = "hexadecimal";\r
1400             }\r
1401             SIGNAL abx\r
1402             {\r
1403                format = "Logic";\r
1404                name = "E_iw";\r
1405                radix = "hexadecimal";\r
1406             }\r
1407             SIGNAL aby\r
1408             {\r
1409                format = "Logic";\r
1410                name = "E_valid_prior_to_hbreak";\r
1411                radix = "hexadecimal";\r
1412             }\r
1413             SIGNAL abz\r
1414             {\r
1415                format = "Logic";\r
1416                name = "M_pipe_flush_nxt";\r
1417                radix = "hexadecimal";\r
1418             }\r
1419             SIGNAL aca\r
1420             {\r
1421                format = "Logic";\r
1422                name = "M_pipe_flush_baddr_nxt";\r
1423                radix = "hexadecimal";\r
1424             }\r
1425             SIGNAL acb\r
1426             {\r
1427                format = "Logic";\r
1428                name = "M_status_reg_pie";\r
1429                radix = "hexadecimal";\r
1430             }\r
1431             SIGNAL acc\r
1432             {\r
1433                format = "Logic";\r
1434                name = "M_ienable_reg";\r
1435                radix = "hexadecimal";\r
1436             }\r
1437             SIGNAL acd\r
1438             {\r
1439                format = "Logic";\r
1440                name = "intr_req";\r
1441                radix = "hexadecimal";\r
1442             }\r
1443          }\r
1444       }\r
1445    }\r
1446    MODULE onchip_memory\r
1447    {\r
1448       SLAVE s1\r
1449       {\r
1450          PORT_WIRING \r
1451          {\r
1452             PORT clk\r
1453             {\r
1454                type = "clk";\r
1455                width = "1";\r
1456                direction = "input";\r
1457                Is_Enabled = "1";\r
1458             }\r
1459             PORT reset_n\r
1460             {\r
1461                type = "reset_n";\r
1462                width = "1";\r
1463                direction = "input";\r
1464                Is_Enabled = "0";\r
1465             }\r
1466             PORT address\r
1467             {\r
1468                type = "address";\r
1469                width = "11";\r
1470                direction = "input";\r
1471                Is_Enabled = "1";\r
1472             }\r
1473             PORT chipselect\r
1474             {\r
1475                type = "chipselect";\r
1476                width = "1";\r
1477                direction = "input";\r
1478                Is_Enabled = "1";\r
1479             }\r
1480             PORT clken\r
1481             {\r
1482                type = "clken";\r
1483                width = "1";\r
1484                direction = "input";\r
1485                Is_Enabled = "1";\r
1486                default_value = "1'b1";\r
1487             }\r
1488             PORT read\r
1489             {\r
1490                type = "read";\r
1491                width = "1";\r
1492                direction = "input";\r
1493                Is_Enabled = "0";\r
1494             }\r
1495             PORT readdata\r
1496             {\r
1497                type = "readdata";\r
1498                width = "32";\r
1499                direction = "output";\r
1500                Is_Enabled = "1";\r
1501             }\r
1502             PORT write\r
1503             {\r
1504                type = "write";\r
1505                width = "1";\r
1506                direction = "input";\r
1507                Is_Enabled = "1";\r
1508             }\r
1509             PORT writedata\r
1510             {\r
1511                type = "writedata";\r
1512                width = "32";\r
1513                direction = "input";\r
1514                Is_Enabled = "1";\r
1515             }\r
1516             PORT debugaccess\r
1517             {\r
1518                type = "debugaccess";\r
1519                width = "1";\r
1520                direction = "input";\r
1521                Is_Enabled = "0";\r
1522             }\r
1523             PORT byteenable\r
1524             {\r
1525                type = "byteenable";\r
1526                width = "4";\r
1527                direction = "input";\r
1528                Is_Enabled = "1";\r
1529             }\r
1530          }\r
1531          SYSTEM_BUILDER_INFO \r
1532          {\r
1533             Bus_Type = "avalon";\r
1534             Write_Wait_States = "0cycles";\r
1535             Read_Wait_States = "0cycles";\r
1536             Hold_Time = "0cycles";\r
1537             Setup_Time = "0cycles";\r
1538             Is_Printable_Device = "0";\r
1539             Address_Alignment = "dynamic";\r
1540             Well_Behaved_Waitrequest = "0";\r
1541             Is_Nonvolatile_Storage = "0";\r
1542             Address_Span = "8192";\r
1543             Read_Latency = "1";\r
1544             Is_Memory_Device = "1";\r
1545             Maximum_Pending_Read_Transactions = "0";\r
1546             Minimum_Uninterrupted_Run_Length = "1";\r
1547             Accepts_Internal_Connections = "1";\r
1548             Write_Latency = "0";\r
1549             Is_Flash = "0";\r
1550             Data_Width = "32";\r
1551             Address_Width = "11";\r
1552             Maximum_Burst_Size = "1";\r
1553             Register_Incoming_Signals = "0";\r
1554             Register_Outgoing_Signals = "0";\r
1555             Interleave_Bursts = "0";\r
1556             Linewrap_Bursts = "0";\r
1557             Burst_On_Burst_Boundaries_Only = "0";\r
1558             Always_Burst_Max_Burst = "0";\r
1559             Is_Big_Endian = "0";\r
1560             Is_Enabled = "1";\r
1561             MASTERED_BY cpu_0/instruction_master\r
1562             {\r
1563                priority = "1";\r
1564                Offset_Address = "0x00904000";\r
1565             }\r
1566             MASTERED_BY cpu_0/data_master\r
1567             {\r
1568                priority = "1";\r
1569                Offset_Address = "0x00904000";\r
1570             }\r
1571             Base_Address = "0x00904000";\r
1572             Address_Group = "0";\r
1573             Has_IRQ = "0";\r
1574             Is_Channel = "1";\r
1575             Is_Writable = "1";\r
1576             IRQ_MASTER cpu_0/data_master\r
1577             {\r
1578                IRQ_Number = "NC";\r
1579             }\r
1580          }\r
1581       }\r
1582       iss_model_name = "altera_memory";\r
1583       WIZARD_SCRIPT_ARGUMENTS \r
1584       {\r
1585          allow_mram_sim_contents_only_file = "0";\r
1586          ram_block_type = "AUTO";\r
1587          init_contents_file = "onchip_memory";\r
1588          non_default_init_file_enabled = "0";\r
1589          gui_ram_block_type = "Automatic";\r
1590          Writeable = "1";\r
1591          dual_port = "0";\r
1592          Size_Value = "8192";\r
1593          Size_Multiple = "1";\r
1594          use_shallow_mem_blocks = "0";\r
1595          init_mem_content = "1";\r
1596          allow_in_system_memory_content_editor = "0";\r
1597          instance_id = "NONE";\r
1598          read_during_write_mode = "DONT_CARE";\r
1599          ignore_auto_block_type_assignment = "1";\r
1600          MAKE \r
1601          {\r
1602             TARGET delete_placeholder_warning\r
1603             {\r
1604                onchip_memory \r
1605                {\r
1606                   Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";\r
1607                   Is_Phony = "1";\r
1608                   Target_File = "do_delete_placeholder_warning";\r
1609                }\r
1610             }\r
1611             TARGET hex\r
1612             {\r
1613                onchip_memory \r
1614                {\r
1615                   Command1 = "@echo Post-processing to create $(notdir $@)";\r
1616                   Command2 = "elf2hex $(ELF) 0x00904000 0x905FFF --width=32 $(QUARTUS_PROJECT_DIR)/onchip_memory.hex --create-lanes=0 ";\r
1617                   Dependency = "$(ELF)";\r
1618                   Target_File = "$(QUARTUS_PROJECT_DIR)/onchip_memory.hex";\r
1619                }\r
1620             }\r
1621             TARGET sim\r
1622             {\r
1623                onchip_memory \r
1624                {\r
1625                   Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";\r
1626                   Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";\r
1627                   Command3 = "touch $(SIMDIR)/dummy_file";\r
1628                   Dependency = "$(ELF)";\r
1629                   Target_File = "$(SIMDIR)/dummy_file";\r
1630                }\r
1631             }\r
1632          }\r
1633          contents_info = "";\r
1634       }\r
1635       SIMULATION \r
1636       {\r
1637          DISPLAY \r
1638          {\r
1639             SIGNAL a\r
1640             {\r
1641                name = "chipselect";\r
1642                conditional = "1";\r
1643             }\r
1644             SIGNAL c\r
1645             {\r
1646                name = "address";\r
1647                radix = "hexadecimal";\r
1648             }\r
1649             SIGNAL d\r
1650             {\r
1651                name = "byteenable";\r
1652                radix = "binary";\r
1653                conditional = "1";\r
1654             }\r
1655             SIGNAL e\r
1656             {\r
1657                name = "readdata";\r
1658                radix = "hexadecimal";\r
1659             }\r
1660             SIGNAL b\r
1661             {\r
1662                name = "write";\r
1663                conditional = "1";\r
1664             }\r
1665             SIGNAL f\r
1666             {\r
1667                name = "writedata";\r
1668                radix = "hexadecimal";\r
1669                conditional = "1";\r
1670             }\r
1671          }\r
1672       }\r
1673       SYSTEM_BUILDER_INFO \r
1674       {\r
1675          Prohibited_Device_Family = "MERCURY, APEX20K, APEX20KE, APEX20KC, APEXII, ACEX1K, FLEX10KE, EXCALIBUR_ARM, MAXII";\r
1676          Instantiate_In_System_Module = "1";\r
1677          Is_Enabled = "1";\r
1678          Default_Module_Name = "onchip_memory";\r
1679          Top_Level_Ports_Are_Enumerated = "1";\r
1680          Clock_Source = "clk";\r
1681          Has_Clock = "1";\r
1682          View \r
1683          {\r
1684             MESSAGES \r
1685             {\r
1686             }\r
1687          }\r
1688       }\r
1689       class = "altera_avalon_onchip_memory2";\r
1690       class_version = "7.08";\r
1691       HDL_INFO \r
1692       {\r
1693          Precompiled_Simulation_Library_Files = "";\r
1694          Simulation_HDL_Files = "";\r
1695          Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/onchip_memory.vhd";\r
1696          Synthesis_Only_Files = "";\r
1697       }\r
1698       SLAVE s2\r
1699       {\r
1700          PORT_WIRING \r
1701          {\r
1702          }\r
1703          SYSTEM_BUILDER_INFO \r
1704          {\r
1705             Bus_Type = "avalon";\r
1706             Is_Memory_Device = "1";\r
1707             Address_Group = "0";\r
1708             Address_Alignment = "dynamic";\r
1709             Address_Width = "11";\r
1710             Data_Width = "32";\r
1711             Has_IRQ = "0";\r
1712             Read_Wait_States = "0";\r
1713             Write_Wait_States = "0";\r
1714             Address_Span = "8192";\r
1715             Read_Latency = "1";\r
1716             Is_Channel = "1";\r
1717             Is_Enabled = "0";\r
1718             Is_Writable = "1";\r
1719          }\r
1720       }\r
1721       PORT_WIRING \r
1722       {\r
1723       }\r
1724    }\r
1725    MODULE jtag_uart_0\r
1726    {\r
1727       SLAVE avalon_jtag_slave\r
1728       {\r
1729          PORT_WIRING \r
1730          {\r
1731             PORT clk\r
1732             {\r
1733                type = "clk";\r
1734                width = "1";\r
1735                direction = "input";\r
1736                Is_Enabled = "1";\r
1737             }\r
1738             PORT reset_n\r
1739             {\r
1740                type = "reset_n";\r
1741                width = "1";\r
1742                direction = "input";\r
1743                Is_Enabled = "0";\r
1744             }\r
1745             PORT av_irq\r
1746             {\r
1747                type = "irq";\r
1748                width = "1";\r
1749                direction = "output";\r
1750                Is_Enabled = "1";\r
1751             }\r
1752             PORT av_chipselect\r
1753             {\r
1754                type = "chipselect";\r
1755                width = "1";\r
1756                direction = "input";\r
1757                Is_Enabled = "1";\r
1758             }\r
1759             PORT av_address\r
1760             {\r
1761                type = "address";\r
1762                width = "1";\r
1763                direction = "input";\r
1764                Is_Enabled = "1";\r
1765             }\r
1766             PORT av_read_n\r
1767             {\r
1768                type = "read_n";\r
1769                width = "1";\r
1770                direction = "input";\r
1771                Is_Enabled = "1";\r
1772             }\r
1773             PORT av_readdata\r
1774             {\r
1775                type = "readdata";\r
1776                width = "32";\r
1777                direction = "output";\r
1778                Is_Enabled = "1";\r
1779             }\r
1780             PORT av_write_n\r
1781             {\r
1782                type = "write_n";\r
1783                width = "1";\r
1784                direction = "input";\r
1785                Is_Enabled = "1";\r
1786             }\r
1787             PORT av_writedata\r
1788             {\r
1789                type = "writedata";\r
1790                width = "32";\r
1791                direction = "input";\r
1792                Is_Enabled = "1";\r
1793             }\r
1794             PORT av_waitrequest\r
1795             {\r
1796                type = "waitrequest";\r
1797                width = "1";\r
1798                direction = "output";\r
1799                Is_Enabled = "1";\r
1800             }\r
1801             PORT dataavailable\r
1802             {\r
1803                type = "dataavailable";\r
1804                width = "1";\r
1805                direction = "output";\r
1806                Is_Enabled = "1";\r
1807             }\r
1808             PORT readyfordata\r
1809             {\r
1810                type = "readyfordata";\r
1811                width = "1";\r
1812                direction = "output";\r
1813                Is_Enabled = "1";\r
1814             }\r
1815             PORT rst_n\r
1816             {\r
1817                type = "reset_n";\r
1818                direction = "input";\r
1819                width = "1";\r
1820                Is_Enabled = "1";\r
1821             }\r
1822          }\r
1823          SYSTEM_BUILDER_INFO \r
1824          {\r
1825             Has_IRQ = "1";\r
1826             Bus_Type = "avalon";\r
1827             Read_Wait_States = "peripheral_controlled";\r
1828             Write_Wait_States = "peripheral_controlled";\r
1829             Hold_Time = "0cycles";\r
1830             Setup_Time = "0cycles";\r
1831             Is_Printable_Device = "1";\r
1832             Address_Alignment = "native";\r
1833             Well_Behaved_Waitrequest = "0";\r
1834             Is_Nonvolatile_Storage = "0";\r
1835             Read_Latency = "0";\r
1836             Is_Memory_Device = "0";\r
1837             Maximum_Pending_Read_Transactions = "0";\r
1838             Minimum_Uninterrupted_Run_Length = "1";\r
1839             Accepts_Internal_Connections = "1";\r
1840             Write_Latency = "0";\r
1841             Is_Flash = "0";\r
1842             Data_Width = "32";\r
1843             Address_Width = "1";\r
1844             Maximum_Burst_Size = "1";\r
1845             Register_Incoming_Signals = "0";\r
1846             Register_Outgoing_Signals = "0";\r
1847             Interleave_Bursts = "0";\r
1848             Linewrap_Bursts = "0";\r
1849             Burst_On_Burst_Boundaries_Only = "0";\r
1850             Always_Burst_Max_Burst = "0";\r
1851             Is_Big_Endian = "0";\r
1852             Is_Enabled = "1";\r
1853             JTAG_Hub_Base_Id = "262254";\r
1854             JTAG_Hub_Instance_Id = "0";\r
1855             Connection_Limit = "1";\r
1856             MASTERED_BY cpu_0/data_master\r
1857             {\r
1858                priority = "1";\r
1859                Offset_Address = "0x009000d0";\r
1860             }\r
1861             IRQ_MASTER cpu_0/data_master\r
1862             {\r
1863                IRQ_Number = "1";\r
1864             }\r
1865             Base_Address = "0x009000d0";\r
1866             Address_Group = "0";\r
1867          }\r
1868       }\r
1869       class = "altera_avalon_jtag_uart";\r
1870       class_version = "7.08";\r
1871       iss_model_name = "altera_avalon_jtag_uart";\r
1872       WIZARD_SCRIPT_ARGUMENTS \r
1873       {\r
1874          write_depth = "64";\r
1875          read_depth = "64";\r
1876          write_threshold = "8";\r
1877          read_threshold = "8";\r
1878          read_char_stream = "";\r
1879          showascii = "1";\r
1880          read_le = "0";\r
1881          write_le = "0";\r
1882          altera_show_unreleased_jtag_uart_features = "0";\r
1883       }\r
1884       SIMULATION \r
1885       {\r
1886          DISPLAY \r
1887          {\r
1888             SIGNAL av_chipselect\r
1889             {\r
1890                name = "av_chipselect";\r
1891             }\r
1892             SIGNAL av_address\r
1893             {\r
1894                name = "av_address";\r
1895                radix = "hexadecimal";\r
1896             }\r
1897             SIGNAL av_read_n\r
1898             {\r
1899                name = "av_read_n";\r
1900             }\r
1901             SIGNAL av_readdata\r
1902             {\r
1903                name = "av_readdata";\r
1904                radix = "hexadecimal";\r
1905             }\r
1906             SIGNAL av_write_n\r
1907             {\r
1908                name = "av_write_n";\r
1909             }\r
1910             SIGNAL av_writedata\r
1911             {\r
1912                name = "av_writedata";\r
1913                radix = "hexadecimal";\r
1914             }\r
1915             SIGNAL av_waitrequest\r
1916             {\r
1917                name = "av_waitrequest";\r
1918             }\r
1919             SIGNAL dataavailable\r
1920             {\r
1921                name = "dataavailable";\r
1922             }\r
1923             SIGNAL readyfordata\r
1924             {\r
1925                name = "readyfordata";\r
1926             }\r
1927             SIGNAL av_irq\r
1928             {\r
1929                name = "av_irq";\r
1930             }\r
1931          }\r
1932          INTERACTIVE_IN drive\r
1933          {\r
1934             enable = "0";\r
1935             file = "_input_data_stream.dat";\r
1936             mutex = "_input_data_mutex.dat";\r
1937             log = "_in.log";\r
1938             rate = "100";\r
1939             signals = "temp,list";\r
1940             exe = "nios2-terminal";\r
1941          }\r
1942          INTERACTIVE_OUT log\r
1943          {\r
1944             enable = "1";\r
1945             exe = "perl -- atail-f.pl";\r
1946             file = "_output_stream.dat";\r
1947             radix = "ascii";\r
1948             signals = "temp,list";\r
1949          }\r
1950          Fix_Me_Up = "";\r
1951       }\r
1952       SYSTEM_BUILDER_INFO \r
1953       {\r
1954          Is_Enabled = "1";\r
1955          Clock_Source = "clk";\r
1956          Has_Clock = "1";\r
1957          Instantiate_In_System_Module = "1";\r
1958          Iss_Launch_Telnet = "0";\r
1959          Top_Level_Ports_Are_Enumerated = "1";\r
1960          View \r
1961          {\r
1962             MESSAGES \r
1963             {\r
1964             }\r
1965             Settings_Summary = "<br>Write Depth: 64; Write IRQ Threshold: 8
1966                 <br>Read  Depth: 64; Read  IRQ Threshold: 8";\r
1967          }\r
1968       }\r
1969       HDL_INFO \r
1970       {\r
1971          Precompiled_Simulation_Library_Files = "";\r
1972          Simulation_HDL_Files = "";\r
1973          Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/jtag_uart_0.vhd";\r
1974          Synthesis_Only_Files = "";\r
1975       }\r
1976       PORT_WIRING \r
1977       {\r
1978       }\r
1979    }\r
1980    MODULE sdram\r
1981    {\r
1982       SLAVE s1\r
1983       {\r
1984          PORT_WIRING \r
1985          {\r
1986             PORT clk\r
1987             {\r
1988                type = "clk";\r
1989                width = "1";\r
1990                direction = "input";\r
1991                Is_Enabled = "1";\r
1992             }\r
1993             PORT reset_n\r
1994             {\r
1995                type = "reset_n";\r
1996                width = "1";\r
1997                direction = "input";\r
1998                Is_Enabled = "1";\r
1999             }\r
2000             PORT az_addr\r
2001             {\r
2002                type = "address";\r
2003                width = "22";\r
2004                direction = "input";\r
2005                Is_Enabled = "1";\r
2006             }\r
2007             PORT az_be_n\r
2008             {\r
2009                type = "byteenable_n";\r
2010                width = "4";\r
2011                direction = "input";\r
2012                Is_Enabled = "1";\r
2013             }\r
2014             PORT az_cs\r
2015             {\r
2016                type = "chipselect";\r
2017                width = "1";\r
2018                direction = "input";\r
2019                Is_Enabled = "1";\r
2020             }\r
2021             PORT az_data\r
2022             {\r
2023                type = "writedata";\r
2024                width = "32";\r
2025                direction = "input";\r
2026                Is_Enabled = "1";\r
2027             }\r
2028             PORT az_rd_n\r
2029             {\r
2030                type = "read_n";\r
2031                width = "1";\r
2032                direction = "input";\r
2033                Is_Enabled = "1";\r
2034             }\r
2035             PORT az_wr_n\r
2036             {\r
2037                type = "write_n";\r
2038                width = "1";\r
2039                direction = "input";\r
2040                Is_Enabled = "1";\r
2041             }\r
2042             PORT za_data\r
2043             {\r
2044                type = "readdata";\r
2045                width = "32";\r
2046                direction = "output";\r
2047                Is_Enabled = "1";\r
2048             }\r
2049             PORT za_valid\r
2050             {\r
2051                type = "readdatavalid";\r
2052                width = "1";\r
2053                direction = "output";\r
2054                Is_Enabled = "1";\r
2055             }\r
2056             PORT za_waitrequest\r
2057             {\r
2058                type = "waitrequest";\r
2059                width = "1";\r
2060                direction = "output";\r
2061                Is_Enabled = "1";\r
2062             }\r
2063             PORT zs_addr\r
2064             {\r
2065                direction = "output";\r
2066                width = "12";\r
2067                Is_Enabled = "1";\r
2068             }\r
2069             PORT zs_ba\r
2070             {\r
2071                direction = "output";\r
2072                width = "2";\r
2073                Is_Enabled = "1";\r
2074             }\r
2075             PORT zs_cas_n\r
2076             {\r
2077                direction = "output";\r
2078                width = "1";\r
2079                Is_Enabled = "1";\r
2080             }\r
2081             PORT zs_cke\r
2082             {\r
2083                direction = "output";\r
2084                width = "1";\r
2085                Is_Enabled = "1";\r
2086             }\r
2087             PORT zs_cs_n\r
2088             {\r
2089                direction = "output";\r
2090                width = "1";\r
2091                Is_Enabled = "1";\r
2092             }\r
2093             PORT zs_dq\r
2094             {\r
2095                direction = "inout";\r
2096                width = "32";\r
2097                Is_Enabled = "1";\r
2098             }\r
2099             PORT zs_dqm\r
2100             {\r
2101                direction = "output";\r
2102                width = "4";\r
2103                Is_Enabled = "1";\r
2104             }\r
2105             PORT zs_ras_n\r
2106             {\r
2107                direction = "output";\r
2108                width = "1";\r
2109                Is_Enabled = "1";\r
2110             }\r
2111             PORT zs_we_n\r
2112             {\r
2113                direction = "output";\r
2114                width = "1";\r
2115                Is_Enabled = "1";\r
2116             }\r
2117          }\r
2118          SYSTEM_BUILDER_INFO \r
2119          {\r
2120             Bus_Type = "avalon";\r
2121             Read_Wait_States = "peripheral_controlled";\r
2122             Write_Wait_States = "peripheral_controlled";\r
2123             Hold_Time = "0cycles";\r
2124             Setup_Time = "0cycles";\r
2125             Is_Printable_Device = "0";\r
2126             Address_Alignment = "dynamic";\r
2127             Well_Behaved_Waitrequest = "0";\r
2128             Is_Nonvolatile_Storage = "0";\r
2129             Address_Span = "16777216";\r
2130             Read_Latency = "0";\r
2131             Is_Memory_Device = "1";\r
2132             Maximum_Pending_Read_Transactions = "6";\r
2133             Minimum_Uninterrupted_Run_Length = "1";\r
2134             Accepts_Internal_Connections = "1";\r
2135             Write_Latency = "0";\r
2136             Is_Flash = "0";\r
2137             Data_Width = "32";\r
2138             Address_Width = "22";\r
2139             Maximum_Burst_Size = "1";\r
2140             Register_Incoming_Signals = "0";\r
2141             Register_Outgoing_Signals = "0";\r
2142             Interleave_Bursts = "0";\r
2143             Linewrap_Bursts = "0";\r
2144             Burst_On_Burst_Boundaries_Only = "0";\r
2145             Always_Burst_Max_Burst = "0";\r
2146             Is_Big_Endian = "0";\r
2147             Is_Enabled = "1";\r
2148             MASTERED_BY cpu_0/instruction_master\r
2149             {\r
2150                priority = "1";\r
2151                Offset_Address = "0x01000000";\r
2152             }\r
2153             MASTERED_BY cpu_0/data_master\r
2154             {\r
2155                priority = "1";\r
2156                Offset_Address = "0x01000000";\r
2157             }\r
2158             Base_Address = "0x01000000";\r
2159             Has_IRQ = "0";\r
2160             Simulation_Num_Lanes = "1";\r
2161             Address_Group = "0";\r
2162             IRQ_MASTER cpu_0/data_master\r
2163             {\r
2164                IRQ_Number = "NC";\r
2165             }\r
2166          }\r
2167       }\r
2168       PORT_WIRING \r
2169       {\r
2170          PORT zs_addr\r
2171          {\r
2172             type = "export";\r
2173             width = "12";\r
2174             direction = "output";\r
2175             Is_Enabled = "0";\r
2176          }\r
2177          PORT zs_ba\r
2178          {\r
2179             type = "export";\r
2180             width = "2";\r
2181             direction = "output";\r
2182             Is_Enabled = "0";\r
2183          }\r
2184          PORT zs_cas_n\r
2185          {\r
2186             type = "export";\r
2187             width = "1";\r
2188             direction = "output";\r
2189             Is_Enabled = "0";\r
2190          }\r
2191          PORT zs_cke\r
2192          {\r
2193             type = "export";\r
2194             width = "1";\r
2195             direction = "output";\r
2196             Is_Enabled = "0";\r
2197          }\r
2198          PORT zs_cs_n\r
2199          {\r
2200             type = "export";\r
2201             width = "1";\r
2202             direction = "output";\r
2203             Is_Enabled = "0";\r
2204          }\r
2205          PORT zs_dq\r
2206          {\r
2207             type = "export";\r
2208             width = "32";\r
2209             direction = "output";\r
2210             Is_Enabled = "0";\r
2211          }\r
2212          PORT zs_dqm\r
2213          {\r
2214             type = "export";\r
2215             width = "4";\r
2216             direction = "output";\r
2217             Is_Enabled = "0";\r
2218          }\r
2219          PORT zs_ras_n\r
2220          {\r
2221             type = "export";\r
2222             width = "1";\r
2223             direction = "output";\r
2224             Is_Enabled = "0";\r
2225          }\r
2226          PORT zs_we_n\r
2227          {\r
2228             type = "export";\r
2229             width = "1";\r
2230             direction = "output";\r
2231             Is_Enabled = "0";\r
2232          }\r
2233       }\r
2234       iss_model_name = "altera_memory";\r
2235       WIZARD_SCRIPT_ARGUMENTS \r
2236       {\r
2237          register_data_in = "1";\r
2238          sim_model_base = "0";\r
2239          sdram_data_width = "32";\r
2240          sdram_addr_width = "12";\r
2241          sdram_row_width = "12";\r
2242          sdram_col_width = "8";\r
2243          sdram_num_chipselects = "1";\r
2244          sdram_num_banks = "4";\r
2245          refresh_period = "15.625";\r
2246          powerup_delay = "100.0";\r
2247          cas_latency = "2";\r
2248          t_rfc = "70.0";\r
2249          t_rp = "15.0";\r
2250          t_mrd = "3";\r
2251          t_rcd = "15.0";\r
2252          t_ac = "6.0";\r
2253          t_wr = "14.0";\r
2254          init_refresh_commands = "2";\r
2255          init_nop_delay = "0.0";\r
2256          shared_data = "0";\r
2257          sdram_bank_width = "2";\r
2258          tristate_bridge_slave = "";\r
2259          starvation_indicator = "0";\r
2260          is_initialized = "1";\r
2261       }\r
2262       SIMULATION \r
2263       {\r
2264          DISPLAY \r
2265          {\r
2266             SIGNAL a\r
2267             {\r
2268                name = "az_addr";\r
2269                radix = "hexadecimal";\r
2270             }\r
2271             SIGNAL b\r
2272             {\r
2273                name = "az_be_n";\r
2274                radix = "hexadecimal";\r
2275             }\r
2276             SIGNAL c\r
2277             {\r
2278                name = "az_cs";\r
2279             }\r
2280             SIGNAL d\r
2281             {\r
2282                name = "az_data";\r
2283                radix = "hexadecimal";\r
2284             }\r
2285             SIGNAL e\r
2286             {\r
2287                name = "az_rd_n";\r
2288             }\r
2289             SIGNAL f\r
2290             {\r
2291                name = "az_wr_n";\r
2292             }\r
2293             SIGNAL h\r
2294             {\r
2295                name = "za_data";\r
2296                radix = "hexadecimal";\r
2297             }\r
2298             SIGNAL i\r
2299             {\r
2300                name = "za_valid";\r
2301             }\r
2302             SIGNAL j\r
2303             {\r
2304                name = "za_waitrequest";\r
2305             }\r
2306             SIGNAL l\r
2307             {\r
2308                name = "CODE";\r
2309                radix = "ascii";\r
2310             }\r
2311             SIGNAL g\r
2312             {\r
2313                name = "clk";\r
2314             }\r
2315             SIGNAL k\r
2316             {\r
2317                name = "za_cannotrefresh";\r
2318                suppress = "1";\r
2319             }\r
2320             SIGNAL m\r
2321             {\r
2322                name = "zs_addr";\r
2323                radix = "hexadecimal";\r
2324                suppress = "0";\r
2325             }\r
2326             SIGNAL n\r
2327             {\r
2328                name = "zs_ba";\r
2329                radix = "hexadecimal";\r
2330                suppress = "0";\r
2331             }\r
2332             SIGNAL o\r
2333             {\r
2334                name = "zs_cs_n";\r
2335                radix = "hexadecimal";\r
2336                suppress = "0";\r
2337             }\r
2338             SIGNAL p\r
2339             {\r
2340                name = "zs_ras_n";\r
2341                suppress = "0";\r
2342             }\r
2343             SIGNAL q\r
2344             {\r
2345                name = "zs_cas_n";\r
2346                suppress = "0";\r
2347             }\r
2348             SIGNAL r\r
2349             {\r
2350                name = "zs_we_n";\r
2351                suppress = "0";\r
2352             }\r
2353             SIGNAL s\r
2354             {\r
2355                name = "zs_dq";\r
2356                radix = "hexadecimal";\r
2357                suppress = "0";\r
2358             }\r
2359             SIGNAL t\r
2360             {\r
2361                name = "zs_dqm";\r
2362                radix = "hexadecimal";\r
2363                suppress = "0";\r
2364             }\r
2365             SIGNAL u\r
2366             {\r
2367                name = "zt_addr";\r
2368                radix = "hexadecimal";\r
2369                suppress = "1";\r
2370             }\r
2371             SIGNAL v\r
2372             {\r
2373                name = "zt_ba";\r
2374                radix = "hexadecimal";\r
2375                suppress = "1";\r
2376             }\r
2377             SIGNAL w\r
2378             {\r
2379                name = "zt_oe";\r
2380                suppress = "1";\r
2381             }\r
2382             SIGNAL x\r
2383             {\r
2384                name = "zt_cke";\r
2385                suppress = "1";\r
2386             }\r
2387             SIGNAL y\r
2388             {\r
2389                name = "zt_chipselect";\r
2390                suppress = "1";\r
2391             }\r
2392             SIGNAL z0\r
2393             {\r
2394                name = "zt_lock_n";\r
2395                suppress = "1";\r
2396             }\r
2397             SIGNAL z1\r
2398             {\r
2399                name = "zt_ras_n";\r
2400                suppress = "1";\r
2401             }\r
2402             SIGNAL z2\r
2403             {\r
2404                name = "zt_cas_n";\r
2405                suppress = "1";\r
2406             }\r
2407             SIGNAL z3\r
2408             {\r
2409                name = "zt_we_n";\r
2410                suppress = "1";\r
2411             }\r
2412             SIGNAL z4\r
2413             {\r
2414                name = "zt_cs_n";\r
2415                radix = "hexadecimal";\r
2416                suppress = "1";\r
2417             }\r
2418             SIGNAL z5\r
2419             {\r
2420                name = "zt_dqm";\r
2421                radix = "hexadecimal";\r
2422                suppress = "1";\r
2423             }\r
2424             SIGNAL z6\r
2425             {\r
2426                name = "zt_data";\r
2427                radix = "hexadecimal";\r
2428                suppress = "1";\r
2429             }\r
2430             SIGNAL z7\r
2431             {\r
2432                name = "tz_data";\r
2433                radix = "hexadecimal";\r
2434                suppress = "1";\r
2435             }\r
2436             SIGNAL z8\r
2437             {\r
2438                name = "tz_waitrequest";\r
2439                suppress = "1";\r
2440             }\r
2441          }\r
2442          Fix_Me_Up = "";\r
2443       }\r
2444       SYSTEM_BUILDER_INFO \r
2445       {\r
2446          Instantiate_In_System_Module = "1";\r
2447          Is_Enabled = "1";\r
2448          Default_Module_Name = "sdram";\r
2449          Top_Level_Ports_Are_Enumerated = "1";\r
2450          Clock_Source = "clk";\r
2451          Has_Clock = "1";\r
2452          Disable_Simulation_Port_Wiring = "0";\r
2453          View \r
2454          {\r
2455             MESSAGES \r
2456             {\r
2457             }\r
2458             Settings_Summary = "4194304 x 32<br>
2459                 Memory size: 16 MBytes<br>
2460                 128 MBits
2461                 ";\r
2462          }\r
2463       }\r
2464       class = "altera_avalon_new_sdram_controller";\r
2465       class_version = "7.08";\r
2466       HDL_INFO \r
2467       {\r
2468          Precompiled_Simulation_Library_Files = "";\r
2469          Simulation_HDL_Files = "";\r
2470          Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sdram.vhd";\r
2471          Synthesis_Only_Files = "";\r
2472       }\r
2473    }\r
2474    MODULE sysid\r
2475    {\r
2476       SLAVE control_slave\r
2477       {\r
2478          PORT_WIRING \r
2479          {\r
2480             PORT clock\r
2481             {\r
2482                type = "clk";\r
2483                width = "1";\r
2484                direction = "input";\r
2485                Is_Enabled = "0";\r
2486             }\r
2487             PORT reset_n\r
2488             {\r
2489                type = "reset_n";\r
2490                width = "1";\r
2491                direction = "input";\r
2492                Is_Enabled = "0";\r
2493             }\r
2494             PORT address\r
2495             {\r
2496                type = "address";\r
2497                width = "1";\r
2498                direction = "input";\r
2499                Is_Enabled = "1";\r
2500             }\r
2501             PORT readdata\r
2502             {\r
2503                type = "readdata";\r
2504                width = "32";\r
2505                direction = "output";\r
2506                Is_Enabled = "1";\r
2507             }\r
2508          }\r
2509          SYSTEM_BUILDER_INFO \r
2510          {\r
2511             Bus_Type = "avalon";\r
2512             Write_Wait_States = "0cycles";\r
2513             Read_Wait_States = "1cycles";\r
2514             Hold_Time = "0cycles";\r
2515             Setup_Time = "0cycles";\r
2516             Is_Printable_Device = "0";\r
2517             Address_Alignment = "native";\r
2518             Well_Behaved_Waitrequest = "0";\r
2519             Is_Nonvolatile_Storage = "0";\r
2520             Read_Latency = "0";\r
2521             Is_Memory_Device = "0";\r
2522             Maximum_Pending_Read_Transactions = "0";\r
2523             Minimum_Uninterrupted_Run_Length = "1";\r
2524             Accepts_Internal_Connections = "1";\r
2525             Write_Latency = "0";\r
2526             Is_Flash = "0";\r
2527             Data_Width = "32";\r
2528             Address_Width = "1";\r
2529             Maximum_Burst_Size = "1";\r
2530             Register_Incoming_Signals = "0";\r
2531             Register_Outgoing_Signals = "0";\r
2532             Interleave_Bursts = "0";\r
2533             Linewrap_Bursts = "0";\r
2534             Burst_On_Burst_Boundaries_Only = "0";\r
2535             Always_Burst_Max_Burst = "0";\r
2536             Is_Big_Endian = "0";\r
2537             Is_Enabled = "1";\r
2538             MASTERED_BY cpu_0/data_master\r
2539             {\r
2540                priority = "1";\r
2541                Offset_Address = "0x009000d8";\r
2542             }\r
2543             Base_Address = "0x009000d8";\r
2544             Has_IRQ = "0";\r
2545             Address_Group = "0";\r
2546             IRQ_MASTER cpu_0/data_master\r
2547             {\r
2548                IRQ_Number = "NC";\r
2549             }\r
2550          }\r
2551       }\r
2552       class = "altera_avalon_sysid";\r
2553       class_version = "7.08";\r
2554       SYSTEM_BUILDER_INFO \r
2555       {\r
2556          Date_Modified = "";\r
2557          Is_Enabled = "1";\r
2558          Instantiate_In_System_Module = "1";\r
2559          Fixed_Module_Name = "sysid";\r
2560          Top_Level_Ports_Are_Enumerated = "1";\r
2561          Clock_Source = "clk";\r
2562          Has_Clock = "1";\r
2563          View \r
2564          {\r
2565             Settings_Summary = "System ID (at last Generate):<br> <b>2A1C5786</b>    (unique ID tag) <br> <b>485BC1C0</b> (timestamp: Fri Jun 20, 2008 @4:42 PM)";\r
2566             MESSAGES \r
2567             {\r
2568             }\r
2569          }\r
2570       }\r
2571       WIZARD_SCRIPT_ARGUMENTS \r
2572       {\r
2573          id = "706500486u";\r
2574          timestamp = "1213972928u";\r
2575          regenerate_values = "0";\r
2576          MAKE \r
2577          {\r
2578             TARGET verifysysid\r
2579             {\r
2580                verifysysid \r
2581                {\r
2582                   All_Depends_On = "0";\r
2583                   Command = "nios2-download $(JTAG_CABLE)                                --sidp=0x009000d8 --id=706500486 --timestamp=1213972928";\r
2584                   Is_Phony = "1";\r
2585                   Target_File = "dummy_verifysysid_file";\r
2586                }\r
2587             }\r
2588          }\r
2589       }\r
2590       HDL_INFO \r
2591       {\r
2592          Precompiled_Simulation_Library_Files = "";\r
2593          Simulation_HDL_Files = "";\r
2594          Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sysid.vhd";\r
2595          Synthesis_Only_Files = "";\r
2596       }\r
2597       PORT_WIRING \r
2598       {\r
2599       }\r
2600    }\r
2601    MODULE LED_Pio\r
2602    {\r
2603       SLAVE s1\r
2604       {\r
2605          PORT_WIRING \r
2606          {\r
2607             PORT clk\r
2608             {\r
2609                type = "clk";\r
2610                width = "1";\r
2611                direction = "input";\r
2612                Is_Enabled = "1";\r
2613             }\r
2614             PORT reset_n\r
2615             {\r
2616                type = "reset_n";\r
2617                width = "1";\r
2618                direction = "input";\r
2619                Is_Enabled = "1";\r
2620             }\r
2621             PORT address\r
2622             {\r
2623                type = "address";\r
2624                width = "2";\r
2625                direction = "input";\r
2626                Is_Enabled = "1";\r
2627             }\r
2628             PORT write_n\r
2629             {\r
2630                type = "write_n";\r
2631                width = "1";\r
2632                direction = "input";\r
2633                Is_Enabled = "1";\r
2634             }\r
2635             PORT writedata\r
2636             {\r
2637                type = "writedata";\r
2638                width = "8";\r
2639                direction = "input";\r
2640                Is_Enabled = "1";\r
2641             }\r
2642             PORT chipselect\r
2643             {\r
2644                type = "chipselect";\r
2645                width = "1";\r
2646                direction = "input";\r
2647                Is_Enabled = "1";\r
2648             }\r
2649          }\r
2650          SYSTEM_BUILDER_INFO \r
2651          {\r
2652             Bus_Type = "avalon";\r
2653             Write_Wait_States = "0cycles";\r
2654             Read_Wait_States = "1cycles";\r
2655             Hold_Time = "0cycles";\r
2656             Setup_Time = "0cycles";\r
2657             Is_Printable_Device = "0";\r
2658             Address_Alignment = "native";\r
2659             Well_Behaved_Waitrequest = "0";\r
2660             Is_Nonvolatile_Storage = "0";\r
2661             Read_Latency = "0";\r
2662             Is_Memory_Device = "0";\r
2663             Maximum_Pending_Read_Transactions = "0";\r
2664             Minimum_Uninterrupted_Run_Length = "1";\r
2665             Accepts_Internal_Connections = "1";\r
2666             Write_Latency = "0";\r
2667             Is_Flash = "0";\r
2668             Data_Width = "8";\r
2669             Address_Width = "2";\r
2670             Maximum_Burst_Size = "1";\r
2671             Register_Incoming_Signals = "0";\r
2672             Register_Outgoing_Signals = "0";\r
2673             Interleave_Bursts = "0";\r
2674             Linewrap_Bursts = "0";\r
2675             Burst_On_Burst_Boundaries_Only = "0";\r
2676             Always_Burst_Max_Burst = "0";\r
2677             Is_Big_Endian = "0";\r
2678             Is_Enabled = "1";\r
2679             MASTERED_BY cpu_0/data_master\r
2680             {\r
2681                priority = "1";\r
2682                Offset_Address = "0x00900080";\r
2683             }\r
2684             Base_Address = "0x00900080";\r
2685             Has_IRQ = "0";\r
2686             Address_Group = "0";\r
2687             IRQ_MASTER cpu_0/data_master\r
2688             {\r
2689                IRQ_Number = "NC";\r
2690             }\r
2691             Is_Readable = "0";\r
2692             Is_Writable = "1";\r
2693          }\r
2694       }\r
2695       PORT_WIRING \r
2696       {\r
2697          PORT out_port\r
2698          {\r
2699             type = "export";\r
2700             width = "8";\r
2701             direction = "output";\r
2702             Is_Enabled = "1";\r
2703          }\r
2704          PORT in_port\r
2705          {\r
2706             direction = "input";\r
2707             Is_Enabled = "0";\r
2708             width = "8";\r
2709          }\r
2710          PORT bidir_port\r
2711          {\r
2712             direction = "inout";\r
2713             Is_Enabled = "0";\r
2714             width = "8";\r
2715          }\r
2716       }\r
2717       class = "altera_avalon_pio";\r
2718       class_version = "7.08";\r
2719       SYSTEM_BUILDER_INFO \r
2720       {\r
2721          Is_Enabled = "1";\r
2722          Instantiate_In_System_Module = "1";\r
2723          Wire_Test_Bench_Values = "1";\r
2724          Top_Level_Ports_Are_Enumerated = "1";\r
2725          Clock_Source = "clk";\r
2726          Has_Clock = "1";\r
2727          Date_Modified = "";\r
2728          View \r
2729          {\r
2730             MESSAGES \r
2731             {\r
2732             }\r
2733             Settings_Summary = " 8-bit PIO using <br>
2734
2735
2736                                          output pins";\r
2737          }\r
2738       }\r
2739       WIZARD_SCRIPT_ARGUMENTS \r
2740       {\r
2741          Do_Test_Bench_Wiring = "0";\r
2742          Driven_Sim_Value = "0";\r
2743          has_tri = "0";\r
2744          has_out = "1";\r
2745          has_in = "0";\r
2746          capture = "0";\r
2747          Data_Width = "8";\r
2748          reset_value = "0";\r
2749          edge_type = "NONE";\r
2750          irq_type = "NONE";\r
2751          bit_clearing_edge_register = "0";\r
2752       }\r
2753       HDL_INFO \r
2754       {\r
2755          Precompiled_Simulation_Library_Files = "";\r
2756          Simulation_HDL_Files = "";\r
2757          Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/LED_Pio.vhd";\r
2758          Synthesis_Only_Files = "";\r
2759       }\r
2760    }\r
2761    MODULE SG_Pio\r
2762    {\r
2763       SLAVE s1\r
2764       {\r
2765          PORT_WIRING \r
2766          {\r
2767             PORT clk\r
2768             {\r
2769                type = "clk";\r
2770                width = "1";\r
2771                direction = "input";\r
2772                Is_Enabled = "1";\r
2773             }\r
2774             PORT reset_n\r
2775             {\r
2776                type = "reset_n";\r
2777                width = "1";\r
2778                direction = "input";\r
2779                Is_Enabled = "1";\r
2780             }\r
2781             PORT address\r
2782             {\r
2783                type = "address";\r
2784                width = "2";\r
2785                direction = "input";\r
2786                Is_Enabled = "1";\r
2787             }\r
2788             PORT write_n\r
2789             {\r
2790                type = "write_n";\r
2791                width = "1";\r
2792                direction = "input";\r
2793                Is_Enabled = "1";\r
2794             }\r
2795             PORT writedata\r
2796             {\r
2797                type = "writedata";\r
2798                width = "14";\r
2799                direction = "input";\r
2800                Is_Enabled = "1";\r
2801             }\r
2802             PORT chipselect\r
2803             {\r
2804                type = "chipselect";\r
2805                width = "1";\r
2806                direction = "input";\r
2807                Is_Enabled = "1";\r
2808             }\r
2809          }\r
2810          SYSTEM_BUILDER_INFO \r
2811          {\r
2812             Bus_Type = "avalon";\r
2813             Write_Wait_States = "0cycles";\r
2814             Read_Wait_States = "1cycles";\r
2815             Hold_Time = "0cycles";\r
2816             Setup_Time = "0cycles";\r
2817             Is_Printable_Device = "0";\r
2818             Address_Alignment = "native";\r
2819             Well_Behaved_Waitrequest = "0";\r
2820             Is_Nonvolatile_Storage = "0";\r
2821             Read_Latency = "0";\r
2822             Is_Memory_Device = "0";\r
2823             Maximum_Pending_Read_Transactions = "0";\r
2824             Minimum_Uninterrupted_Run_Length = "1";\r
2825             Accepts_Internal_Connections = "1";\r
2826             Write_Latency = "0";\r
2827             Is_Flash = "0";\r
2828             Data_Width = "14";\r
2829             Address_Width = "2";\r
2830             Maximum_Burst_Size = "1";\r
2831             Register_Incoming_Signals = "0";\r
2832             Register_Outgoing_Signals = "0";\r
2833             Interleave_Bursts = "0";\r
2834             Linewrap_Bursts = "0";\r
2835             Burst_On_Burst_Boundaries_Only = "0";\r
2836             Always_Burst_Max_Burst = "0";\r
2837             Is_Big_Endian = "0";\r
2838             Is_Enabled = "1";\r
2839             MASTERED_BY cpu_0/data_master\r
2840             {\r
2841                priority = "1";\r
2842                Offset_Address = "0x00900090";\r
2843             }\r
2844             Base_Address = "0x00900090";\r
2845             Has_IRQ = "0";\r
2846             Address_Group = "0";\r
2847             IRQ_MASTER cpu_0/data_master\r
2848             {\r
2849                IRQ_Number = "NC";\r
2850             }\r
2851             Is_Readable = "0";\r
2852             Is_Writable = "1";\r
2853          }\r
2854       }\r
2855       PORT_WIRING \r
2856       {\r
2857          PORT out_port\r
2858          {\r
2859             type = "export";\r
2860             width = "14";\r
2861             direction = "output";\r
2862             Is_Enabled = "1";\r
2863          }\r
2864          PORT in_port\r
2865          {\r
2866             direction = "input";\r
2867             Is_Enabled = "0";\r
2868             width = "14";\r
2869          }\r
2870          PORT bidir_port\r
2871          {\r
2872             direction = "inout";\r
2873             Is_Enabled = "0";\r
2874             width = "14";\r
2875          }\r
2876       }\r
2877       class = "altera_avalon_pio";\r
2878       class_version = "7.08";\r
2879       SYSTEM_BUILDER_INFO \r
2880       {\r
2881          Is_Enabled = "1";\r
2882          Instantiate_In_System_Module = "1";\r
2883          Wire_Test_Bench_Values = "1";\r
2884          Top_Level_Ports_Are_Enumerated = "1";\r
2885          Clock_Source = "clk";\r
2886          Has_Clock = "1";\r
2887          Date_Modified = "";\r
2888          View \r
2889          {\r
2890             MESSAGES \r
2891             {\r
2892             }\r
2893             Settings_Summary = " 14-bit PIO using <br>
2894
2895
2896                                          output pins";\r
2897          }\r
2898       }\r
2899       WIZARD_SCRIPT_ARGUMENTS \r
2900       {\r
2901          Do_Test_Bench_Wiring = "0";\r
2902          Driven_Sim_Value = "0";\r
2903          has_tri = "0";\r
2904          has_out = "1";\r
2905          has_in = "0";\r
2906          capture = "0";\r
2907          Data_Width = "14";\r
2908          reset_value = "0";\r
2909          edge_type = "NONE";\r
2910          irq_type = "NONE";\r
2911          bit_clearing_edge_register = "0";\r
2912       }\r
2913       HDL_INFO \r
2914       {\r
2915          Precompiled_Simulation_Library_Files = "";\r
2916          Simulation_HDL_Files = "";\r
2917          Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/SG_Pio.vhd";\r
2918          Synthesis_Only_Files = "";\r
2919       }\r
2920    }\r
2921    MODULE IO_Pio\r
2922    {\r
2923       SLAVE s1\r
2924       {\r
2925          PORT_WIRING \r
2926          {\r
2927             PORT clk\r
2928             {\r
2929                type = "clk";\r
2930                width = "1";\r
2931                direction = "input";\r
2932                Is_Enabled = "1";\r
2933             }\r
2934             PORT reset_n\r
2935             {\r
2936                type = "reset_n";\r
2937                width = "1";\r
2938                direction = "input";\r
2939                Is_Enabled = "1";\r
2940             }\r
2941             PORT address\r
2942             {\r
2943                type = "address";\r
2944                width = "2";\r
2945                direction = "input";\r
2946                Is_Enabled = "1";\r
2947             }\r
2948             PORT write_n\r
2949             {\r
2950                type = "write_n";\r
2951                width = "1";\r
2952                direction = "input";\r
2953                Is_Enabled = "1";\r
2954             }\r
2955             PORT writedata\r
2956             {\r
2957                type = "writedata";\r
2958                width = "32";\r
2959                direction = "input";\r
2960                Is_Enabled = "1";\r
2961             }\r
2962             PORT chipselect\r
2963             {\r
2964                type = "chipselect";\r
2965                width = "1";\r
2966                direction = "input";\r
2967                Is_Enabled = "1";\r
2968             }\r
2969             PORT readdata\r
2970             {\r
2971                type = "readdata";\r
2972                width = "32";\r
2973                direction = "output";\r
2974                Is_Enabled = "1";\r
2975             }\r
2976          }\r
2977          SYSTEM_BUILDER_INFO \r
2978          {\r
2979             Bus_Type = "avalon";\r
2980             Write_Wait_States = "0cycles";\r
2981             Read_Wait_States = "1cycles";\r
2982             Hold_Time = "0cycles";\r
2983             Setup_Time = "0cycles";\r
2984             Is_Printable_Device = "0";\r
2985             Address_Alignment = "native";\r
2986             Well_Behaved_Waitrequest = "0";\r
2987             Is_Nonvolatile_Storage = "0";\r
2988             Read_Latency = "0";\r
2989             Is_Memory_Device = "0";\r
2990             Maximum_Pending_Read_Transactions = "0";\r
2991             Minimum_Uninterrupted_Run_Length = "1";\r
2992             Accepts_Internal_Connections = "1";\r
2993             Write_Latency = "0";\r
2994             Is_Flash = "0";\r
2995             Data_Width = "32";\r
2996             Address_Width = "2";\r
2997             Maximum_Burst_Size = "1";\r
2998             Register_Incoming_Signals = "0";\r
2999             Register_Outgoing_Signals = "0";\r
3000             Interleave_Bursts = "0";\r
3001             Linewrap_Bursts = "0";\r
3002             Burst_On_Burst_Boundaries_Only = "0";\r
3003             Always_Burst_Max_Burst = "0";\r
3004             Is_Big_Endian = "0";\r
3005             Is_Enabled = "1";\r
3006             MASTERED_BY cpu_0/data_master\r
3007             {\r
3008                priority = "1";\r
3009                Offset_Address = "0x009000a0";\r
3010             }\r
3011             Base_Address = "0x009000a0";\r
3012             Has_IRQ = "0";\r
3013             Address_Group = "0";\r
3014             IRQ_MASTER cpu_0/data_master\r
3015             {\r
3016                IRQ_Number = "NC";\r
3017             }\r
3018             Is_Readable = "1";\r
3019             Is_Writable = "1";\r
3020          }\r
3021       }\r
3022       PORT_WIRING \r
3023       {\r
3024          PORT bidir_port\r
3025          {\r
3026             type = "export";\r
3027             width = "32";\r
3028             direction = "inout";\r
3029             Is_Enabled = "1";\r
3030          }\r
3031          PORT in_port\r
3032          {\r
3033             direction = "input";\r
3034             Is_Enabled = "0";\r
3035             width = "32";\r
3036          }\r
3037          PORT out_port\r
3038          {\r
3039             direction = "output";\r
3040             Is_Enabled = "0";\r
3041             width = "32";\r
3042          }\r
3043       }\r
3044       class = "altera_avalon_pio";\r
3045       class_version = "7.08";\r
3046       SYSTEM_BUILDER_INFO \r
3047       {\r
3048          Is_Enabled = "1";\r
3049          Instantiate_In_System_Module = "1";\r
3050          Wire_Test_Bench_Values = "1";\r
3051          Top_Level_Ports_Are_Enumerated = "1";\r
3052          Clock_Source = "clk";\r
3053          Has_Clock = "1";\r
3054          Date_Modified = "";\r
3055          View \r
3056          {\r
3057             MESSAGES \r
3058             {\r
3059             }\r
3060             Settings_Summary = " 32-bit PIO using <br>
3061                                          tri-state pins with edge type NONE and interrupt source NONE
3062
3063                                         ";\r
3064          }\r
3065       }\r
3066       WIZARD_SCRIPT_ARGUMENTS \r
3067       {\r
3068          Do_Test_Bench_Wiring = "0";\r
3069          Driven_Sim_Value = "0";\r
3070          has_tri = "1";\r
3071          has_out = "0";\r
3072          has_in = "0";\r
3073          capture = "0";\r
3074          Data_Width = "32";\r
3075          reset_value = "0";\r
3076          edge_type = "NONE";\r
3077          irq_type = "NONE";\r
3078          bit_clearing_edge_register = "0";\r
3079       }\r
3080       HDL_INFO \r
3081       {\r
3082          Precompiled_Simulation_Library_Files = "";\r
3083          Simulation_HDL_Files = "";\r
3084          Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/IO_Pio.vhd";\r
3085          Synthesis_Only_Files = "";\r
3086       }\r
3087    }\r
3088    MODULE Button_Pio\r
3089    {\r
3090       SLAVE s1\r
3091       {\r
3092          PORT_WIRING \r
3093          {\r
3094             PORT clk\r
3095             {\r
3096                type = "clk";\r
3097                width = "1";\r
3098                direction = "input";\r
3099                Is_Enabled = "1";\r
3100             }\r
3101             PORT reset_n\r
3102             {\r
3103                type = "reset_n";\r
3104                width = "1";\r
3105                direction = "input";\r
3106                Is_Enabled = "1";\r
3107             }\r
3108             PORT address\r
3109             {\r
3110                type = "address";\r
3111                width = "2";\r
3112                direction = "input";\r
3113                Is_Enabled = "1";\r
3114             }\r
3115             PORT readdata\r
3116             {\r
3117                type = "readdata";\r
3118                width = "9";\r
3119                direction = "output";\r
3120                Is_Enabled = "1";\r
3121             }\r
3122          }\r
3123          SYSTEM_BUILDER_INFO \r
3124          {\r
3125             Bus_Type = "avalon";\r
3126             Write_Wait_States = "0cycles";\r
3127             Read_Wait_States = "1cycles";\r
3128             Hold_Time = "0cycles";\r
3129             Setup_Time = "0cycles";\r
3130             Is_Printable_Device = "0";\r
3131             Address_Alignment = "native";\r
3132             Well_Behaved_Waitrequest = "0";\r
3133             Is_Nonvolatile_Storage = "0";\r
3134             Read_Latency = "0";\r
3135             Is_Memory_Device = "0";\r
3136             Maximum_Pending_Read_Transactions = "0";\r
3137             Minimum_Uninterrupted_Run_Length = "1";\r
3138             Accepts_Internal_Connections = "1";\r
3139             Write_Latency = "0";\r
3140             Is_Flash = "0";\r
3141             Data_Width = "9";\r
3142             Address_Width = "2";\r
3143             Maximum_Burst_Size = "1";\r
3144             Register_Incoming_Signals = "0";\r
3145             Register_Outgoing_Signals = "0";\r
3146             Interleave_Bursts = "0";\r
3147             Linewrap_Bursts = "0";\r
3148             Burst_On_Burst_Boundaries_Only = "0";\r
3149             Always_Burst_Max_Burst = "0";\r
3150             Is_Big_Endian = "0";\r
3151             Is_Enabled = "1";\r
3152             MASTERED_BY cpu_0/data_master\r
3153             {\r
3154                priority = "1";\r
3155                Offset_Address = "0x009000b0";\r
3156             }\r
3157             Base_Address = "0x009000b0";\r
3158             Has_IRQ = "0";\r
3159             Address_Group = "0";\r
3160             IRQ_MASTER cpu_0/data_master\r
3161             {\r
3162                IRQ_Number = "NC";\r
3163             }\r
3164             Is_Readable = "1";\r
3165             Is_Writable = "0";\r
3166          }\r
3167       }\r
3168       PORT_WIRING \r
3169       {\r
3170          PORT in_port\r
3171          {\r
3172             type = "export";\r
3173             width = "9";\r
3174             direction = "input";\r
3175             Is_Enabled = "1";\r
3176          }\r
3177          PORT out_port\r
3178          {\r
3179             direction = "output";\r
3180             Is_Enabled = "0";\r
3181             width = "9";\r
3182          }\r
3183          PORT bidir_port\r
3184          {\r
3185             direction = "inout";\r
3186             Is_Enabled = "0";\r
3187             width = "9";\r
3188          }\r
3189       }\r
3190       class = "altera_avalon_pio";\r
3191       class_version = "7.08";\r
3192       SYSTEM_BUILDER_INFO \r
3193       {\r
3194          Is_Enabled = "1";\r
3195          Instantiate_In_System_Module = "1";\r
3196          Wire_Test_Bench_Values = "1";\r
3197          Top_Level_Ports_Are_Enumerated = "1";\r
3198          Clock_Source = "clk";\r
3199          Has_Clock = "1";\r
3200          Date_Modified = "";\r
3201          View \r
3202          {\r
3203             MESSAGES \r
3204             {\r
3205             }\r
3206             Settings_Summary = " 9-bit PIO using <br>
3207
3208                                          input pins with edge type NONE and interrupt source NONE
3209                                         ";\r
3210          }\r
3211       }\r
3212       WIZARD_SCRIPT_ARGUMENTS \r
3213       {\r
3214          Do_Test_Bench_Wiring = "0";\r
3215          Driven_Sim_Value = "0";\r
3216          has_tri = "0";\r
3217          has_out = "0";\r
3218          has_in = "1";\r
3219          capture = "0";\r
3220          Data_Width = "9";\r
3221          reset_value = "0";\r
3222          edge_type = "NONE";\r
3223          irq_type = "NONE";\r
3224          bit_clearing_edge_register = "0";\r
3225       }\r
3226       HDL_INFO \r
3227       {\r
3228          Precompiled_Simulation_Library_Files = "";\r
3229          Simulation_HDL_Files = "";\r
3230          Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/Button_Pio.vhd";\r
3231          Synthesis_Only_Files = "";\r
3232       }\r
3233    }\r
3234    MODULE uart\r
3235    {\r
3236       SLAVE s1\r
3237       {\r
3238          PORT_WIRING \r
3239          {\r
3240             PORT clk\r
3241             {\r
3242                type = "clk";\r
3243                width = "1";\r
3244                direction = "input";\r
3245                Is_Enabled = "1";\r
3246             }\r
3247             PORT reset_n\r
3248             {\r
3249                type = "reset_n";\r
3250                width = "1";\r
3251                direction = "input";\r
3252                Is_Enabled = "1";\r
3253             }\r
3254             PORT irq\r
3255             {\r
3256                type = "irq";\r
3257                width = "1";\r
3258                direction = "output";\r
3259                Is_Enabled = "1";\r
3260             }\r
3261             PORT address\r
3262             {\r
3263                type = "address";\r
3264                width = "3";\r
3265                direction = "input";\r
3266                Is_Enabled = "1";\r
3267             }\r
3268             PORT begintransfer\r
3269             {\r
3270                type = "begintransfer";\r
3271                width = "1";\r
3272                direction = "input";\r
3273                Is_Enabled = "1";\r
3274             }\r
3275             PORT chipselect\r
3276             {\r
3277                type = "chipselect";\r
3278                width = "1";\r
3279                direction = "input";\r
3280                Is_Enabled = "1";\r
3281             }\r
3282             PORT read_n\r
3283             {\r
3284                type = "read_n";\r
3285                width = "1";\r
3286                direction = "input";\r
3287                Is_Enabled = "1";\r
3288             }\r
3289             PORT write_n\r
3290             {\r
3291                type = "write_n";\r
3292                width = "1";\r
3293                direction = "input";\r
3294                Is_Enabled = "1";\r
3295             }\r
3296             PORT writedata\r
3297             {\r
3298                type = "writedata";\r
3299                width = "16";\r
3300                direction = "input";\r
3301                Is_Enabled = "1";\r
3302             }\r
3303             PORT readdata\r
3304             {\r
3305                type = "readdata";\r
3306                width = "16";\r
3307                direction = "output";\r
3308                Is_Enabled = "1";\r
3309             }\r
3310             PORT dataavailable\r
3311             {\r
3312                type = "dataavailable";\r
3313                width = "1";\r
3314                direction = "output";\r
3315                Is_Enabled = "1";\r
3316             }\r
3317             PORT readyfordata\r
3318             {\r
3319                type = "readyfordata";\r
3320                width = "1";\r
3321                direction = "output";\r
3322                Is_Enabled = "1";\r
3323             }\r
3324          }\r
3325          SYSTEM_BUILDER_INFO \r
3326          {\r
3327             Has_IRQ = "1";\r
3328             Bus_Type = "avalon";\r
3329             Write_Wait_States = "1cycles";\r
3330             Read_Wait_States = "1cycles";\r
3331             Hold_Time = "0cycles";\r
3332             Setup_Time = "0cycles";\r
3333             Is_Printable_Device = "1";\r
3334             Address_Alignment = "native";\r
3335             Well_Behaved_Waitrequest = "0";\r
3336             Is_Nonvolatile_Storage = "0";\r
3337             Read_Latency = "0";\r
3338             Is_Memory_Device = "0";\r
3339             Maximum_Pending_Read_Transactions = "0";\r
3340             Minimum_Uninterrupted_Run_Length = "1";\r
3341             Accepts_Internal_Connections = "1";\r
3342             Write_Latency = "0";\r
3343             Is_Flash = "0";\r
3344             Data_Width = "16";\r
3345             Address_Width = "3";\r
3346             Maximum_Burst_Size = "1";\r
3347             Register_Incoming_Signals = "0";\r
3348             Register_Outgoing_Signals = "0";\r
3349             Interleave_Bursts = "0";\r
3350             Linewrap_Bursts = "0";\r
3351             Burst_On_Burst_Boundaries_Only = "0";\r
3352             Always_Burst_Max_Burst = "0";\r
3353             Is_Big_Endian = "0";\r
3354             Is_Enabled = "1";\r
3355             MASTERED_BY cpu_0/data_master\r
3356             {\r
3357                priority = "1";\r
3358                Offset_Address = "0x00900040";\r
3359             }\r
3360             IRQ_MASTER cpu_0/data_master\r
3361             {\r
3362                IRQ_Number = "0";\r
3363             }\r
3364             Base_Address = "0x00900040";\r
3365             Address_Group = "0";\r
3366          }\r
3367       }\r
3368       PORT_WIRING \r
3369       {\r
3370          PORT rxd\r
3371          {\r
3372             type = "export";\r
3373             width = "1";\r
3374             direction = "input";\r
3375             Is_Enabled = "1";\r
3376          }\r
3377          PORT txd\r
3378          {\r
3379             type = "export";\r
3380             width = "1";\r
3381             direction = "output";\r
3382             Is_Enabled = "1";\r
3383          }\r
3384          PORT cts_n\r
3385          {\r
3386             direction = "input";\r
3387             width = "1";\r
3388             Is_Enabled = "0";\r
3389          }\r
3390          PORT rts_n\r
3391          {\r
3392             direction = "output";\r
3393             width = "1";\r
3394             Is_Enabled = "0";\r
3395          }\r
3396       }\r
3397       class = "altera_avalon_uart";\r
3398       class_version = "7.08";\r
3399       iss_model_name = "altera_avalon_uart";\r
3400       SYSTEM_BUILDER_INFO \r
3401       {\r
3402          Instantiate_In_System_Module = "1";\r
3403          Is_Enabled = "1";\r
3404          Iss_Launch_Telnet = "0";\r
3405          Top_Level_Ports_Are_Enumerated = "1";\r
3406          View \r
3407          {\r
3408             Settings_Summary = "8-bit UART with 115200 baud, <br>
3409                     1 stop bits and N parity";\r
3410             Is_Collapsed = "1";\r
3411             MESSAGES \r
3412             {\r
3413             }\r
3414          }\r
3415          Clock_Source = "clk";\r
3416          Has_Clock = "1";\r
3417       }\r
3418       SIMULATION \r
3419       {\r
3420          DISPLAY \r
3421          {\r
3422             SIGNAL a\r
3423             {\r
3424                name = "  Bus Interface";\r
3425                format = "Divider";\r
3426             }\r
3427             SIGNAL b\r
3428             {\r
3429                name = "chipselect";\r
3430             }\r
3431             SIGNAL c\r
3432             {\r
3433                name = "address";\r
3434                radix = "hexadecimal";\r
3435             }\r
3436             SIGNAL d\r
3437             {\r
3438                name = "writedata";\r
3439                radix = "hexadecimal";\r
3440             }\r
3441             SIGNAL e\r
3442             {\r
3443                name = "readdata";\r
3444                radix = "hexadecimal";\r
3445             }\r
3446             SIGNAL f\r
3447             {\r
3448                name = "  Internals";\r
3449                format = "Divider";\r
3450             }\r
3451             SIGNAL g\r
3452             {\r
3453                name = "tx_ready";\r
3454             }\r
3455             SIGNAL h\r
3456             {\r
3457                name = "tx_data";\r
3458                radix = "ascii";\r
3459             }\r
3460             SIGNAL i\r
3461             {\r
3462                name = "rx_char_ready";\r
3463             }\r
3464             SIGNAL j\r
3465             {\r
3466                name = "rx_data";\r
3467                radix = "ascii";\r
3468             }\r
3469          }\r
3470          INTERACTIVE_OUT log\r
3471          {\r
3472             enable = "0";\r
3473             file = "_log_module.txt";\r
3474             radix = "ascii";\r
3475             signals = "temp,list";\r
3476             exe = "perl -- tail-f.pl";\r
3477          }\r
3478          INTERACTIVE_IN drive\r
3479          {\r
3480             enable = "0";\r
3481             file = "_input_data_stream.dat";\r
3482             mutex = "_input_data_mutex.dat";\r
3483             log = "_in.log";\r
3484             rate = "100";\r
3485             signals = "temp,list";\r
3486             exe = "perl -- uart.pl";\r
3487          }\r
3488       }\r
3489       WIZARD_SCRIPT_ARGUMENTS \r
3490       {\r
3491          baud = "115200";\r
3492          data_bits = "8";\r
3493          fixed_baud = "1";\r
3494          parity = "N";\r
3495          stop_bits = "1";\r
3496          use_cts_rts = "0";\r
3497          use_eop_register = "0";\r
3498          sim_true_baud = "0";\r
3499          sim_char_stream = "";\r
3500       }\r
3501       HDL_INFO \r
3502       {\r
3503          Precompiled_Simulation_Library_Files = "";\r
3504          Simulation_HDL_Files = "";\r
3505          Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/uart.vhd";\r
3506          Synthesis_Only_Files = "";\r
3507       }\r
3508    }\r
3509    MODULE LM74_Pio\r
3510    {\r
3511       SLAVE s1\r
3512       {\r
3513          PORT_WIRING \r
3514          {\r
3515             PORT clk\r
3516             {\r
3517                type = "clk";\r
3518                width = "1";\r
3519                direction = "input";\r
3520                Is_Enabled = "1";\r
3521             }\r
3522             PORT reset_n\r
3523             {\r
3524                type = "reset_n";\r
3525                width = "1";\r
3526                direction = "input";\r
3527                Is_Enabled = "1";\r
3528             }\r
3529             PORT address\r
3530             {\r
3531                type = "address";\r
3532                width = "2";\r
3533                direction = "input";\r
3534                Is_Enabled = "1";\r
3535             }\r
3536             PORT write_n\r
3537             {\r
3538                type = "write_n";\r
3539                width = "1";\r
3540                direction = "input";\r
3541                Is_Enabled = "1";\r
3542             }\r
3543             PORT writedata\r
3544             {\r
3545                type = "writedata";\r
3546                width = "3";\r
3547                direction = "input";\r
3548                Is_Enabled = "1";\r
3549             }\r
3550             PORT chipselect\r
3551             {\r
3552                type = "chipselect";\r
3553                width = "1";\r
3554                direction = "input";\r
3555                Is_Enabled = "1";\r
3556             }\r
3557             PORT readdata\r
3558             {\r
3559                type = "readdata";\r
3560                width = "3";\r
3561                direction = "output";\r
3562                Is_Enabled = "1";\r
3563             }\r
3564          }\r
3565          SYSTEM_BUILDER_INFO \r
3566          {\r
3567             Bus_Type = "avalon";\r
3568             Write_Wait_States = "0cycles";\r
3569             Read_Wait_States = "1cycles";\r
3570             Hold_Time = "0cycles";\r
3571             Setup_Time = "0cycles";\r
3572             Is_Printable_Device = "0";\r
3573             Address_Alignment = "native";\r
3574             Well_Behaved_Waitrequest = "0";\r
3575             Is_Nonvolatile_Storage = "0";\r
3576             Read_Latency = "0";\r
3577             Is_Memory_Device = "0";\r
3578             Maximum_Pending_Read_Transactions = "0";\r
3579             Minimum_Uninterrupted_Run_Length = "1";\r
3580             Accepts_Internal_Connections = "1";\r
3581             Write_Latency = "0";\r
3582             Is_Flash = "0";\r
3583             Data_Width = "3";\r
3584             Address_Width = "2";\r
3585             Maximum_Burst_Size = "1";\r
3586             Register_Incoming_Signals = "0";\r
3587             Register_Outgoing_Signals = "0";\r
3588             Interleave_Bursts = "0";\r
3589             Linewrap_Bursts = "0";\r
3590             Burst_On_Burst_Boundaries_Only = "0";\r
3591             Always_Burst_Max_Burst = "0";\r
3592             Is_Big_Endian = "0";\r
3593             Is_Enabled = "1";\r
3594             MASTERED_BY cpu_0/data_master\r
3595             {\r
3596                priority = "1";\r
3597                Offset_Address = "0x009000c0";\r
3598             }\r
3599             Base_Address = "0x009000c0";\r
3600             Has_IRQ = "0";\r
3601             Address_Group = "0";\r
3602             IRQ_MASTER cpu_0/data_master\r
3603             {\r
3604                IRQ_Number = "NC";\r
3605             }\r
3606             Is_Readable = "1";\r
3607             Is_Writable = "1";\r
3608          }\r
3609       }\r
3610       PORT_WIRING \r
3611       {\r
3612          PORT bidir_port\r
3613          {\r
3614             type = "export";\r
3615             width = "3";\r
3616             direction = "inout";\r
3617             Is_Enabled = "1";\r
3618          }\r
3619          PORT in_port\r
3620          {\r
3621             direction = "input";\r
3622             Is_Enabled = "0";\r
3623             width = "3";\r
3624          }\r
3625          PORT out_port\r
3626          {\r
3627             direction = "output";\r
3628             Is_Enabled = "0";\r
3629             width = "3";\r
3630          }\r
3631       }\r
3632       class = "altera_avalon_pio";\r
3633       class_version = "7.08";\r
3634       SYSTEM_BUILDER_INFO \r
3635       {\r
3636          Is_Enabled = "1";\r
3637          Instantiate_In_System_Module = "1";\r
3638          Wire_Test_Bench_Values = "1";\r
3639          Top_Level_Ports_Are_Enumerated = "1";\r
3640          Clock_Source = "clk";\r
3641          Has_Clock = "1";\r
3642          Date_Modified = "";\r
3643          View \r
3644          {\r
3645             MESSAGES \r
3646             {\r
3647             }\r
3648             Settings_Summary = " 3-bit PIO using <br>
3649                                          tri-state pins with edge type NONE and interrupt source NONE
3650
3651                                         ";\r
3652          }\r
3653       }\r
3654       WIZARD_SCRIPT_ARGUMENTS \r
3655       {\r
3656          Do_Test_Bench_Wiring = "0";\r
3657          Driven_Sim_Value = "0";\r
3658          has_tri = "1";\r
3659          has_out = "0";\r
3660          has_in = "0";\r
3661          capture = "0";\r
3662          Data_Width = "3";\r
3663          reset_value = "0";\r
3664          edge_type = "NONE";\r
3665          irq_type = "NONE";\r
3666          bit_clearing_edge_register = "0";\r
3667       }\r
3668       HDL_INFO \r
3669       {\r
3670          Precompiled_Simulation_Library_Files = "";\r
3671          Simulation_HDL_Files = "";\r
3672          Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/LM74_Pio.vhd";\r
3673          Synthesis_Only_Files = "";\r
3674       }\r
3675    }\r
3676    MODULE epcs_controller\r
3677    {\r
3678       SLAVE epcs_control_port\r
3679       {\r
3680          PORT_WIRING \r
3681          {\r
3682             PORT clk\r
3683             {\r
3684                type = "clk";\r
3685                width = "1";\r
3686                direction = "input";\r
3687                Is_Enabled = "1";\r
3688             }\r
3689             PORT reset_n\r
3690             {\r
3691                type = "reset_n";\r
3692                width = "1";\r
3693                direction = "input";\r
3694                Is_Enabled = "1";\r
3695             }\r
3696             PORT irq\r
3697             {\r
3698                type = "irq";\r
3699                width = "1";\r
3700                direction = "output";\r
3701                Is_Enabled = "1";\r
3702             }\r
3703             PORT address\r
3704             {\r
3705                type = "address";\r
3706                width = "9";\r
3707                direction = "input";\r
3708                Is_Enabled = "1";\r
3709             }\r
3710             PORT chipselect\r
3711             {\r
3712                type = "chipselect";\r
3713                width = "1";\r
3714                direction = "input";\r
3715                Is_Enabled = "1";\r
3716             }\r
3717             PORT dataavailable\r
3718             {\r
3719                type = "dataavailable";\r
3720                width = "1";\r
3721                direction = "output";\r
3722                Is_Enabled = "1";\r
3723             }\r
3724             PORT endofpacket\r
3725             {\r
3726                type = "endofpacket";\r
3727                width = "1";\r
3728                direction = "output";\r
3729                Is_Enabled = "1";\r
3730             }\r
3731             PORT read_n\r
3732             {\r
3733                type = "read_n";\r
3734                width = "1";\r
3735                direction = "input";\r
3736                Is_Enabled = "1";\r
3737             }\r
3738             PORT readdata\r
3739             {\r
3740                type = "readdata";\r
3741                width = "32";\r
3742                direction = "output";\r
3743                Is_Enabled = "1";\r
3744             }\r
3745             PORT readyfordata\r
3746             {\r
3747                type = "readyfordata";\r
3748                width = "1";\r
3749                direction = "output";\r
3750                Is_Enabled = "1";\r
3751             }\r
3752             PORT write_n\r
3753             {\r
3754                type = "write_n";\r
3755                width = "1";\r
3756                direction = "input";\r
3757                Is_Enabled = "1";\r
3758             }\r
3759             PORT writedata\r
3760             {\r
3761                type = "writedata";\r
3762                width = "32";\r
3763                direction = "input";\r
3764                Is_Enabled = "1";\r
3765             }\r
3766             PORT data_from_cpu\r
3767             {\r
3768                Is_Enabled = "0";\r
3769                direction = "input";\r
3770                type = "writedata";\r
3771                width = "16";\r
3772             }\r
3773             PORT data_to_cpu\r
3774             {\r
3775                Is_Enabled = "0";\r
3776                direction = "output";\r
3777                type = "readdata";\r
3778                width = "16";\r
3779             }\r
3780             PORT epcs_select\r
3781             {\r
3782                Is_Enabled = "0";\r
3783                direction = "input";\r
3784                type = "chipselect";\r
3785                width = "1";\r
3786             }\r
3787             PORT mem_addr\r
3788             {\r
3789                Is_Enabled = "0";\r
3790                direction = "input";\r
3791                type = "address";\r
3792                width = "3";\r
3793             }\r
3794          }\r
3795          SYSTEM_BUILDER_INFO \r
3796          {\r
3797             Has_IRQ = "1";\r
3798             Bus_Type = "avalon";\r
3799             Write_Wait_States = "1cycles";\r
3800             Read_Wait_States = "1cycles";\r
3801             Hold_Time = "0cycles";\r
3802             Setup_Time = "0cycles";\r
3803             Is_Printable_Device = "0";\r
3804             Address_Alignment = "dynamic";\r
3805             Well_Behaved_Waitrequest = "0";\r
3806             Is_Nonvolatile_Storage = "1";\r
3807             Address_Span = "2048";\r
3808             Read_Latency = "0";\r
3809             Is_Memory_Device = "1";\r
3810             Maximum_Pending_Read_Transactions = "0";\r
3811             Minimum_Uninterrupted_Run_Length = "1";\r
3812             Accepts_Internal_Connections = "1";\r
3813             Write_Latency = "0";\r
3814             Is_Flash = "1";\r
3815             Data_Width = "32";\r
3816             Address_Width = "9";\r
3817             Maximum_Burst_Size = "1";\r
3818             Register_Incoming_Signals = "0";\r
3819             Register_Outgoing_Signals = "0";\r
3820             Interleave_Bursts = "0";\r
3821             Linewrap_Bursts = "0";\r
3822             Burst_On_Burst_Boundaries_Only = "0";\r
3823             Always_Burst_Max_Burst = "0";\r
3824             Is_Big_Endian = "0";\r
3825             Is_Enabled = "1";\r
3826             MASTERED_BY cpu_0/instruction_master\r
3827             {\r
3828                priority = "1";\r
3829                Offset_Address = "0x00906000";\r
3830             }\r
3831             MASTERED_BY cpu_0/data_master\r
3832             {\r
3833                priority = "1";\r
3834                Offset_Address = "0x00906000";\r
3835             }\r
3836             IRQ_MASTER cpu_0/data_master\r
3837             {\r
3838                IRQ_Number = "2";\r
3839             }\r
3840             Base_Address = "0x00906000";\r
3841             Address_Group = "0";\r
3842          }\r
3843          WIZARD_SCRIPT_ARGUMENTS \r
3844          {\r
3845             class = "altera_avalon_epcs_flash_controller";\r
3846             flash_reference_designator = "";\r
3847          }\r
3848       }\r
3849       PORT_WIRING \r
3850       {\r
3851          PORT dclk\r
3852          {\r
3853             type = "export";\r
3854             width = "1";\r
3855             direction = "output";\r
3856             Is_Enabled = "1";\r
3857          }\r
3858          PORT sce\r
3859          {\r
3860             type = "export";\r
3861             width = "1";\r
3862             direction = "output";\r
3863             Is_Enabled = "1";\r
3864          }\r
3865          PORT sdo\r
3866          {\r
3867             type = "export";\r
3868             width = "1";\r
3869             direction = "output";\r
3870             Is_Enabled = "1";\r
3871          }\r
3872          PORT data0\r
3873          {\r
3874             type = "export";\r
3875             width = "1";\r
3876             direction = "input";\r
3877             Is_Enabled = "1";\r
3878          }\r
3879       }\r
3880       WIZARD_SCRIPT_ARGUMENTS \r
3881       {\r
3882          databits = "8";\r
3883          targetclock = "20";\r
3884          clockunits = "MHz";\r
3885          clockmult = "1000000";\r
3886          numslaves = "1";\r
3887          ismaster = "1";\r
3888          clockpolarity = "0";\r
3889          clockphase = "0";\r
3890          lsbfirst = "0";\r
3891          extradelay = "0";\r
3892          targetssdelay = "100";\r
3893          delayunits = "us";\r
3894          delaymult = "1e-006";\r
3895          prefix = "epcs_";\r
3896          register_offset = "0x400";\r
3897          use_asmi_atom = "0";\r
3898          MAKE \r
3899          {\r
3900             MACRO \r
3901             {\r
3902                EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_ALT_SIM_PREFIX = "$(EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_TMP1:0=)";\r
3903                EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_TMP1 = "$(ALT_SIM_OPTIMIZE:1=RUN_ON_HDL_SIMULATOR_ONLY_)";\r
3904             }\r
3905             MASTER cpu_0\r
3906             {\r
3907                MACRO \r
3908                {\r
3909                   BOOTS_FROM_EPCS = "0";\r
3910                   BOOT_COPIER_EPCS = "boot_loader_epcs.srec";\r
3911                   CPU_CLASS = "altera_nios2";\r
3912                   CPU_RESET_ADDRESS = "0x0";\r
3913                }\r
3914             }\r
3915             TARGET delete_placeholder_warning\r
3916             {\r
3917                epcs_controller \r
3918                {\r
3919                   Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";\r
3920                   Is_Phony = "1";\r
3921                   Target_File = "do_delete_placeholder_warning";\r
3922                }\r
3923             }\r
3924             TARGET flashfiles\r
3925             {\r
3926                epcs_controller \r
3927                {\r
3928                   Command1 = "@if [ $(BOOTS_FROM_EPCS) -eq 1 ]; then echo Post-processing to create $(notdir $@) ; elf2flash --input=$(ELF) --flash= --boot=$(DBL_QUOTE)$(shell $(DBL_QUOTE)$(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir$(DBL_QUOTE) $(CPU_CLASS) $(QUARTUS_PROJECT_DIR))/$(BOOT_COPIER_EPCS)$(DBL_QUOTE) --outfile=$(EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_ALT_SIM_PREFIX)epcs_controller_boot_rom.flash --sim_optimize=$(ALT_SIM_OPTIMIZE) --epcs --base=0x0 --end=0x7FFFFFFF  ; fi";\r
3929                   Dependency = "$(ELF)";\r
3930                   Target_File = "$(EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_ALT_SIM_PREFIX)epcs_controller_boot_rom.flash";\r
3931                }\r
3932             }\r
3933             TARGET sim\r
3934             {\r
3935                epcs_controller \r
3936                {\r
3937                   Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";\r
3938                   Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";\r
3939                   Command3 = "touch $(SIMDIR)/dummy_file";\r
3940                   Dependency = "$(ELF)";\r
3941                   Target_File = "$(SIMDIR)/dummy_file";\r
3942                }\r
3943             }\r
3944          }\r
3945          clockunit = "kHz";\r
3946          delayunit = "us";\r
3947       }\r
3948       class = "altera_avalon_epcs_flash_controller";\r
3949       class_version = "7.08";\r
3950       SYSTEM_BUILDER_INFO \r
3951       {\r
3952          Is_Enabled = "1";\r
3953          Clock_Source = "clk";\r
3954          Has_Clock = "1";\r
3955          Instantiate_In_System_Module = "1";\r
3956          Required_Device_Family = "STRATIX,CYCLONE,CYCLONEII,CYCLONEIII,STRATIXIII,STRATIXII,STRATIXIIGX,ARRIAGX,STRATIXIIGXLITE";\r
3957          Fixed_Module_Name = "epcs_controller";\r
3958          Top_Level_Ports_Are_Enumerated = "1";\r
3959          View \r
3960          {\r
3961             MESSAGES \r
3962             {\r
3963             }\r
3964          }\r
3965       }\r
3966       HDL_INFO \r
3967       {\r
3968          Precompiled_Simulation_Library_Files = "";\r
3969          Simulation_HDL_Files = "";\r
3970          Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/epcs_controller.vhd";\r
3971          Synthesis_Only_Files = "";\r
3972       }\r
3973    }\r
3974    MODULE tri_state_bridge_0\r
3975    {\r
3976       SLAVE avalon_slave\r
3977       {\r
3978          PORT_WIRING \r
3979          {\r
3980          }\r
3981          SYSTEM_BUILDER_INFO \r
3982          {\r
3983             Bus_Type = "avalon";\r
3984             Write_Wait_States = "0cycles";\r
3985             Read_Wait_States = "1cycles";\r
3986             Hold_Time = "0cycles";\r
3987             Setup_Time = "0cycles";\r
3988             Is_Printable_Device = "0";\r
3989             Address_Alignment = "dynamic";\r
3990             Well_Behaved_Waitrequest = "0";\r
3991             Is_Nonvolatile_Storage = "0";\r
3992             Address_Span = "1";\r
3993             Read_Latency = "0";\r
3994             Is_Memory_Device = "0";\r
3995             Maximum_Pending_Read_Transactions = "0";\r
3996             Minimum_Uninterrupted_Run_Length = "1";\r
3997             Accepts_Internal_Connections = "1";\r
3998             Write_Latency = "0";\r
3999             Is_Flash = "0";\r
4000             Maximum_Burst_Size = "1";\r
4001             Register_Incoming_Signals = "1";\r
4002             Register_Outgoing_Signals = "1";\r
4003             Interleave_Bursts = "0";\r
4004             Linewrap_Bursts = "0";\r
4005             Burst_On_Burst_Boundaries_Only = "0";\r
4006             Always_Burst_Max_Burst = "0";\r
4007             Is_Big_Endian = "0";\r
4008             Is_Enabled = "1";\r
4009             MASTERED_BY cpu_0/data_master\r
4010             {\r
4011                priority = "1";\r
4012                Offset_Address = "0x00000000";\r
4013             }\r
4014             MASTERED_BY cpu_0/instruction_master\r
4015             {\r
4016                priority = "1";\r
4017                Offset_Address = "0x00000000";\r
4018             }\r
4019             MASTERED_BY nios_vga_inst/vga_dma\r
4020             {\r
4021                priority = "1";\r
4022                Offset_Address = "0x00000000";\r
4023             }\r
4024             Bridges_To = "tristate_master";\r
4025             Base_Address = "N/A";\r
4026             Has_IRQ = "0";\r
4027             IRQ = "N/A";\r
4028             Address_Group = "0";\r
4029             IRQ_MASTER cpu_0/data_master\r
4030             {\r
4031                IRQ_Number = "NC";\r
4032             }\r
4033          }\r
4034       }\r
4035       MASTER tristate_master\r
4036       {\r
4037          SYSTEM_BUILDER_INFO \r
4038          {\r
4039             Bus_Type = "avalon_tristate";\r
4040             Is_Asynchronous = "0";\r
4041             DBS_Big_Endian = "0";\r
4042             Adapts_To = "";\r
4043             Maximum_Burst_Size = "1";\r
4044             Register_Incoming_Signals = "0";\r
4045             Register_Outgoing_Signals = "0";\r
4046             Interleave_Bursts = "0";\r
4047             Linewrap_Bursts = "0";\r
4048             Burst_On_Burst_Boundaries_Only = "0";\r
4049             Always_Burst_Max_Burst = "0";\r
4050             Is_Big_Endian = "0";\r
4051             Is_Enabled = "1";\r
4052             Bridges_To = "avalon_slave";\r
4053          }\r
4054          PORT_WIRING \r
4055          {\r
4056          }\r
4057          MEMORY_MAP \r
4058          {\r
4059             Entry cfi_flash/s1\r
4060             {\r
4061                address = "0x00000000";\r
4062                span = "0x00800000";\r
4063                is_bridge = "0";\r
4064             }\r
4065             Entry DBC3C40_SRAM_inst/avalon_tristate_slave\r
4066             {\r
4067                address = "0x00800000";\r
4068                span = "0x00100000";\r
4069                is_bridge = "0";\r
4070             }\r
4071          }\r
4072       }\r
4073       WIZARD_SCRIPT_ARGUMENTS \r
4074       {\r
4075       }\r
4076       class = "altera_avalon_tri_state_bridge";\r
4077       class_version = "7.08";\r
4078       SYSTEM_BUILDER_INFO \r
4079       {\r
4080          Is_Enabled = "1";\r
4081          Clock_Source = "clk";\r
4082          Has_Clock = "1";\r
4083          Instantiate_In_System_Module = "1";\r
4084          Is_Bridge = "1";\r
4085          Top_Level_Ports_Are_Enumerated = "1";\r
4086          View \r
4087          {\r
4088             MESSAGES \r
4089             {\r
4090             }\r
4091          }\r
4092       }\r
4093    }\r
4094    MODULE sys_clk\r
4095    {\r
4096       SLAVE s1\r
4097       {\r
4098          PORT_WIRING \r
4099          {\r
4100             PORT clk\r
4101             {\r
4102                type = "clk";\r
4103                width = "1";\r
4104                direction = "input";\r
4105                Is_Enabled = "1";\r
4106             }\r
4107             PORT reset_n\r
4108             {\r
4109                type = "reset_n";\r
4110                width = "1";\r
4111                direction = "input";\r
4112                Is_Enabled = "1";\r
4113             }\r
4114             PORT irq\r
4115             {\r
4116                type = "irq";\r
4117                width = "1";\r
4118                direction = "output";\r
4119                Is_Enabled = "1";\r
4120             }\r
4121             PORT address\r
4122             {\r
4123                type = "address";\r
4124                width = "3";\r
4125                direction = "input";\r
4126                Is_Enabled = "1";\r
4127             }\r
4128             PORT writedata\r
4129             {\r
4130                type = "writedata";\r
4131                width = "16";\r
4132                direction = "input";\r
4133                Is_Enabled = "1";\r
4134             }\r
4135             PORT readdata\r
4136             {\r
4137                type = "readdata";\r
4138                width = "16";\r
4139                direction = "output";\r
4140                Is_Enabled = "1";\r
4141             }\r
4142             PORT chipselect\r
4143             {\r
4144                type = "chipselect";\r
4145                width = "1";\r
4146                direction = "input";\r
4147                Is_Enabled = "1";\r
4148             }\r
4149             PORT write_n\r
4150             {\r
4151                type = "write_n";\r
4152                width = "1";\r
4153                direction = "input";\r
4154                Is_Enabled = "1";\r
4155             }\r
4156          }\r
4157          SYSTEM_BUILDER_INFO \r
4158          {\r
4159             Has_IRQ = "1";\r
4160             Bus_Type = "avalon";\r
4161             Write_Wait_States = "0cycles";\r
4162             Read_Wait_States = "1cycles";\r
4163             Hold_Time = "0cycles";\r
4164             Setup_Time = "0cycles";\r
4165             Is_Printable_Device = "0";\r
4166             Address_Alignment = "native";\r
4167             Well_Behaved_Waitrequest = "0";\r
4168             Is_Nonvolatile_Storage = "0";\r
4169             Read_Latency = "0";\r
4170             Is_Memory_Device = "0";\r
4171             Maximum_Pending_Read_Transactions = "0";\r
4172             Minimum_Uninterrupted_Run_Length = "1";\r
4173             Accepts_Internal_Connections = "1";\r
4174             Write_Latency = "0";\r
4175             Is_Flash = "0";\r
4176             Data_Width = "16";\r
4177             Address_Width = "3";\r
4178             Maximum_Burst_Size = "1";\r
4179             Register_Incoming_Signals = "0";\r
4180             Register_Outgoing_Signals = "0";\r
4181             Interleave_Bursts = "0";\r
4182             Linewrap_Bursts = "0";\r
4183             Burst_On_Burst_Boundaries_Only = "0";\r
4184             Always_Burst_Max_Burst = "0";\r
4185             Is_Big_Endian = "0";\r
4186             Is_Enabled = "1";\r
4187             MASTERED_BY cpu_0/data_master\r
4188             {\r
4189                priority = "1";\r
4190                Offset_Address = "0x00900060";\r
4191             }\r
4192             IRQ_MASTER cpu_0/data_master\r
4193             {\r
4194                IRQ_Number = "3";\r
4195             }\r
4196             Base_Address = "0x00900060";\r
4197             Address_Group = "0";\r
4198          }\r
4199       }\r
4200       class = "altera_avalon_timer";\r
4201       class_version = "7.08";\r
4202       iss_model_name = "altera_avalon_timer";\r
4203       SYSTEM_BUILDER_INFO \r
4204       {\r
4205          Instantiate_In_System_Module = "1";\r
4206          Is_Enabled = "1";\r
4207          Top_Level_Ports_Are_Enumerated = "1";\r
4208          View \r
4209          {\r
4210             Settings_Summary = "Timer with 1 ms timeout period.";\r
4211             Is_Collapsed = "1";\r
4212             MESSAGES \r
4213             {\r
4214             }\r
4215          }\r
4216          Clock_Source = "clk";\r
4217          Has_Clock = "1";\r
4218       }\r
4219       WIZARD_SCRIPT_ARGUMENTS \r
4220       {\r
4221          always_run = "0";\r
4222          fixed_period = "0";\r
4223          snapshot = "1";\r
4224          period = "1.0";\r
4225          period_units = "ms";\r
4226          reset_output = "0";\r
4227          timeout_pulse_output = "0";\r
4228          load_value = "74999";\r
4229          counter_size = "32";\r
4230          mult = "0.0010";\r
4231          ticks_per_sec = "1000";\r
4232       }\r
4233       HDL_INFO \r
4234       {\r
4235          Precompiled_Simulation_Library_Files = "";\r
4236          Simulation_HDL_Files = "";\r
4237          Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sys_clk.vhd";\r
4238          Synthesis_Only_Files = "";\r
4239       }\r
4240       PORT_WIRING \r
4241       {\r
4242       }\r
4243    }\r
4244    MODULE cfi_flash\r
4245    {\r
4246       SLAVE s1\r
4247       {\r
4248          PORT_WIRING \r
4249          {\r
4250             PORT data\r
4251             {\r
4252                type = "data";\r
4253                width = "16";\r
4254                direction = "inout";\r
4255                Is_Enabled = "1";\r
4256                is_shared = "1";\r
4257             }\r
4258             PORT address\r
4259             {\r
4260                type = "address";\r
4261                width = "22";\r
4262                direction = "input";\r
4263                Is_Enabled = "1";\r
4264                is_shared = "1";\r
4265             }\r
4266             PORT read_n\r
4267             {\r
4268                type = "read_n";\r
4269                width = "1";\r
4270                direction = "input";\r
4271                Is_Enabled = "1";\r
4272                is_shared = "1";\r
4273             }\r
4274             PORT write_n\r
4275             {\r
4276                type = "write_n";\r
4277                width = "1";\r
4278                direction = "input";\r
4279                Is_Enabled = "1";\r
4280                is_shared = "1";\r
4281             }\r
4282             PORT select_n\r
4283             {\r
4284                type = "chipselect_n";\r
4285                width = "1";\r
4286                direction = "input";\r
4287                Is_Enabled = "1";\r
4288                is_shared = "0";\r
4289             }\r
4290          }\r
4291          SYSTEM_BUILDER_INFO \r
4292          {\r
4293             Bus_Type = "avalon_tristate";\r
4294             Write_Wait_States = "100ns";\r
4295             Read_Wait_States = "100ns";\r
4296             Hold_Time = "20ns";\r
4297             Setup_Time = "20ns";\r
4298             Is_Printable_Device = "0";\r
4299             Address_Alignment = "dynamic";\r
4300             Well_Behaved_Waitrequest = "0";\r
4301             Is_Nonvolatile_Storage = "1";\r
4302             Address_Span = "8388608";\r
4303             Read_Latency = "0";\r
4304             Is_Memory_Device = "1";\r
4305             Maximum_Pending_Read_Transactions = "0";\r
4306             Minimum_Uninterrupted_Run_Length = "1";\r
4307             Accepts_Internal_Connections = "1";\r
4308             Write_Latency = "0";\r
4309             Is_Flash = "1";\r
4310             Active_CS_Through_Read_Latency = "0";\r
4311             Data_Width = "16";\r
4312             Address_Width = "22";\r
4313             Maximum_Burst_Size = "1";\r
4314             Register_Incoming_Signals = "0";\r
4315             Register_Outgoing_Signals = "0";\r
4316             Interleave_Bursts = "0";\r
4317             Linewrap_Bursts = "0";\r
4318             Burst_On_Burst_Boundaries_Only = "0";\r
4319             Always_Burst_Max_Burst = "0";\r
4320             Is_Big_Endian = "0";\r
4321             Is_Enabled = "1";\r
4322             MASTERED_BY tri_state_bridge_0/tristate_master\r
4323             {\r
4324                priority = "1";\r
4325                Offset_Address = "0x00000000";\r
4326             }\r
4327             Base_Address = "0x00000000";\r
4328             Has_IRQ = "0";\r
4329             Simulation_Num_Lanes = "1";\r
4330             Convert_Xs_To_0 = "1";\r
4331             Address_Group = "0";\r
4332             IRQ_MASTER cpu_0/data_master\r
4333             {\r
4334                IRQ_Number = "NC";\r
4335             }\r
4336          }\r
4337          WIZARD_SCRIPT_ARGUMENTS \r
4338          {\r
4339             class = "altera_avalon_cfi_flash";\r
4340             Supports_Flash_File_System = "1";\r
4341             flash_reference_designator = "";\r
4342          }\r
4343       }\r
4344       WIZARD_SCRIPT_ARGUMENTS \r
4345       {\r
4346          Setup_Value = "20";\r
4347          Wait_Value = "100";\r
4348          Hold_Value = "20";\r
4349          Timing_Units = "ns";\r
4350          Unit_Multiplier = "1";\r
4351          Size = "8388608";\r
4352          MAKE \r
4353          {\r
4354             MACRO \r
4355             {\r
4356                CFI_FLASH_FLASHTARGET_ALT_SIM_PREFIX = "$(CFI_FLASH_FLASHTARGET_TMP1:0=)";\r
4357                CFI_FLASH_FLASHTARGET_TMP1 = "$(ALT_SIM_OPTIMIZE:1=RUN_ON_HDL_SIMULATOR_ONLY_)";\r
4358             }\r
4359             MASTER cpu_0\r
4360             {\r
4361                MACRO \r
4362                {\r
4363                   BOOT_COPIER = "boot_loader_cfi.srec";\r
4364                   CPU_CLASS = "altera_nios2";\r
4365                   CPU_RESET_ADDRESS = "0x0";\r
4366                }\r
4367             }\r
4368             TARGET delete_placeholder_warning\r
4369             {\r
4370                cfi_flash \r
4371                {\r
4372                   Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";\r
4373                   Is_Phony = "1";\r
4374                   Target_File = "do_delete_placeholder_warning";\r
4375                }\r
4376             }\r
4377             TARGET flashfiles\r
4378             {\r
4379                cfi_flash \r
4380                {\r
4381                   Command1 = "@echo Post-processing to create $(notdir $@)";\r
4382                   Command2 = "elf2flash --input=$(ELF) --flash= --boot=$(DBL_QUOTE)$(shell $(DBL_QUOTE)$(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir$(DBL_QUOTE) $(CPU_CLASS) $(QUARTUS_PROJECT_DIR))/$(BOOT_COPIER)$(DBL_QUOTE) --outfile=$(CFI_FLASH_FLASHTARGET_ALT_SIM_PREFIX)cfi_flash.flash --sim_optimize=$(ALT_SIM_OPTIMIZE) --base=0x0 --end=0x7FFFFF --reset=$(CPU_RESET_ADDRESS) ";\r
4383                   Dependency = "$(ELF)";\r
4384                   Target_File = "$(CFI_FLASH_FLASHTARGET_ALT_SIM_PREFIX)cfi_flash.flash";\r
4385                }\r
4386             }\r
4387             TARGET sim\r
4388             {\r
4389                cfi_flash \r
4390                {\r
4391                   Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";\r
4392                   Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";\r
4393                   Command3 = "touch $(SIMDIR)/dummy_file";\r
4394                   Dependency = "$(ELF)";\r
4395                   Target_File = "$(SIMDIR)/dummy_file";\r
4396                }\r
4397             }\r
4398          }\r
4399       }\r
4400       SYSTEM_BUILDER_INFO \r
4401       {\r
4402          Simulation_Num_Lanes = "2";\r
4403          Is_Enabled = "1";\r
4404          Clock_Source = "clk";\r
4405          Has_Clock = "1";\r
4406          Make_Memory_Model = "1";\r
4407          Instantiate_In_System_Module = "0";\r
4408          Top_Level_Ports_Are_Enumerated = "1";\r
4409          View \r
4410          {\r
4411             MESSAGES \r
4412             {\r
4413             }\r
4414          }\r
4415       }\r
4416       class = "altera_avalon_cfi_flash";\r
4417       class_version = "7.08";\r
4418       iss_model_name = "altera_avalon_flash";\r
4419       HDL_INFO \r
4420       {\r
4421       }\r
4422    }\r
4423    MODULE nios_vga_inst\r
4424    {\r
4425       MASTER vga_dma\r
4426       {\r
4427          PORT_WIRING \r
4428          {\r
4429             PORT cpu_clk\r
4430             {\r
4431                type = "clk";\r
4432                width = "1";\r
4433                direction = "input";\r
4434                Is_Enabled = "1";\r
4435             }\r
4436             PORT rst_n\r
4437             {\r
4438                type = "reset_n";\r
4439                width = "1";\r
4440                direction = "input";\r
4441                Is_Enabled = "1";\r
4442             }\r
4443             PORT ram_in\r
4444             {\r
4445                type = "readdata";\r
4446                width = "32";\r
4447                direction = "input";\r
4448                Is_Enabled = "1";\r
4449             }\r
4450             PORT wait_st\r
4451             {\r
4452                type = "waitrequest";\r
4453                width = "1";\r
4454                direction = "input";\r
4455                Is_Enabled = "1";\r
4456             }\r
4457             PORT ram_cs\r
4458             {\r
4459                type = "chipselect";\r
4460                width = "1";\r
4461                direction = "output";\r
4462                Is_Enabled = "1";\r
4463             }\r
4464             PORT ram_wr\r
4465             {\r
4466                type = "write";\r
4467                width = "1";\r
4468                direction = "output";\r
4469                Is_Enabled = "1";\r
4470             }\r
4471             PORT ram_rd\r
4472             {\r
4473                type = "read";\r
4474                width = "1";\r
4475                direction = "output";\r
4476                Is_Enabled = "1";\r
4477             }\r
4478             PORT ram_addr\r
4479             {\r
4480                type = "address";\r
4481                width = "26";\r
4482                direction = "output";\r
4483                Is_Enabled = "1";\r
4484             }\r
4485             PORT ram_out\r
4486             {\r
4487                type = "writedata";\r
4488                width = "32";\r
4489                direction = "output";\r
4490                Is_Enabled = "1";\r
4491             }\r
4492          }\r
4493          SYSTEM_BUILDER_INFO \r
4494          {\r
4495             Bus_Type = "avalon";\r
4496             Is_Asynchronous = "0";\r
4497             DBS_Big_Endian = "0";\r
4498             Adapts_To = "";\r
4499             Do_Stream_Reads = "0";\r
4500             Do_Stream_Writes = "0";\r
4501             Max_Address_Width = "32";\r
4502             Data_Width = "32";\r
4503             Address_Width = "26";\r
4504             Maximum_Burst_Size = "1";\r
4505             Register_Incoming_Signals = "0";\r
4506             Register_Outgoing_Signals = "0";\r
4507             Interleave_Bursts = "0";\r
4508             Linewrap_Bursts = "0";\r
4509             Burst_On_Burst_Boundaries_Only = "0";\r
4510             Always_Burst_Max_Burst = "0";\r
4511             Is_Big_Endian = "0";\r
4512             Is_Enabled = "1";\r
4513          }\r
4514          MEMORY_MAP \r
4515          {\r
4516             Entry cfi_flash/s1\r
4517             {\r
4518                address = "0x00000000";\r
4519                span = "0x00800000";\r
4520                is_bridge = "0";\r
4521             }\r
4522             Entry DBC3C40_SRAM_inst/avalon_tristate_slave\r
4523             {\r
4524                address = "0x00800000";\r
4525                span = "0x00100000";\r
4526                is_bridge = "0";\r
4527             }\r
4528          }\r
4529       }\r
4530       SLAVE vga_regs\r
4531       {\r
4532          SYSTEM_BUILDER_INFO \r
4533          {\r
4534             Bus_Type = "avalon";\r
4535             Write_Wait_States = "1cycles";\r
4536             Read_Wait_States = "1cycles";\r
4537             Hold_Time = "0cycles";\r
4538             Setup_Time = "0cycles";\r
4539             Is_Printable_Device = "0";\r
4540             Address_Alignment = "native";\r
4541             Well_Behaved_Waitrequest = "0";\r
4542             Is_Nonvolatile_Storage = "0";\r
4543             Read_Latency = "0";\r
4544             Is_Memory_Device = "0";\r
4545             Maximum_Pending_Read_Transactions = "0";\r
4546             Minimum_Uninterrupted_Run_Length = "1";\r
4547             Accepts_Internal_Connections = "1";\r
4548             Write_Latency = "0";\r
4549             Is_Flash = "0";\r
4550             Data_Width = "32";\r
4551             Address_Width = "4";\r
4552             Maximum_Burst_Size = "1";\r
4553             Register_Incoming_Signals = "0";\r
4554             Register_Outgoing_Signals = "0";\r
4555             Interleave_Bursts = "0";\r
4556             Linewrap_Bursts = "0";\r
4557             Burst_On_Burst_Boundaries_Only = "0";\r
4558             Always_Burst_Max_Burst = "0";\r
4559             Is_Big_Endian = "0";\r
4560             Is_Enabled = "1";\r
4561             MASTERED_BY cpu_0/data_master\r
4562             {\r
4563                priority = "1";\r
4564                Offset_Address = "0x00900000";\r
4565             }\r
4566             Base_Address = "0x00900000";\r
4567             Address_Group = "0";\r
4568             IRQ_MASTER cpu_0/data_master\r
4569             {\r
4570                IRQ_Number = "NC";\r
4571             }\r
4572          }\r
4573          PORT_WIRING \r
4574          {\r
4575             PORT cpu_cs\r
4576             {\r
4577                type = "chipselect";\r
4578                width = "1";\r
4579                direction = "input";\r
4580                Is_Enabled = "1";\r
4581             }\r
4582             PORT cpu_wr\r
4583             {\r
4584                type = "write";\r
4585                width = "1";\r
4586                direction = "input";\r
4587                Is_Enabled = "1";\r
4588             }\r
4589             PORT cpu_addr\r
4590             {\r
4591                type = "address";\r
4592                width = "4";\r
4593                direction = "input";\r
4594                Is_Enabled = "1";\r
4595             }\r
4596             PORT cpu_in\r
4597             {\r
4598                type = "writedata";\r
4599                width = "32";\r
4600                direction = "input";\r
4601                Is_Enabled = "1";\r
4602             }\r
4603             PORT cpu_out\r
4604             {\r
4605                type = "readdata";\r
4606                width = "32";\r
4607                direction = "output";\r
4608                Is_Enabled = "1";\r
4609             }\r
4610          }\r
4611       }\r
4612       PORT_WIRING \r
4613       {\r
4614          PORT r\r
4615          {\r
4616             type = "export";\r
4617             width = "8";\r
4618             direction = "output";\r
4619             Is_Enabled = "1";\r
4620          }\r
4621          PORT g\r
4622          {\r
4623             type = "export";\r
4624             width = "8";\r
4625             direction = "output";\r
4626             Is_Enabled = "1";\r
4627          }\r
4628          PORT b\r
4629          {\r
4630             type = "export";\r
4631             width = "8";\r
4632             direction = "output";\r
4633             Is_Enabled = "1";\r
4634          }\r
4635          PORT hs\r
4636          {\r
4637             type = "export";\r
4638             width = "1";\r
4639             direction = "output";\r
4640             Is_Enabled = "1";\r
4641          }\r
4642          PORT vs\r
4643          {\r
4644             type = "export";\r
4645             width = "1";\r
4646             direction = "output";\r
4647             Is_Enabled = "1";\r
4648          }\r
4649          PORT m1\r
4650          {\r
4651             type = "export";\r
4652             width = "1";\r
4653             direction = "output";\r
4654             Is_Enabled = "1";\r
4655          }\r
4656          PORT m2\r
4657          {\r
4658             type = "export";\r
4659             width = "1";\r
4660             direction = "output";\r
4661             Is_Enabled = "1";\r
4662          }\r
4663          PORT blank_n\r
4664          {\r
4665             type = "export";\r
4666             width = "1";\r
4667             direction = "output";\r
4668             Is_Enabled = "1";\r
4669          }\r
4670          PORT sync_n\r
4671          {\r
4672             type = "export";\r
4673             width = "1";\r
4674             direction = "output";\r
4675             Is_Enabled = "1";\r
4676          }\r
4677          PORT sync_t\r
4678          {\r
4679             type = "export";\r
4680             width = "1";\r
4681             direction = "output";\r
4682             Is_Enabled = "1";\r
4683          }\r
4684          PORT lcd_reg\r
4685          {\r
4686             type = "export";\r
4687             width = "3";\r
4688             direction = "output";\r
4689             Is_Enabled = "1";\r
4690          }\r
4691          PORT video_clk\r
4692          {\r
4693             type = "export";\r
4694             width = "1";\r
4695             direction = "input";\r
4696             Is_Enabled = "1";\r
4697          }\r
4698       }\r
4699       class = "no_legacy_module";\r
4700       class_version = "7.08";\r
4701       gtf_class_name = "nios_vga";\r
4702       gtf_class_version = "1.0.1";\r
4703       SYSTEM_BUILDER_INFO \r
4704       {\r
4705          Do_Not_Generate = "1";\r
4706          Instantiate_In_System_Module = "1";\r
4707          Is_Enabled = "1";\r
4708          Clock_Source = "clk";\r
4709          Has_Clock = "1";\r
4710          View \r
4711          {\r
4712             MESSAGES \r
4713             {\r
4714             }\r
4715          }\r
4716       }\r
4717       HDL_INFO \r
4718       {\r
4719          Simulation_HDL_Files = "__PROJECT_DIRECTORY__/nios_vga_inst.vhd";\r
4720       }\r
4721       WIZARD_SCRIPT_ARGUMENTS \r
4722       {\r
4723          terminated_ports \r
4724          {\r
4725          }\r
4726       }\r
4727    }\r
4728    MODULE DBC3C40_SRAM_inst\r
4729    {\r
4730       SLAVE avalon_tristate_slave\r
4731       {\r
4732          SYSTEM_BUILDER_INFO \r
4733          {\r
4734             Bus_Type = "avalon_tristate";\r
4735             Write_Wait_States = "1cycles";\r
4736             Read_Wait_States = "1cycles";\r
4737             Hold_Time = "1cycles";\r
4738             Setup_Time = "0cycles";\r
4739             Is_Printable_Device = "0";\r
4740             Address_Alignment = "dynamic";\r
4741             Well_Behaved_Waitrequest = "0";\r
4742             Is_Nonvolatile_Storage = "0";\r
4743             Address_Span = "1048576";\r
4744             Read_Latency = "0";\r
4745             Is_Memory_Device = "1";\r
4746             Maximum_Pending_Read_Transactions = "0";\r
4747             Minimum_Uninterrupted_Run_Length = "1";\r
4748             Accepts_Internal_Connections = "1";\r
4749             Write_Latency = "0";\r
4750             Is_Flash = "0";\r
4751             Active_CS_Through_Read_Latency = "0";\r
4752             Data_Width = "16";\r
4753             Address_Width = "19";\r
4754             Maximum_Burst_Size = "1";\r
4755             Register_Incoming_Signals = "0";\r
4756             Register_Outgoing_Signals = "0";\r
4757             Interleave_Bursts = "0";\r
4758             Linewrap_Bursts = "0";\r
4759             Burst_On_Burst_Boundaries_Only = "0";\r
4760             Always_Burst_Max_Burst = "0";\r
4761             Is_Big_Endian = "0";\r
4762             Is_Enabled = "1";\r
4763             MASTERED_BY tri_state_bridge_0/tristate_master\r
4764             {\r
4765                priority = "1";\r
4766                Offset_Address = "0x00800000";\r
4767             }\r
4768             Base_Address = "0x00800000";\r
4769             Address_Group = "0";\r
4770             IRQ_MASTER cpu_0/data_master\r
4771             {\r
4772                IRQ_Number = "NC";\r
4773             }\r
4774          }\r
4775          PORT_WIRING \r
4776          {\r
4777             PORT addr\r
4778             {\r
4779                type = "address";\r
4780                width = "19";\r
4781                direction = "input";\r
4782                Is_Enabled = "1";\r
4783                is_shared = "1";\r
4784             }\r
4785             PORT data\r
4786             {\r
4787                type = "data";\r
4788                width = "16";\r
4789                direction = "inout";\r
4790                Is_Enabled = "1";\r
4791                is_shared = "1";\r
4792             }\r
4793             PORT ncs\r
4794             {\r
4795                type = "chipselect_n";\r
4796                width = "1";\r
4797                direction = "input";\r
4798                Is_Enabled = "1";\r
4799                is_shared = "0";\r
4800             }\r
4801             PORT wrn\r
4802             {\r
4803                type = "write_n";\r
4804                width = "1";\r
4805                direction = "input";\r
4806                Is_Enabled = "1";\r
4807                is_shared = "1";\r
4808             }\r
4809             PORT rdn\r
4810             {\r
4811                type = "read_n";\r
4812                width = "1";\r
4813                direction = "input";\r
4814                Is_Enabled = "1";\r
4815                is_shared = "1";\r
4816             }\r
4817             PORT ben\r
4818             {\r
4819                type = "byteenable_n";\r
4820                width = "2";\r
4821                direction = "input";\r
4822                Is_Enabled = "1";\r
4823                is_shared = "1";\r
4824             }\r
4825          }\r
4826       }\r
4827       class = "no_legacy_module";\r
4828       class_version = "7.08";\r
4829       gtf_class_name = "DBC3C40_SRAM";\r
4830       gtf_class_version = "1.0";\r
4831       SYSTEM_BUILDER_INFO \r
4832       {\r
4833          Do_Not_Generate = "1";\r
4834          Instantiate_In_System_Module = "0";\r
4835          Is_Enabled = "1";\r
4836          Clock_Source = "clk";\r
4837          View \r
4838          {\r
4839             MESSAGES \r
4840             {\r
4841             }\r
4842          }\r
4843       }\r
4844       HDL_INFO \r
4845       {\r
4846          Simulation_HDL_Files = "";\r
4847       }\r
4848       WIZARD_SCRIPT_ARGUMENTS \r
4849       {\r
4850          terminated_ports \r
4851          {\r
4852          }\r
4853       }\r
4854    }\r
4855 }\r