2 This serial port driver is borrowed heavily from DZComm. I have
\r
3 simplified it by removing a lot of the functionality (hardware
\r
4 flow control, etc.). For more details and the full version see
\r
5 http://dzcomm.sourceforge.net
\r
9 FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
\r
12 ***************************************************************************
\r
14 * FreeRTOS tutorial books are available in pdf and paperback. *
\r
15 * Complete, revised, and edited pdf reference manuals are also *
\r
18 * Purchasing FreeRTOS documentation will not only help you, by *
\r
19 * ensuring you get running as quickly as possible and with an *
\r
20 * in-depth knowledge of how to use FreeRTOS, it will also help *
\r
21 * the FreeRTOS project to continue with its mission of providing *
\r
22 * professional grade, cross platform, de facto standard solutions *
\r
23 * for microcontrollers - completely free of charge! *
\r
25 * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
\r
27 * Thank you for using FreeRTOS, and thank you for your support! *
\r
29 ***************************************************************************
\r
32 This file is part of the FreeRTOS distribution.
\r
34 FreeRTOS is free software; you can redistribute it and/or modify it under
\r
35 the terms of the GNU General Public License (version 2) as published by the
\r
36 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
\r
37 >>>NOTE<<< The modification to the GPL is included to allow you to
\r
38 distribute a combined work that includes FreeRTOS without being obliged to
\r
39 provide the source code for proprietary components outside of the FreeRTOS
\r
40 kernel. FreeRTOS is distributed in the hope that it will be useful, but
\r
41 WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
\r
42 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
\r
43 more details. You should have received a copy of the GNU General Public
\r
44 License and the FreeRTOS license exception along with FreeRTOS; if not it
\r
45 can be viewed here: http://www.freertos.org/a00114.html and also obtained
\r
46 by writing to Richard Barry, contact details for whom are available on the
\r
51 ***************************************************************************
\r
53 * Having a problem? Start by reading the FAQ "My application does *
\r
54 * not run, what could be wrong? *
\r
56 * http://www.FreeRTOS.org/FAQHelp.html *
\r
58 ***************************************************************************
\r
61 http://www.FreeRTOS.org - Documentation, training, latest information,
\r
62 license and contact details.
\r
64 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
\r
65 including FreeRTOS+Trace - an indispensable productivity tool.
\r
67 Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
\r
68 the code with commercial support, indemnification, and middleware, under
\r
69 the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
\r
70 provide a safety engineered and independently SIL3 certified version under
\r
71 the SafeRTOS brand: http://www.SafeRTOS.com.
\r
78 #include "FreeRTOS.h"
\r
82 #include "portasm.h"
\r
84 #define serMAX_IRQs ( 16 )
\r
85 #define serTRANSMIT_HOLD_EMPTY_INT ( 0x02 )
\r
86 #define serCOM1_STANDARD_IRQ ( ( unsigned char ) 4 )
\r
87 #define serCOM2_STANDARD_IRQ ( ( unsigned char ) 3 )
\r
90 #define serIMR_8259_0 ( ( unsigned char ) 0x21 )
\r
91 #define serIMR_8259_1 ( ( unsigned char ) 0xa1 )
\r
92 #define serISR_8259_0 ( ( unsigned char ) 0x20 )
\r
93 #define serISR_8259_1 ( ( unsigned char ) 0xa0 )
\r
94 #define serALL_COMS_INTERRUPTS ( ( unsigned char ) 0x0f )
\r
95 #define serALL_MODEM_CTRL_INTERRUPTS ( ( unsigned char ) 0x0f )
\r
97 #define serTRANSMIT_HOLD_OFFSET ( 0 )
\r
98 #define serRECEIVE_DATA_OFFSET ( 0 )
\r
99 #define serBAUD_RATE_DIVISOR_LOW_OFFSET ( 0 )
\r
100 #define serBAUD_RATE_DIVISOR_HIGH_OFFSET ( 1 )
\r
101 #define serINTERRUPT_ENABLE_OFFSET ( 1 )
\r
102 #define serINTERRUPT_ID_OFFSET ( 2 )
\r
103 #define serFIFO_CTRL_OFFSET ( 2 )
\r
104 #define serLINE_CTRL_OFFSET ( 3 )
\r
105 #define serMODEM_CTRL_OFFSET ( 4 )
\r
106 #define serLINE_STATUS_OFFSET ( 5 )
\r
107 #define serMODEM_STATUS_OFFSET ( 6 )
\r
108 #define serSCR_OFFSET ( 7 )
\r
110 #define serMAX_BAUD ( ( unsigned long ) 115200UL )
\r
112 #define serNO_INTERRUPTS ( 0x00 )
\r
114 #define vInterruptOn( pxPort, ucInterrupt ) \
\r
116 unsigned char ucIn = portINPUT_BYTE( pxPort->usInterruptEnableReg ); \
\r
117 if( !( ucIn & ucInterrupt ) ) \
\r
119 portOUTPUT_BYTE( pxPort->usInterruptEnableReg, ucIn | ucInterrupt ); \
\r
122 /*-----------------------------------------------------------*/
\r
124 #define vInterruptOff( pxPort, ucInterrupt ) \
\r
126 unsigned char ucIn = portINPUT_BYTE( pxPort->usInterruptEnableReg ); \
\r
127 if( ucIn & ucInterrupt ) \
\r
129 portOUTPUT_BYTE( pxPort->usInterruptEnableReg, ucIn & ~ucInterrupt); \
\r
132 /*-----------------------------------------------------------*/
\r
190 /* This *MUST* match the order in the eBaud definition. */
\r
191 unsigned long ulBaudFromEnum[] =
\r
193 ( unsigned long ) 50,
\r
194 ( unsigned long ) 75,
\r
195 ( unsigned long ) 110,
\r
196 ( unsigned long ) 134,
\r
197 ( unsigned long ) 150,
\r
198 ( unsigned long ) 200,
\r
199 ( unsigned long ) 300,
\r
200 ( unsigned long ) 600,
\r
201 ( unsigned long ) 1200,
\r
202 ( unsigned long ) 1800,
\r
203 ( unsigned long ) 2400,
\r
204 ( unsigned long ) 4800,
\r
205 ( unsigned long ) 9600,
\r
206 ( unsigned long ) 19200,
\r
207 ( unsigned long ) 38400UL,
\r
208 ( unsigned long ) 57600UL,
\r
209 ( unsigned long ) 115200UL
\r
212 typedef struct xCOM_PORT
\r
214 unsigned short sPort; /* comm port address eg. 0x3f8 */
\r
215 unsigned char ucIRQ; /* comm IRQ eg. 3 */
\r
217 /* Next two fields used for setting up the IRQ routine and
\r
218 * (un)masking the interrupt in certain circumstances.
\r
220 unsigned short usIRQVector;
\r
221 unsigned char ucInterruptEnableMast;
\r
223 /* Read/Write buffers. */
\r
224 xQueueHandle xRxedChars;
\r
225 xQueueHandle xCharsForTx;
\r
227 /* This lot are set up to minimise CPU time where accessing the comm
\r
228 * port's registers.
\r
230 unsigned short usTransmitHoldReg;
\r
231 unsigned short usReceiveDataRegister;
\r
232 unsigned short usBaudRateDivisorLow;
\r
233 unsigned short usBaudRateDivisorHigh;
\r
234 unsigned short usInterruptEnableReg;
\r
235 unsigned short usInterruptIDReg;
\r
236 unsigned short usFIFOCtrlReg;
\r
237 unsigned short usLineCtrlReg;
\r
238 unsigned short usModemCtrlReg;
\r
239 unsigned short usLineStatusReg;
\r
240 unsigned short usModemStatusReg;
\r
241 unsigned short usSCRReg;
\r
242 unsigned short us8259InterruptServiceReg;
\r
243 unsigned short us8259InterruptMaskReg;
\r
245 /* This semaphore does nothing useful except test a feature of the
\r
247 xSemaphoreHandle xTestSem;
\r
251 typedef xComPort *xComPortHandle;
\r
253 /* A xComPort structure can be associated with each IRQ. Initially none
\r
254 are create/installed. */
\r
255 xComPort *xPortStatus[ serMAX_IRQs ] = { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL };
\r
257 /*-----------------------------------------------------------*/
\r
259 /* These prototypes are repeated here so we don't have to include the serial header. This allows
\r
260 the xComPortHandle structure details to be private to this file. */
\r
261 xComPortHandle xSerialPortInit( eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits, unsigned portBASE_TYPE uxBufferLength );
\r
262 portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, char *pcRxedChar, portTickType xBlockTime );
\r
263 portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, char cOutChar, portTickType xBlockTime );
\r
264 portBASE_TYPE xSerialWaitForSemaphore( xComPortHandle xPort );
\r
266 static void prvSetupPortHardware( xComPort *pxPort, eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits );
\r
267 static short sComPortISR( const xComPort * const pxPort );
\r
269 /*-----------------------------------------------------------*/
\r
271 /* Define an interrupt handler for each slot in the xPortStatus array. */
\r
273 #define COM_IRQ_WRAPPER(N) \
\r
274 static void __interrupt COM_IRQ##N##_WRAPPER( void ) \
\r
276 portDISABLE_INTERRUPTS(); \
\r
277 if( sComPortISR( xPortStatus[##N##] ) ) \
\r
279 portSWITCH_CONTEXT(); \
\r
283 COM_IRQ_WRAPPER( 0 )
\r
284 COM_IRQ_WRAPPER( 1 )
\r
285 COM_IRQ_WRAPPER( 2 )
\r
286 COM_IRQ_WRAPPER( 3 )
\r
287 COM_IRQ_WRAPPER( 4 )
\r
288 COM_IRQ_WRAPPER( 5 )
\r
289 COM_IRQ_WRAPPER( 6 )
\r
290 COM_IRQ_WRAPPER( 7 )
\r
291 COM_IRQ_WRAPPER( 8 )
\r
292 COM_IRQ_WRAPPER( 9 )
\r
293 COM_IRQ_WRAPPER( 10 )
\r
294 COM_IRQ_WRAPPER( 11 )
\r
295 COM_IRQ_WRAPPER( 12 )
\r
296 COM_IRQ_WRAPPER( 13 )
\r
297 COM_IRQ_WRAPPER( 14 )
\r
298 COM_IRQ_WRAPPER( 15 )
\r
300 static pxISR xISRs[ serMAX_IRQs ] =
\r
312 COM_IRQ10_WRAPPER,
\r
313 COM_IRQ11_WRAPPER,
\r
314 COM_IRQ12_WRAPPER,
\r
315 COM_IRQ13_WRAPPER,
\r
320 static pxISR xOldISRs[ serMAX_IRQs ] = { NULL };
\r
322 /*-----------------------------------------------------------*/
\r
325 xComPortHandle xSerialPortInit( eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits, unsigned portBASE_TYPE uxBufferLength )
\r
329 /* Create a structure to handle this port. */
\r
330 pxPort = ( xComPort * ) pvPortMalloc( sizeof( xComPort ) );
\r
332 if( pxPort != NULL )
\r
334 /* Create the queues used by the comtest task. */
\r
335 pxPort->xRxedChars = xQueueCreate( uxBufferLength, ( unsigned portBASE_TYPE ) sizeof( char ) );
\r
336 pxPort->xCharsForTx = xQueueCreate( uxBufferLength, ( unsigned portBASE_TYPE ) sizeof( char ) );
\r
338 /* Create the test semaphore. This does nothing useful except test a feature of the scheduler. */
\r
339 vSemaphoreCreateBinary( pxPort->xTestSem );
\r
341 prvSetupPortHardware( pxPort, ePort, eWantedBaud, eWantedParity, eWantedDataBits, eWantedStopBits );
\r
348 /*-----------------------------------------------------------*/
\r
350 static void prvSetupPortHardware( xComPort *pxPort, eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits )
\r
353 unsigned long ulDivisor;
\r
354 unsigned char ucDivisorLow;
\r
355 unsigned char ucDivisorHigh;
\r
356 unsigned char ucCommParam;
\r
358 /* IRQ numbers - standard */
\r
359 if( ( ePort == serCOM1 ) || ( ePort == serCOM3 ) || ( ePort == serCOM5 ) || ( ePort == serCOM7 ) )
\r
361 pxPort->ucIRQ = serCOM1_STANDARD_IRQ;
\r
362 pxPort->sPort = 0x3f8;
\r
366 pxPort->ucIRQ = serCOM2_STANDARD_IRQ;
\r
367 pxPort->sPort = 0x2f8;
\r
370 /* Set up variables in port making it easy to see which sIn/o address is which */
\r
371 pxPort->usTransmitHoldReg = pxPort->sPort + serTRANSMIT_HOLD_OFFSET;
\r
372 pxPort->usReceiveDataRegister = pxPort->sPort + serRECEIVE_DATA_OFFSET;
\r
373 pxPort->usBaudRateDivisorLow = pxPort->sPort + serBAUD_RATE_DIVISOR_LOW_OFFSET;
\r
374 pxPort->usBaudRateDivisorHigh = pxPort->sPort + serBAUD_RATE_DIVISOR_HIGH_OFFSET;
\r
375 pxPort->usInterruptEnableReg = pxPort->sPort + serINTERRUPT_ENABLE_OFFSET;
\r
376 pxPort->usInterruptIDReg = pxPort->sPort + serINTERRUPT_ID_OFFSET;
\r
377 pxPort->usFIFOCtrlReg = pxPort->sPort + serFIFO_CTRL_OFFSET;
\r
378 pxPort->usLineCtrlReg = pxPort->sPort + serLINE_CTRL_OFFSET;
\r
379 pxPort->usModemCtrlReg = pxPort->sPort + serMODEM_CTRL_OFFSET;
\r
380 pxPort->usLineStatusReg = pxPort->sPort + serLINE_STATUS_OFFSET;
\r
381 pxPort->usModemStatusReg = pxPort->sPort + serMODEM_STATUS_OFFSET;
\r
382 pxPort->usSCRReg = pxPort->sPort + serSCR_OFFSET;
\r
384 /* Set communication parameters. */
\r
385 ulDivisor = serMAX_BAUD / ulBaudFromEnum[ eWantedBaud ];
\r
386 ucDivisorLow = ( unsigned char ) ulDivisor & ( unsigned char ) 0xff;
\r
387 ucDivisorHigh = ( unsigned char ) ( ( ( unsigned short ) ulDivisor >> 8 ) & 0xff );
\r
389 switch( eWantedParity )
\r
391 case serNO_PARITY: ucCommParam = 0x00;
\r
393 case serODD_PARITY: ucCommParam = 0x08;
\r
395 case serEVEN_PARITY: ucCommParam = 0x18;
\r
397 case serMARK_PARITY: ucCommParam = 0x28;
\r
399 case serSPACE_PARITY: ucCommParam = 0x38;
\r
401 default: ucCommParam = 0x00;
\r
405 switch ( eWantedDataBits )
\r
407 case serBITS_5: ucCommParam |= 0x00;
\r
409 case serBITS_6: ucCommParam |= 0x01;
\r
411 case serBITS_7: ucCommParam |= 0x02;
\r
413 case serBITS_8: ucCommParam |= 0x03;
\r
415 default: ucCommParam |= 0x03;
\r
419 if( eWantedStopBits == serSTOP_2 )
\r
421 ucCommParam |= 0x04;
\r
424 /* Reset UART into known state - Thanks to Bradley Town */
\r
425 portOUTPUT_BYTE( pxPort->usLineCtrlReg, 0x00 ); /* Access usTransmitHoldReg/RBR/usInterruptEnableReg */
\r
426 portOUTPUT_BYTE( pxPort->usInterruptEnableReg, 0x00 ); /* Disable interrupts from UART */
\r
427 portOUTPUT_BYTE( pxPort->usModemCtrlReg, 0x04 ); /* Enable some multi-port cards */
\r
429 /* Code based on stuff from SVAsync lib. Clear UART Status and data registers
\r
430 setting up FIFO if possible */
\r
431 sIn = portINPUT_BYTE( pxPort->usSCRReg );
\r
432 portOUTPUT_BYTE( pxPort->usSCRReg, 0x55 );
\r
434 if( portINPUT_BYTE( pxPort->usSCRReg ) == 0x55 )
\r
436 /* The chip is better than an 8250 */
\r
437 portOUTPUT_BYTE( pxPort->usSCRReg, sIn ); /* Set usSCRReg back to what it was before */
\r
438 portINPUT_BYTE( pxPort->usSCRReg); /* Give slow motherboards a chance */
\r
440 /* Try and start the FIFO. It appears that some chips need a two call
\r
441 protocol, but those that don't seem to work even if you do start it twice.
\r
442 The first call is simply to start it, the second starts it and sets an 8
\r
443 byte FIFO trigger level. */
\r
444 portOUTPUT_BYTE( pxPort->usFIFOCtrlReg, 0x01 );
\r
445 portINPUT_BYTE( pxPort->usFIFOCtrlReg ); /* Give slow motherboards a chance to catch up */
\r
446 portOUTPUT_BYTE( pxPort->usFIFOCtrlReg, 0x87 );
\r
448 /* Check that the FIFO initialised */
\r
449 if( ( portINPUT_BYTE( pxPort->usInterruptIDReg ) & 0xc0 ) != 0xc0 )
\r
451 /* It didn't so we assume it isn't there but disable it to be on the
\r
453 portOUTPUT_BYTE( pxPort->usInterruptIDReg, 0xfe );
\r
457 /* End of (modified) SVAsync code.
\r
458 Set interrupt parameters calculating mask for 8259 controller's
\r
459 IMR and number of interrupt handler for given irq level */
\r
460 if (pxPort->ucIRQ <= 7)
\r
462 /* if 0<=irq<=7 first IMR address used */
\r
463 pxPort->ucInterruptEnableMast = ~(0x01 << pxPort->ucIRQ);
\r
464 pxPort->usIRQVector = pxPort->ucIRQ + 8;
\r
465 pxPort->us8259InterruptMaskReg = serIMR_8259_0;
\r
466 pxPort->us8259InterruptServiceReg = serISR_8259_0;
\r
470 pxPort->ucInterruptEnableMast = ~( 0x01 << ( pxPort->ucIRQ % 8 ) );
\r
471 pxPort->usIRQVector = 0x70 + ( pxPort->ucIRQ - 8) ;
\r
472 pxPort->us8259InterruptMaskReg = serIMR_8259_1;
\r
473 pxPort->us8259InterruptServiceReg = serISR_8259_1;
\r
476 /* Set Port Toggle to usBaudRateDivisorLow/usBaudRateDivisorHigh registers
\r
477 to set baud rate */
\r
478 portOUTPUT_BYTE( pxPort->usLineCtrlReg, ucCommParam | 0x80 );
\r
479 portOUTPUT_BYTE( pxPort->usBaudRateDivisorLow, ucDivisorLow );
\r
480 portOUTPUT_BYTE( pxPort->usBaudRateDivisorHigh, ucDivisorHigh );
\r
482 /* reset usLineCtrlReg and Port Toggleout */
\r
483 portOUTPUT_BYTE( pxPort->usLineCtrlReg, ucCommParam & 0x7F );
\r
485 portENTER_CRITICAL();
\r
487 if( xPortStatus[ pxPort->ucIRQ ] == NULL )
\r
489 xPortStatus[ pxPort->ucIRQ ] = pxPort;
\r
492 xOldISRs[ pxPort->ucIRQ ] = _dos_getvect( pxPort->usIRQVector );
\r
493 _dos_setvect( pxPort->usIRQVector, xISRs[ pxPort->ucIRQ ] );
\r
495 /* enable interrupt pxPort->ucIRQ level */
\r
496 portOUTPUT_BYTE( pxPort->us8259InterruptMaskReg, portINPUT_BYTE( pxPort->us8259InterruptMaskReg ) & pxPort->ucInterruptEnableMast );
\r
498 /* And allow interrupts again now the hairy bit's done */
\r
499 portEXIT_CRITICAL();
\r
501 /* This version does not allow flow control. */
\r
502 portOUTPUT_BYTE( pxPort->usModemCtrlReg, serALL_MODEM_CTRL_INTERRUPTS );
\r
504 /* enable all communication's interrupts */
\r
505 portOUTPUT_BYTE( pxPort->usInterruptEnableReg, serALL_COMS_INTERRUPTS );
\r
507 /*-----------------------------------------------------------*/
\r
509 static short sComPortISR( const xComPort * const pxPort )
\r
511 short sInterruptID;
\r
513 portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
\r
514 extern void vComTestUnsuspendTask( void );
\r
516 portOUTPUT_BYTE( pxPort->us8259InterruptMaskReg, ( portINPUT_BYTE( pxPort->us8259InterruptMaskReg) | ~pxPort->ucInterruptEnableMast ) );
\r
518 /* Decide which UART has issued the interrupt */
\r
519 sInterruptID = portINPUT_BYTE( pxPort->usInterruptIDReg );
\r
521 /* service whatever requests the calling UART may have. The top 4 bits are
\r
522 either unused or indicate the presence of a functioning FIFO, which we don't
\r
523 need to know. So trim them off to simplify the switch statement below. */
\r
524 sInterruptID &= 0x0f;
\r
527 switch( sInterruptID )
\r
529 case 0x0c: /* Timeout
\r
530 Called when FIFO not up to trigger level but no activity for
\r
531 a while. Handled exactly as RDAINT, see below for
\r
535 cIn = ( char ) portINPUT_BYTE( pxPort->usReceiveDataRegister );
\r
536 xQueueSendFromISR( pxPort->xRxedChars, &cIn, &xHigherPriorityTaskWoken );
\r
538 /* Also release the semaphore - this does nothing interesting and is just a test.
\r
539 We first attempt to unsuspend the task to check the scheduler correctely detects
\r
540 this as an invalid call, then give the semaphore for real. */
\r
541 vComTestUnsuspendTask();
\r
542 xSemaphoreGiveFromISR( pxPort->xTestSem, &xHigherPriorityTaskWoken );
\r
544 } while( portINPUT_BYTE( pxPort->usLineStatusReg ) & 0x01 );
\r
547 case 0x06: /* LSINT */
\r
548 portINPUT_BYTE( pxPort->usLineStatusReg );
\r
551 case 0x04: /* RDAINT */
\r
552 /* The usInterruptIDReg flag tested above stops when the
\r
553 FIFO is below the trigger level rather than empty, whereas
\r
554 this flag allows one to empty it: (do loop because there
\r
555 must be at least one to read by virtue of having got here.) */
\r
558 cIn = ( char ) portINPUT_BYTE( pxPort->usReceiveDataRegister );
\r
559 xQueueSendFromISR( pxPort->xRxedChars, &cIn, &xHigherPriorityTaskWoken );
\r
561 /* Also release the semaphore - this does nothing interesting and is just a test.
\r
562 We first attempt to unsuspend the task to check the scheduler correctely detects
\r
563 this as an invalid call, then give the semaphore for real. */
\r
564 vComTestUnsuspendTask();
\r
565 xSemaphoreGiveFromISR( pxPort->xTestSem, &xHigherPriorityTaskWoken );
\r
567 } while( portINPUT_BYTE( pxPort->usLineStatusReg ) & 0x01 );
\r
570 case 0x02: /* serTRANSMIT_HOLD_EMPTY_INT */
\r
571 if( xQueueReceiveFromISR( pxPort->xCharsForTx, &cOut, &xHigherPriorityTaskWoken ) != pdTRUE )
\r
573 /* Queue empty, nothing to send */
\r
574 vInterruptOff( pxPort, serTRANSMIT_HOLD_EMPTY_INT);
\r
578 portOUTPUT_BYTE( pxPort->usTransmitHoldReg, ( short ) cOut );
\r
582 case 0x00: /* MSINT */
\r
583 portINPUT_BYTE( pxPort->usModemStatusReg );
\r
587 /* Get the next instruction, trimming as above */
\r
588 sInterruptID = portINPUT_BYTE( pxPort->usInterruptIDReg ) & 0x0f;
\r
590 } while( !( sInterruptID & 0x01 ) );
\r
592 if( pxPort->ucIRQ > 7 )
\r
594 portOUTPUT_BYTE( 0xA0, 0x60 + ( pxPort->ucIRQ & 0x07 ) );
\r
595 portOUTPUT_BYTE( 0x20, 0x62);
\r
599 portOUTPUT_BYTE( 0x20, 0x60 + pxPort->ucIRQ );
\r
602 portOUTPUT_BYTE( pxPort->us8259InterruptMaskReg, portINPUT_BYTE( pxPort->us8259InterruptMaskReg ) & pxPort->ucInterruptEnableMast );
\r
604 /* If posting any of the characters to a queue woke a task that was blocked on
\r
605 the queue we may want to return to the task just woken (depending on its
\r
606 priority relative to the task this ISR interrupted. */
\r
607 return xHigherPriorityTaskWoken;
\r
609 /*-----------------------------------------------------------*/
\r
611 portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, char *pcRxedChar, portTickType xBlockTime )
\r
613 /* Get the next character from the buffer, note that this routine is only
\r
614 called having checked that the is (at least) one to get */
\r
615 if( xQueueReceive( pxPort->xRxedChars, pcRxedChar, xBlockTime ) )
\r
624 /*-----------------------------------------------------------*/
\r
626 portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, char cOutChar, portTickType xBlockTime )
\r
628 if( xQueueSend( pxPort->xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )
\r
633 vInterruptOn( pxPort, serTRANSMIT_HOLD_EMPTY_INT );
\r
637 /*-----------------------------------------------------------*/
\r
639 void vSerialPutString( xComPortHandle pxPort, const char * const pcString, unsigned short usStringLength )
\r
642 const portTickType xNoBlock = ( portTickType ) 0;
\r
644 /* Stop warnings. */
\r
645 ( void ) usStringLength;
\r
647 pcNextChar = ( char * ) pcString;
\r
648 while( *pcNextChar )
\r
650 xSerialPutChar( pxPort, *pcNextChar, xNoBlock );
\r
654 /*-----------------------------------------------------------*/
\r
656 portBASE_TYPE xSerialWaitForSemaphore( xComPortHandle xPort )
\r
658 const portTickType xBlockTime = ( portTickType ) 0xffff;
\r
660 /* This function does nothing interesting, but test the
\r
661 semaphore from ISR mechanism. */
\r
662 return xSemaphoreTake( xPort->xTestSem, xBlockTime );
\r
664 /*-----------------------------------------------------------*/
\r
666 void vSerialClose( xComPortHandle xPort )
\r
668 portENTER_CRITICAL();
\r
670 /* Turn off the interrupts. */
\r
671 portOUTPUT_BYTE( xPort->usModemCtrlReg, serNO_INTERRUPTS );
\r
672 portOUTPUT_BYTE( xPort->usInterruptEnableReg, serNO_INTERRUPTS );
\r
674 /* Put back the original ISR. */
\r
675 _dos_setvect( xPort->usIRQVector, xOldISRs[ xPort->ucIRQ ] );
\r
677 /* Remove the reference in the array of xComPort structures. */
\r
678 xPortStatus[ xPort->ucIRQ ] = NULL;
\r
680 /* Delete the queues. */
\r
681 vQueueDelete( xPort->xRxedChars );
\r
682 vQueueDelete( xPort->xCharsForTx );
\r
684 vPortFree( ( void * ) xPort );
\r
686 portEXIT_CRITICAL();
\r