2 FreeRTOS V8.0.0 - Copyright (C) 2014 Real Time Engineers Ltd.
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5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 ***************************************************************************
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9 * FreeRTOS provides completely free yet professionally developed, *
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10 * robust, strictly quality controlled, supported, and cross *
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11 * platform software that has become a de facto standard. *
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13 * Help yourself get started quickly and support the FreeRTOS *
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14 * project by purchasing a FreeRTOS tutorial book, reference *
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15 * manual, or both from: http://www.FreeRTOS.org/Documentation *
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19 ***************************************************************************
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21 This file is part of the FreeRTOS distribution.
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23 FreeRTOS is free software; you can redistribute it and/or modify it under
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24 the terms of the GNU General Public License (version 2) as published by the
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25 Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
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27 >>! NOTE: The modification to the GPL is included to allow you to distribute
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28 >>! a combined work that includes FreeRTOS without being obliged to provide
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29 >>! the source code for proprietary components outside of the FreeRTOS
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32 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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33 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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34 FOR A PARTICULAR PURPOSE. Full license text is available from the following
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35 link: http://www.freertos.org/a00114.html
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39 ***************************************************************************
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41 * Having a problem? Start by reading the FAQ "My application does *
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42 * not run, what could be wrong?" *
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44 * http://www.FreeRTOS.org/FAQHelp.html *
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46 ***************************************************************************
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48 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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49 license and Real Time Engineers Ltd. contact details.
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51 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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52 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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53 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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55 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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56 Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
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57 licenses offer ticketed support, indemnification and middleware.
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59 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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60 engineered and independently SIL3 certified version for use in safety and
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61 mission critical applications that require provable dependability.
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67 * This file implements functions to access and manipulate the PIC32 hardware
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68 * without reliance on third party library functions that may be liable to
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72 /* FreeRTOS includes. */
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73 #include "FreeRTOS.h"
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75 /* Demo includes. */
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76 #include "ConfigPerformance.h"
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78 /* Hardware specific definitions. */
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79 #define hwCHECON_PREFEN_BITS ( 0x03UL << 0x04UL )
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80 #define hwCHECON_WAIT_STAT_BITS ( 0x07UL << 0UL )
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81 #define hwMAX_FLASH_SPEED ( 30000000UL )
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82 #define hwPERIPHERAL_CLOCK_DIV_BY_2 ( 1UL << 0x13UL )
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83 #define hwUNLOCK_KEY_0 ( 0xAA996655UL )
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84 #define hwUNLOCK_KEY_1 ( 0x556699AAUL )
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85 #define hwLOCK_KEY ( 0x33333333UL )
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86 #define hwGLOBAL_INTERRUPT_BIT ( 0x01UL )
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87 #define hwBEV_BIT ( 0x00400000 )
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88 #define hwEXL_BIT ( 0x00000002 )
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89 #define hwIV_BIT ( 0x00800000 )
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92 * Set the flash wait states for the configured CPU clock speed.
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94 static void prvConfigureWaitStates( void );
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97 * Use a divisor of 2 on the peripheral bus.
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99 static void prvConfigurePeripheralBus( void );
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102 * Enable the cache.
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104 static void __attribute__ ((nomips16)) prvKSeg0CacheOn( void );
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106 /*-----------------------------------------------------------*/
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108 void vHardwareConfigurePerformance( void )
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110 unsigned long ulStatus;
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112 unsigned long ulCacheStatus;
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115 /* Disable interrupts - note taskDISABLE_INTERRUPTS() cannot be used here as
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116 FreeRTOS does not globally disable interrupt. */
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117 ulStatus = _CP0_GET_STATUS();
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118 _CP0_SET_STATUS( ulStatus & ~hwGLOBAL_INTERRUPT_BIT );
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120 prvConfigurePeripheralBus();
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121 prvConfigureWaitStates();
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123 /* Disable DRM wait state. */
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124 BMXCONCLR = _BMXCON_BMXWSDRM_MASK;
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128 /* Read the current CHECON value. */
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129 ulCacheStatus = CHECON;
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131 /* All the PREFEN bits are being set, so no need to clear first. */
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132 ulCacheStatus |= hwCHECON_PREFEN_BITS;
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134 /* Write back the new value. */
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135 CHECON = ulCacheStatus;
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140 /* Reset the status register back to its original value so the original
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141 interrupt enable status is retored. */
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142 _CP0_SET_STATUS( ulStatus );
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144 /*-----------------------------------------------------------*/
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146 void vHardwareUseMultiVectoredInterrupts( void )
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148 unsigned long ulStatus, ulCause;
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149 extern unsigned long _ebase_address[];
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151 /* Get current status. */
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152 ulStatus = _CP0_GET_STATUS();
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154 /* Disable interrupts. */
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155 ulStatus &= ~hwGLOBAL_INTERRUPT_BIT;
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158 ulStatus |= hwBEV_BIT;
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160 /* Write status back. */
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161 _CP0_SET_STATUS( ulStatus );
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164 _CP0_SET_EBASE( ( unsigned long ) _ebase_address );
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166 /* Space vectors by 0x20 bytes. */
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167 _CP0_XCH_INTCTL( 0x20 );
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169 /* Set the IV bit in the CAUSE register. */
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170 ulCause = _CP0_GET_CAUSE();
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171 ulCause |= hwIV_BIT;
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172 _CP0_SET_CAUSE( ulCause );
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174 /* Clear BEV and EXL bits in status. */
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175 ulStatus &= ~( hwBEV_BIT | hwEXL_BIT );
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176 _CP0_SET_STATUS( ulStatus );
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178 /* Set MVEC bit. */
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179 INTCONbits.MVEC = 1;
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181 /* Finally enable interrupts again. */
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182 ulStatus |= hwGLOBAL_INTERRUPT_BIT;
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183 _CP0_SET_STATUS( ulStatus );
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185 /*-----------------------------------------------------------*/
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187 static void prvConfigurePeripheralBus( void )
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189 unsigned long ulDMAStatus;
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190 __OSCCONbits_t xOSCCONBits;
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192 /* Unlock after suspending. */
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193 ulDMAStatus = DMACONbits.SUSPEND;
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194 if( ulDMAStatus == 0 )
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196 DMACONSET = _DMACON_SUSPEND_MASK;
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198 /* Wait until actually suspended. */
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199 while( DMACONbits.SUSPEND == 0 );
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203 SYSKEY = hwUNLOCK_KEY_0;
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204 SYSKEY = hwUNLOCK_KEY_1;
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206 /* Read to start in sync. */
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207 xOSCCONBits.w = OSCCON;
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208 xOSCCONBits.PBDIV = 0;
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209 xOSCCONBits.w |= hwPERIPHERAL_CLOCK_DIV_BY_2;
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212 OSCCON = xOSCCONBits.w;
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214 /* Ensure the write occurred. */
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215 xOSCCONBits.w = OSCCON;
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218 SYSKEY = hwLOCK_KEY;
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220 /* Resume DMA activity. */
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221 if( ulDMAStatus == 0 )
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223 DMACONCLR=_DMACON_SUSPEND_MASK;
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226 /*-----------------------------------------------------------*/
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228 static void prvConfigureWaitStates( void )
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230 unsigned long ulSystemClock = configCPU_CLOCK_HZ - 1;
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231 unsigned long ulWaitStates, ulCHECONVal;
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233 /* 1 wait state for every hwMAX_FLASH_SPEED MHz. */
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236 while( ulSystemClock > hwMAX_FLASH_SPEED )
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239 ulSystemClock -= hwMAX_FLASH_SPEED;
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242 /* Obtain current CHECON value. */
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243 ulCHECONVal = CHECON;
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245 /* Clear the wait state bits, then set the calculated wait state bits. */
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246 ulCHECONVal &= ~hwCHECON_WAIT_STAT_BITS;
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247 ulCHECONVal |= ulWaitStates;
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249 /* Write back the new value. */
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250 CHECON = ulWaitStates;
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252 /*-----------------------------------------------------------*/
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254 static void __attribute__ ((nomips16)) prvKSeg0CacheOn( void )
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256 unsigned long ulValue;
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258 __asm volatile( "mfc0 %0, $16, 0" : "=r"( ulValue ) );
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259 ulValue = ( ulValue & ~0x07) | 0x03;
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260 __asm volatile( "mtc0 %0, $16, 0" :: "r" ( ulValue ) );
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