git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/system.log

   1 No logfile was found.\r
   2 \r
   3 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
   4 \r
   5 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
   6 \r
   7 Generating Block Diagram to Buffer
   8 \r
   9 Generated Block Diagram SVG
  10 \r
  11 The project file (XMP) has changed on disk.
  12 \r
  13 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
  14 \r
  15 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
  16 \r
  17 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
  18 \r
  19 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
  20 \r
  21 At Local date and time: Tue Jun 30 18:34:41 2009
  22  make -f system.make hwclean started...
  23 \r
  24 rm -f implementation/system.ngc\r
  25 rm -f platgen.log\r
  26 rm -f __xps/ise/_xmsgs/platgen.xmsgs\r
  27 rm -f implementation/system.bmm\r
  28 rm -f implementation/system.bit\r
  29 rm -f implementation/system.ncd\r
  30 rm -f implementation/system_bd.bmm \r
  31 rm -f implementation/system_map.ncd \r
  32 rm -f __xps/system_routed\r
  33 rm -rf implementation synthesis xst hdl\r
  34 rm -rf xst.srp system.srp\r
  35 rm -f __xps/ise/_xmsgs/bitinit.xmsgs\r
  36 \r
  37 \r
  38 Done!
  39 \r
  40 At Local date and time: Tue Jun 30 18:34:46 2009
  41  make -f system.make bitsclean started...
  42 \r
  43 rm -f implementation/system.bit\r
  44 rm -f implementation/system.ncd\r
  45 rm -f implementation/system_bd.bmm \r
  46 rm -f implementation/system_map.ncd \r
  47 rm -f __xps/system_routed\r
  48 \r
  49 \r
  50 Done!
  51 \r
  52 At Local date and time: Tue Jun 30 18:34:52 2009
  53  make -f system.make netlistclean started...
  54 \r
  55 rm -f implementation/system.ngc\r
  56 rm -f platgen.log\r
  57 rm -f __xps/ise/_xmsgs/platgen.xmsgs\r
  58 rm -f implementation/system.bmm\r
  59 \r
  60 \r
  61 Done!
  62 \r
  63 At Local date and time: Tue Jun 30 18:34:57 2009
  64  make -f system.make libsclean started...
  65 \r
  66 rm -rf ppc440_0/\r
  67 rm -f libgen.log\r
  68 rm -f __xps/ise/_xmsgs/libgen.xmsgs\r
  69 \r
  70 \r
  71 Done!
  72 \r
  73 At Local date and time: Tue Jun 30 18:35:02 2009
  74  make -f system.make programclean started...
  75 \r
  76 rm -f RTOSDemo/executable.elf \r
  77 \r
  78 \r
  79 Done!
  80 \r
  81 At Local date and time: Tue Jun 30 18:35:08 2009
  82  make -f system.make swclean started...
  83 \r
  84 rm -rf ppc440_0/\r
  85 rm -f libgen.log\r
  86 rm -f __xps/ise/_xmsgs/libgen.xmsgs\r
  87 rm -f RTOSDemo/executable.elf \r
  88 \r
  89 \r
  90 Done!
  91 \r
  92 Writing filter settings....
  93 \r
  94 Done writing filter settings to:
  95         C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
  96 \r
  97 Done writing Tab View settings to:
  98         C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\__xps\system.gui
  99 \r
 100 Xilinx Platform Studio (XPS)\r
 101 Xilinx EDK 11.2 Build EDK_LS3.47
 102 \r
 103 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
 104 \r
 105 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
 106 \r
 107 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
 108 \r
 109 Generating Block Diagram to Buffer
 110 \r
 111 Generated Block Diagram SVG
 112 \r
 113 At Local date and time: Fri Jul 03 21:23:32 2009
 114  make -f system.make bits started...
 115 \r
 116 ****************************************************\r
 117 Creating system netlist for hardware specification..\r
 118 ****************************************************\r
 119 platgen -p xc5vfx70tff1136-1 -lang vhdl   -msg __xps/ise/xmsgprops.lst system.mhs\r
 120 \r\r
 121 Release 11.2 - platgen Xilinx EDK 11.2 Build EDK_LS3.47\r\r
 122  (nt)\r\r
 123 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
 124 \r\r
 125 \r\r
 126 Command Line: platgen -p xc5vfx70tff1136-1 -lang vhdl -msg\r\r
 127 __xps/ise/xmsgprops.lst system.mhs \r\r
 128 \r\r
 129 Parse\r\r
 130 C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/system.mhs\r\r
 131 ...\r\r
 132 \r\r
 133 Read MPD definitions ...\r\r
 134 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
 135    C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
 136    hs line 253 - deprecated core for architecture 'virtex5fx'!\r\r
 137 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
 138    C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
 139    hs line 298 - deprecated core for architecture 'virtex5fx'!\r\r
 140 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
 141    C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
 142    hs line 253 - deprecated core for architecture 'virtex5fx'!\r\r
 143 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
 144    C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
 145    hs line 298 - deprecated core for architecture 'virtex5fx'!\r\r
 146 \r\r
 147 Overriding IP level properties ...\r\r
 148 \r\r
 149 Performing IP level DRCs on properties...\r\r
 150 \r\r
 151 Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...\r\r
 152 Address Map for Processor ppc440_0\r\r
 153   (0b0000000000-0b0011111111) ppc440_0  \r\r
 154   (0000000000-0x0fffffff) DDR2_SDRAM    ppc440_0_PPC440MC\r\r
 155   (0x81000000-0x8100ffff) Ethernet_MAC  plb_v46_0\r\r
 156   (0x81400000-0x8140ffff) Push_Buttons_5Bit     plb_v46_0\r\r
 157   (0x81420000-0x8142ffff) LEDs_Positions        plb_v46_0\r\r
 158   (0x81440000-0x8144ffff) LEDs_8Bit     plb_v46_0\r\r
 159   (0x81460000-0x8146ffff) DIP_Switches_8Bit     plb_v46_0\r\r
 160   (0x81600000-0x8160ffff) IIC_EEPROM    plb_v46_0\r\r
 161   (0x81800000-0x8180ffff) xps_intc_0    plb_v46_0\r\r
 162   (0x83600000-0x8360ffff) SysACE_CompactFlash   plb_v46_0\r\r
 163   (0x84000000-0x8400ffff) RS232_Uart_1  plb_v46_0\r\r
 164   (0x85c00000-0x85c0ffff) PCIe_Bridge   plb_v46_0\r\r
 165   (0xc0000000-0xdfffffff) PCIe_Bridge   plb_v46_0\r\r
 166   (0xe0000000-0xefffffff) PCIe_Bridge   plb_v46_0\r\r
 167   (0xf8000000-0xf80fffff) SRAM  plb_v46_0\r\r
 168   (0xffffe000-0xffffffff) xps_bram_if_cntlr_1   plb_v46_0\r\r
 169 INFO:EDK:1560 - IPNAME:ppc440_virtex5 INSTANCE:ppc440_0 -\r\r
 170    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_\r\r
 171    01_a\data\ppc440_virtex5_v2_1_0.mpd line 175 - tool is overriding PARAMETER\r\r
 172    C_SPLB0_P2P value to 0\r\r
 173 \r\r
 174 Computing clock values...\r\r
 175 INFO:EDK:1432 - Frequency for Top-Level Input Clock\r\r
 176    'fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin' is not specified. Clock DRCs will not be\r\r
 177    performed for IPs connected to that clock port, unless they are connected\r\r
 178    through the clock generator IP. \r\r
 179 \r\r
 180 INFO:EDK:1432 - Frequency for Top-Level Input Clock\r\r
 181    'fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin' is not specified. Clock DRCs will not be\r\r
 182    performed for IPs connected to that clock port, unless they are connected\r\r
 183    through the clock generator IP. \r\r
 184 \r\r
 185 INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
 186    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
 187    ta\plb_v46_v2_1_0.mpd line 70 - tool is overriding PARAMETER\r\r
 188    C_PLBV46_NUM_MASTERS value to 1\r\r
 189 INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
 190    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
 191    ta\plb_v46_v2_1_0.mpd line 71 - tool is overriding PARAMETER\r\r
 192    C_PLBV46_NUM_SLAVES value to 12\r\r
 193 INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
 194    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
 195    ta\plb_v46_v2_1_0.mpd line 72 - tool is overriding PARAMETER\r\r
 196    C_PLBV46_MID_WIDTH value to 1\r\r
 197 INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
 198    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
 199    ta\plb_v46_v2_1_0.mpd line 74 - tool is overriding PARAMETER C_PLBV46_DWIDTH\r\r
 200    value to 128\r\r
 201 INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -\r\r
 202    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_\r\r
 203    v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 75 - tool is overriding\r\r
 204    PARAMETER C_SPLB_DWIDTH value to 128\r\r
 205 INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -\r\r
 206    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_\r\r
 207    v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 76 - tool is overriding\r\r
 208    PARAMETER C_SPLB_NUM_MASTERS value to 1\r\r
 209 INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -\r\r
 210    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_\r\r
 211    v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 80 - tool is overriding\r\r
 212    PARAMETER C_SPLB_SMALLEST_MASTER value to 128\r\r
 213 INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
 214    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\r\r
 215    \data\bram_block_v2_1_0.mpd line 69 - tool is overriding PARAMETER C_MEMSIZE\r\r
 216    value to 0x2000\r\r
 217 INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
 218    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\r\r
 219    \data\bram_block_v2_1_0.mpd line 70 - tool is overriding PARAMETER\r\r
 220    C_PORT_DWIDTH value to 64\r\r
 221 INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
 222    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\r\r
 223    \data\bram_block_v2_1_0.mpd line 72 - tool is overriding PARAMETER C_NUM_WE\r\r
 224    value to 8\r\r
 225 INFO:EDK:1560 - IPNAME:xps_uartlite INSTANCE:RS232_Uart_1 -\r\r
 226    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_uartlite_v1_01\r\r
 227    _a\data\xps_uartlite_v2_1_0.mpd line 73 - tool is overriding PARAMETER\r\r
 228    C_SPLB_DWIDTH value to 128\r\r
 229 INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:LEDs_8Bit -\r\r
 230    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
 231    ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
 232    value to 128\r\r
 233 INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:LEDs_Positions -\r\r
 234    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
 235    ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
 236    value to 128\r\r
 237 INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:Push_Buttons_5Bit -\r\r
 238    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
 239    ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
 240    value to 128\r\r
 241 INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:DIP_Switches_8Bit -\r\r
 242    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
 243    ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
 244    value to 128\r\r
 245 INFO:EDK:1560 - IPNAME:xps_iic INSTANCE:IIC_EEPROM -\r\r
 246    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_iic_v2_01_a\da\r\r
 247    ta\xps_iic_v2_1_0.mpd line 79 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
 248    value to 128\r\r
 249 INFO:EDK:1560 - IPNAME:xps_mch_emc INSTANCE:SRAM -\r\r
 250    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_\r\r
 251    a\data\xps_mch_emc_v2_1_0.mpd line 82 - tool is overriding PARAMETER\r\r
 252    C_SPLB_DWIDTH value to 128\r\r
 253 INFO:EDK:1560 - IPNAME:xps_mch_emc INSTANCE:SRAM -\r\r
 254    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_\r\r
 255    a\data\xps_mch_emc_v2_1_0.mpd line 84 - tool is overriding PARAMETER\r\r
 256    C_SPLB_SMALLEST_MASTER value to 128\r\r
 257 INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
 258    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
 259    b\data\plbv46_pcie_v2_1_0.mpd line 86 - tool is overriding PARAMETER\r\r
 260    C_MPLB_DWIDTH value to 128\r\r
 261 INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
 262    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
 263    b\data\plbv46_pcie_v2_1_0.mpd line 87 - tool is overriding PARAMETER\r\r
 264    C_MPLB_SMALLEST_SLAVE value to 128\r\r
 265 INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
 266    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
 267    b\data\plbv46_pcie_v2_1_0.mpd line 89 - tool is overriding PARAMETER\r\r
 268    C_SPLB_MID_WIDTH value to 1\r\r
 269 INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
 270    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
 271    b\data\plbv46_pcie_v2_1_0.mpd line 90 - tool is overriding PARAMETER\r\r
 272    C_SPLB_NUM_MASTERS value to 1\r\r
 273 INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
 274    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
 275    b\data\plbv46_pcie_v2_1_0.mpd line 91 - tool is overriding PARAMETER\r\r
 276    C_SPLB_SMALLEST_MASTER value to 128\r\r
 277 INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
 278    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
 279    b\data\plbv46_pcie_v2_1_0.mpd line 95 - tool is overriding PARAMETER\r\r
 280    C_SPLB_DWIDTH value to 128\r\r
 281 INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
 282    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
 283    ta\plb_v46_v2_1_0.mpd line 70 - tool is overriding PARAMETER\r\r
 284    C_PLBV46_NUM_MASTERS value to 1\r\r
 285 INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
 286    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
 287    ta\plb_v46_v2_1_0.mpd line 71 - tool is overriding PARAMETER\r\r
 288    C_PLBV46_NUM_SLAVES value to 1\r\r
 289 INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
 290    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
 291    ta\plb_v46_v2_1_0.mpd line 72 - tool is overriding PARAMETER\r\r
 292    C_PLBV46_MID_WIDTH value to 1\r\r
 293 INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
 294    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
 295    ta\plb_v46_v2_1_0.mpd line 74 - tool is overriding PARAMETER C_PLBV46_DWIDTH\r\r
 296    value to 128\r\r
 297 INFO:EDK:1560 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
 298    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_ethernetlite_v\r\r
 299    2_01_a\data\xps_ethernetlite_v2_1_0.mpd line 75 - tool is overriding\r\r
 300    PARAMETER C_SPLB_DWIDTH value to 128\r\r
 301 INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -\r\r
 302    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a\r\r
 303    \data\xps_sysace_v2_1_0.mpd line 72 - tool is overriding PARAMETER\r\r
 304    C_SPLB_DWIDTH value to 128\r\r
 305 INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -\r\r
 306    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a\r\r
 307    \data\xps_sysace_v2_1_0.mpd line 74 - tool is overriding PARAMETER\r\r
 308    C_SPLB_MID_WIDTH value to 1\r\r
 309 INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -\r\r
 310    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a\r\r
 311    \data\xps_sysace_v2_1_0.mpd line 75 - tool is overriding PARAMETER\r\r
 312    C_SPLB_NUM_MASTERS value to 1\r\r
 313 INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -\r\r
 314    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d\r\r
 315    ata\xps_intc_v2_1_0.mpd line 72 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
 316    value to 128\r\r
 317 \r\r
 318 Checking platform address map ...\r\r
 319 \r\r
 320 Checking platform configuration ...\r\r
 321 INFO:EDK:1563 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
 322    C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
 323    hs line 298 - This design requires design constraints to guarantee\r\r
 324    performance.\r\r
 325    Please refer to the xps_ethernetlite_v2_00_a data sheet for details.  \r\r
 326    The PLB clock frequency must be greater than or equal to 50 MHz for 100 Mbs\r\r
 327    Ethernet operation and greater than or equal to 5.0 MHz for 10 Mbs Ethernet\r\r
 328    operation.\r\r
 329 IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
 330 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 331 line 109 - 1 master(s) : 12 slave(s)\r\r
 332 IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
 333 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 334 line 290 - 1 master(s) : 1 slave(s)\r\r
 335 IPNAME:fcb_v20 INSTANCE:ppc440_0_fcb_v20 -\r\r
 336 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 337 line 394 - 1 master(s) : 1 slave(s)\r\r
 338 \r\r
 339 Checking port drivers...\r\r
 340 WARNING:EDK:2099 - PORT:Peripheral_Reset CONNECTOR:sys_periph_reset -\r\r
 341    C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
 342    hs line 462 - floating connection!\r\r
 343 \r\r
 344 Performing Clock DRCs...\r\r
 345 \r\r
 346 Performing Reset DRCs...\r\r
 347 \r\r
 348 Overriding system level properties...\r\r
 349 INFO:EDK:1560 - IPNAME:ppc440_virtex5 INSTANCE:ppc440_0 -\r\r
 350    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_\r\r
 351    01_a\data\ppc440_virtex5_v2_1_0.mpd line 124 - tcl is overriding PARAMETER\r\r
 352    C_PPC440MC_ADDR_BASE value to 0x00000000\r\r
 353 INFO:EDK:1560 - IPNAME:ppc440_virtex5 INSTANCE:ppc440_0 -\r\r
 354    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_\r\r
 355    01_a\data\ppc440_virtex5_v2_1_0.mpd line 125 - tcl is overriding PARAMETER\r\r
 356    C_PPC440MC_ADDR_HIGH value to 0x0fffffff\r\r
 357 INFO:EDK:1560 - IPNAME:jtagppc_cntlr INSTANCE:jtagppc_cntlr_inst -\r\r
 358    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\jtagppc_cntlr_v2_0\r\r
 359    1_c\data\jtagppc_cntlr_v2_1_0.mpd line 70 - tcl is overriding PARAMETER\r\r
 360    C_NUM_PPC_USED value to 1\r\r
 361 INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -\r\r
 362    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d\r\r
 363    ata\xps_intc_v2_1_0.mpd line 79 - tcl is overriding PARAMETER C_KIND_OF_INTR\r\r
 364    value to 0b00000000000000000000000000000001\r\r
 365 INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -\r\r
 366    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d\r\r
 367    ata\xps_intc_v2_1_0.mpd line 80 - tcl is overriding PARAMETER C_KIND_OF_EDGE\r\r
 368    value to 0b00000000000000000000000000000001\r\r
 369 INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -\r\r
 370    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d\r\r
 371    ata\xps_intc_v2_1_0.mpd line 81 - tcl is overriding PARAMETER C_KIND_OF_LVL\r\r
 372    value to 0b00000000000000000000000000000000\r\r
 373 \r\r
 374 Running system level update procedures...\r\r
 375 \r\r
 376 Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...\r\r
 377 \r\r
 378 Running system level DRCs...\r\r
 379 \r\r
 380 Performing System level DRCs on properties...\r\r
 381 \r\r
 382 Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...\r\r
 383 \r\r
 384 Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...\r\r
 385 INFO: The PCIe_Bridge core has constraints automatically generated by XPS in\r\r
 386 implementation/pcie_bridge_wrapper/pcie_bridge_wrapper.ucf.\r\r\r
 387 It can be overridden by constraints placed in the system.ucf file.\r\r\r
 388 \r\r
 389 \r\r\r
 390 \r\r
 391 INFO: The Ethernet_MAC core has constraints automatically generated by XPS in\r\r
 392 implementation/ethernet_mac_wrapper/ethernet_mac_wrapper.ucf.\r\r\r
 393 It can be overridden by constraints placed in the system.ucf file.\r\r\r
 394 \r\r
 395 \r\r\r
 396 \r\r
 397 INFO: The DDR2_SDRAM core has constraints automatically generated by XPS in\r\r
 398 implementation/ddr2_sdram_wrapper/ddr2_sdram_wrapper.ucf.\r\r\r
 399 It can be overridden by constraints placed in the system.ucf file.\r\r\r
 400 \r\r
 401 \r\r\r
 402 \r\r
 403 \r\r
 404 Modify defaults ...\r\r
 405 \r\r
 406 Creating stub ...\r\r
 407 \r\r
 408 Processing licensed instances ...\r\r
 409 Completion time: 0.00 seconds\r\r
 410 \r\r
 411 Creating hardware output directories ...\r\r
 412 \r\r
 413 Managing hardware (BBD-specified) netlist files ...\r\r
 414 IPNAME:plbv46_pcie INSTANCE:pcie_bridge -\r\r
 415 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 416 line 253 - Copying (BBD-specified) netlist files.\r\r
 417 IPNAME:xps_ethernetlite INSTANCE:ethernet_mac -\r\r
 418 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 419 line 298 - Copying (BBD-specified) netlist files.\r\r
 420 IPNAME:apu_fpu_virtex5 INSTANCE:ppc440_0_apu_fpu_virtex5 -\r\r
 421 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 422 line 401 - Copying (BBD-specified) netlist files.\r\r
 423 \r\r
 424 Managing cache ...\r\r
 425 \r\r
 426 Elaborating instances ...\r\r
 427 IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
 428 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 429 line 131 - elaborating IP\r\r
 430 \r\r
 431 Writing HDL for elaborated instances ...\r\r
 432 \r\r
 433 Inserting wrapper level ...\r\r
 434 Completion time: 2.00 seconds\r\r
 435 \r\r
 436 Constructing platform-level connectivity ...\r\r
 437 Completion time: 1.00 seconds\r\r
 438 \r\r
 439 Writing (top-level) BMM ...\r\r
 440 \r\r
 441 Writing (top-level and wrappers) HDL ...\r\r
 442 \r\r
 443 Generating synthesis project file ...\r\r
 444 \r\r
 445 Running XST synthesis ...\r\r
 446 \r\r
 447 INFO:EDK:2502 - The following instances are synthesized with XST. The MPD option\r\r
 448    IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST\r\r
 449    synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized. \r\r
 450 INSTANCE:ppc440_0 -\r\r
 451 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 452 line 78 - Running XST synthesis\r\r
 453 INSTANCE:plb_v46_0 -\r\r
 454 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 455 line 109 - Running XST synthesis\r\r
 456 INSTANCE:xps_bram_if_cntlr_1 -\r\r
 457 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 458 line 118 - Running XST synthesis\r\r
 459 INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
 460 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 461 line 131 - Running XST synthesis\r\r
 462 INSTANCE:rs232_uart_1 -\r\r
 463 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 464 line 138 - Running XST synthesis\r\r
 465 INSTANCE:leds_8bit -\r\r
 466 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 467 line 154 - Running XST synthesis\r\r
 468 INSTANCE:leds_positions -\r\r
 469 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 470 line 168 - Running XST synthesis\r\r
 471 INSTANCE:push_buttons_5bit -\r\r
 472 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 473 line 182 - Running XST synthesis\r\r
 474 INSTANCE:dip_switches_8bit -\r\r
 475 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 476 line 196 - Running XST synthesis\r\r
 477 INSTANCE:iic_eeprom -\r\r
 478 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 479 line 210 - Running XST synthesis\r\r
 480 INSTANCE:sram -\r\r
 481 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 482 line 223 - Running XST synthesis\r\r
 483 INSTANCE:pcie_bridge -\r\r
 484 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 485 line 253 - Running XST synthesis\r\r
 486 INSTANCE:ppc440_0_splb0 -\r\r
 487 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 488 line 290 - Running XST synthesis\r\r
 489 INSTANCE:ethernet_mac -\r\r
 490 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 491 line 298 - Running XST synthesis\r\r
 492 INSTANCE:ddr2_sdram -\r\r
 493 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 494 line 317 - Running XST synthesis\r\r
 495 INSTANCE:sysace_compactflash -\r\r
 496 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 497 line 377 - Running XST synthesis\r\r
 498 INSTANCE:ppc440_0_fcb_v20 -\r\r
 499 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 500 line 394 - Running XST synthesis\r\r
 501 INSTANCE:ppc440_0_apu_fpu_virtex5 -\r\r
 502 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 503 line 401 - Running XST synthesis\r\r
 504 INSTANCE:clock_generator_0 -\r\r
 505 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 506 line 408 - Running XST synthesis\r\r
 507 INSTANCE:jtagppc_cntlr_inst -\r\r
 508 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 509 line 447 - Running XST synthesis\r\r
 510 INSTANCE:proc_sys_reset_0 -\r\r
 511 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 512 line 453 - Running XST synthesis\r\r
 513 INSTANCE:xps_intc_0 -\r\r
 514 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 515 line 465 - Running XST synthesis\r\r
 516 \r\r
 517 Running NGCBUILD ...\r\r
 518 IPNAME:ppc440_0_wrapper INSTANCE:ppc440_0 -\r\r
 519 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 520 line 78 - Running NGCBUILD\r\r
 521 PMSPEC -- Overriding Xilinx file\r\r
 522 <C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
 523 <C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
 524 \r\r
 525 Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p\r\r
 526 xc5vfx70tff1136-1 -intstyle silent -uc ppc440_0_wrapper.ucf -sd ..\r\r
 527 ppc440_0_wrapper.ngc ../ppc440_0_wrapper.ngc\r\r
 528 \r\r
 529 Reading NGO file\r\r
 530 "C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/implementa\r\r
 531 tion/ppc440_0_wrapper/ppc440_0_wrapper.ngc" ...\r\r
 532 \r\r
 533 Applying constraints in "ppc440_0_wrapper.ucf" to the design...\r\r
 534 \r\r
 535 Partition Implementation Status\r\r
 536 -------------------------------\r\r
 537 \r\r
 538   No Partitions were found in this design.\r\r
 539 \r\r
 540 -------------------------------\r\r
 541 \r\r
 542 NGCBUILD Design Results Summary:\r\r
 543   Number of errors:     0\r\r
 544   Number of warnings:   0\r\r
 545 \r\r
 546 Writing NGC file "../ppc440_0_wrapper.ngc" ...\r\r
 547 Total REAL time to NGCBUILD completion:  7 sec\r\r
 548 Total CPU time to NGCBUILD completion:   5 sec\r\r
 549 \r\r
 550 Writing NGCBUILD log file "../ppc440_0_wrapper.blc"...\r\r
 551 \r\r
 552 NGCBUILD done.\r\r
 553 IPNAME:rs232_uart_1_wrapper INSTANCE:rs232_uart_1 -\r\r
 554 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 555 line 138 - Running NGCBUILD\r\r
 556 PMSPEC -- Overriding Xilinx file\r\r
 557 <C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
 558 <C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
 559 \r\r
 560 Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p\r\r
 561 xc5vfx70tff1136-1 -intstyle silent -sd .. rs232_uart_1_wrapper.ngc\r\r
 562 ../rs232_uart_1_wrapper.ngc\r\r
 563 \r\r
 564 Reading NGO file\r\r
 565 "C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/implementa\r\r
 566 tion/rs232_uart_1_wrapper/rs232_uart_1_wrapper.ngc" ...\r\r
 567 \r\r
 568 Partition Implementation Status\r\r
 569 -------------------------------\r\r
 570 \r\r
 571   No Partitions were found in this design.\r\r
 572 \r\r
 573 -------------------------------\r\r
 574 \r\r
 575 NGCBUILD Design Results Summary:\r\r
 576   Number of errors:     0\r\r
 577   Number of warnings:   0\r\r
 578 \r\r
 579 Writing NGC file "../rs232_uart_1_wrapper.ngc" ...\r\r
 580 Total REAL time to NGCBUILD completion:  2 sec\r\r
 581 Total CPU time to NGCBUILD completion:   1 sec\r\r
 582 \r\r
 583 Writing NGCBUILD log file "../rs232_uart_1_wrapper.blc"...\r\r
 584 \r\r
 585 NGCBUILD done.\r\r
 586 IPNAME:pcie_bridge_wrapper INSTANCE:pcie_bridge -\r\r
 587 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 588 line 253 - Running NGCBUILD\r\r
 589 PMSPEC -- Overriding Xilinx file\r\r
 590 <C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
 591 <C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
 592 \r\r
 593 Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p\r\r
 594 xc5vfx70tff1136-1 -intstyle silent -uc pcie_bridge_wrapper.ucf -sd ..\r\r
 595 pcie_bridge_wrapper.ngc ../pcie_bridge_wrapper.ngc\r\r
 596 \r\r
 597 Reading NGO file\r\r
 598 "C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/implementa\r\r
 599 tion/pcie_bridge_wrapper/pcie_bridge_wrapper.ngc" ...\r\r
 600 Executing edif2ngd -noa\r\r
 601 "C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\implementa\r\r
 602 tion\pcie_bridge_wrapper_fifo_generator_v4_3.edn"\r\r
 603 "pcie_bridge_wrapper_fifo_generator_v4_3.ngo"\r\r
 604 Release 11.2 - edif2ngd L.46 (nt)\r\r
 605 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
 606 INFO:NgdBuild - Release 11.2 edif2ngd L.46 (nt)\r\r
 607 INFO:NgdBuild - Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
 608 PMSPEC -- Overriding Xilinx file <C:/devtools/Xilinx/11.1/EDK/data/edif2ngd.pfd>\r\r
 609 with local file <C:/devtools/Xilinx/11.1/ISE/data/edif2ngd.pfd>\r\r
 610 Writing module to "pcie_bridge_wrapper_fifo_generator_v4_3.ngo"...\r\r
 611 Loading design module\r\r
 612 "C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\implementa\r\r
 613 tion\pcie_bridge_wrapper\pcie_bridge_wrapper_fifo_generator_v4_3.ngo"...\r\r
 614 Loading design module\r\r
 615 "../pcie_bridge_wrapper_fifo_generator_v4_3_fifo_generator_v4_3_xst_1.ngc"...\r\r
 616 Loading design module\r\r
 617 "C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\implementa\r\r
 618 tion\pcie_bridge_wrapper/dpram_70_512.ngc"...\r\r
 619 Loading design module\r\r
 620 "C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\implementa\r\r
 621 tion\pcie_bridge_wrapper/fifo_71x512.ngc"...\r\r
 622 \r\r
 623 Applying constraints in "pcie_bridge_wrapper.ucf" to the design...\r\r
 624 \r\r
 625 Partition Implementation Status\r\r
 626 -------------------------------\r\r
 627 \r\r
 628   No Partitions were found in this design.\r\r
 629 \r\r
 630 -------------------------------\r\r
 631 \r\r
 632 NGCBUILD Design Results Summary:\r\r
 633   Number of errors:     0\r\r
 634   Number of warnings:   0\r\r
 635 \r\r
 636 Writing NGC file "../pcie_bridge_wrapper.ngc" ...\r\r
 637 Total REAL time to NGCBUILD completion:  13 sec\r\r
 638 Total CPU time to NGCBUILD completion:   7 sec\r\r
 639 \r\r
 640 Writing NGCBUILD log file "../pcie_bridge_wrapper.blc"...\r\r
 641 \r\r
 642 NGCBUILD done.\r\r
 643 IPNAME:ethernet_mac_wrapper INSTANCE:ethernet_mac -\r\r
 644 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 645 line 298 - Running NGCBUILD\r\r
 646 PMSPEC -- Overriding Xilinx file\r\r
 647 <C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
 648 <C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
 649 \r\r
 650 Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p\r\r
 651 xc5vfx70tff1136-1 -intstyle silent -uc ethernet_mac_wrapper.ucf -sd ..\r\r
 652 ethernet_mac_wrapper.ngc ../ethernet_mac_wrapper.ngc\r\r
 653 \r\r
 654 Reading NGO file\r\r
 655 "C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/implementa\r\r
 656 tion/ethernet_mac_wrapper/ethernet_mac_wrapper.ngc" ...\r\r
 657 Executing edif2ngd -noa "ethernetlite_v1_01_b_dmem_v2.edn"\r\r
 658 "ethernetlite_v1_01_b_dmem_v2.ngo"\r\r
 659 Release 11.2 - edif2ngd L.46 (nt)\r\r
 660 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
 661 INFO:NgdBuild - Release 11.2 edif2ngd L.46 (nt)\r\r
 662 INFO:NgdBuild - Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
 663 PMSPEC -- Overriding Xilinx file <C:/devtools/Xilinx/11.1/EDK/data/edif2ngd.pfd>\r\r
 664 with local file <C:/devtools/Xilinx/11.1/ISE/data/edif2ngd.pfd>\r\r
 665 Writing module to "ethernetlite_v1_01_b_dmem_v2.ngo"...\r\r
 666 Loading design module\r\r
 667 "C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\implementa\r\r
 668 tion\ethernet_mac_wrapper\ethernetlite_v1_01_b_dmem_v2.ngo"...\r\r
 669 \r\r
 670 Applying constraints in "ethernet_mac_wrapper.ucf" to the design...\r\r
 671 \r\r
 672 Partition Implementation Status\r\r
 673 -------------------------------\r\r
 674 \r\r
 675   No Partitions were found in this design.\r\r
 676 \r\r
 677 -------------------------------\r\r
 678 \r\r
 679 NGCBUILD Design Results Summary:\r\r
 680   Number of errors:     0\r\r
 681   Number of warnings:   0\r\r
 682 \r\r
 683 Writing NGC file "../ethernet_mac_wrapper.ngc" ...\r\r
 684 Total REAL time to NGCBUILD completion:  8 sec\r\r
 685 Total CPU time to NGCBUILD completion:   5 sec\r\r
 686 \r\r
 687 Writing NGCBUILD log file "../ethernet_mac_wrapper.blc"...\r\r
 688 \r\r
 689 NGCBUILD done.\r\r
 690 IPNAME:ddr2_sdram_wrapper INSTANCE:ddr2_sdram -\r\r
 691 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 692 line 317 - Running NGCBUILD\r\r
 693 PMSPEC -- Overriding Xilinx file\r\r
 694 <C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
 695 <C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
 696 \r\r
 697 Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p\r\r
 698 xc5vfx70tff1136-1 -intstyle silent -uc ddr2_sdram_wrapper.ucf -sd ..\r\r
 699 ddr2_sdram_wrapper.ngc ../ddr2_sdram_wrapper.ngc\r\r
 700 \r\r
 701 Reading NGO file\r\r
 702 "C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/implementa\r\r
 703 tion/ddr2_sdram_wrapper/ddr2_sdram_wrapper.ngc" ...\r\r
 704 \r\r
 705 Applying constraints in "ddr2_sdram_wrapper.ucf" to the design...\r\r
 706 \r\r
 707 Partition Implementation Status\r\r
 708 -------------------------------\r\r
 709 \r\r
 710   No Partitions were found in this design.\r\r
 711 \r\r
 712 -------------------------------\r\r
 713 \r\r
 714 NGCBUILD Design Results Summary:\r\r
 715   Number of errors:     0\r\r
 716   Number of warnings:   0\r\r
 717 \r\r
 718 Writing NGC file "../ddr2_sdram_wrapper.ngc" ...\r\r
 719 Total REAL time to NGCBUILD completion:  6 sec\r\r
 720 Total CPU time to NGCBUILD completion:   5 sec\r\r
 721 \r\r
 722 Writing NGCBUILD log file "../ddr2_sdram_wrapper.blc"...\r\r
 723 \r\r
 724 NGCBUILD done.\r\r
 725 IPNAME:ppc440_0_apu_fpu_virtex5_wrapper INSTANCE:ppc440_0_apu_fpu_virtex5 -\r\r
 726 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 727 line 401 - Running NGCBUILD\r\r
 728 PMSPEC -- Overriding Xilinx file\r\r
 729 <C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
 730 <C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
 731 \r\r
 732 Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p\r\r
 733 xc5vfx70tff1136-1 -intstyle silent -uc ppc440_0_apu_fpu_virtex5_wrapper.ucf -sd\r\r
 734 .. ppc440_0_apu_fpu_virtex5_wrapper.ngc ../ppc440_0_apu_fpu_virtex5_wrapper.ngc\r\r
 735 \r\r
 736 Reading NGO file\r\r
 737 "C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/implementa\r\r
 738 tion/ppc440_0_apu_fpu_virtex5_wrapper/ppc440_0_apu_fpu_virtex5_wrapper.ngc" ...\r\r
 739 Loading design module\r\r
 740 "C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\implementa\r\r
 741 tion\ppc440_0_apu_fpu_virtex5_wrapper/apu_fpu_sp_lo.ngc"...\r\r
 742 \r\r
 743 Applying constraints in "ppc440_0_apu_fpu_virtex5_wrapper.ucf" to the design...\r\r
 744 \r\r
 745 Partition Implementation Status\r\r
 746 -------------------------------\r\r
 747 \r\r
 748   No Partitions were found in this design.\r\r
 749 \r\r
 750 -------------------------------\r\r
 751 \r\r
 752 NGCBUILD Design Results Summary:\r\r
 753   Number of errors:     0\r\r
 754   Number of warnings:   0\r\r
 755 \r\r
 756 Writing NGC file "../ppc440_0_apu_fpu_virtex5_wrapper.ngc" ...\r\r
 757 Total REAL time to NGCBUILD completion:  6 sec\r\r
 758 Total CPU time to NGCBUILD completion:   5 sec\r\r
 759 \r\r
 760 Writing NGCBUILD log file "../ppc440_0_apu_fpu_virtex5_wrapper.blc"...\r\r
 761 \r\r
 762 NGCBUILD done.\r\r
 763 IPNAME:xps_intc_0_wrapper INSTANCE:xps_intc_0 -\r\r
 764 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
 765 line 465 - Running NGCBUILD\r\r
 766 PMSPEC -- Overriding Xilinx file\r\r
 767 <C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
 768 <C:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
 769 \r\r
 770 Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p\r\r
 771 xc5vfx70tff1136-1 -intstyle silent -sd .. xps_intc_0_wrapper.ngc\r\r
 772 ../xps_intc_0_wrapper.ngc\r\r
 773 \r\r
 774 Reading NGO file\r\r
 775 "C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/implementa\r\r
 776 tion/xps_intc_0_wrapper/xps_intc_0_wrapper.ngc" ...\r\r
 777 \r\r
 778 Partition Implementation Status\r\r
 779 -------------------------------\r\r
 780 \r\r
 781   No Partitions were found in this design.\r\r
 782 \r\r
 783 -------------------------------\r\r
 784 \r\r
 785 NGCBUILD Design Results Summary:\r\r
 786   Number of errors:     0\r\r
 787   Number of warnings:   0\r\r
 788 \r\r
 789 Writing NGC file "../xps_intc_0_wrapper.ngc" ...\r\r
 790 Total REAL time to NGCBUILD completion:  2 sec\r\r
 791 Total CPU time to NGCBUILD completion:   1 sec\r\r
 792 \r\r
 793 Writing NGCBUILD log file "../xps_intc_0_wrapper.blc"...\r\r
 794 \r\r
 795 NGCBUILD done.\r\r
 796 \r\r
 797 Rebuilding cache ...\r\r
 798 \r\r
 799 Total run time: 1330.00 seconds\r\r
 800 Running synthesis...\r
 801 bash -c "cd synthesis; ./synthesis.sh"\r
 802 xst -ifn system_xst.scr -intstyle silent\r
 803 Running XST synthesis ...\r
 804 XST completed\r
 805 Release 11.2 - ngcbuild L.46 (nt)\r\r
 806 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
 807 Overriding Xilinx file <ngcflow.csf> with local file\r\r
 808 <c:/devtools/Xilinx/11.1/ISE/data/ngcflow.csf>\r\r
 809 \r\r
 810 Command Line: c:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe\r\r
 811 ./system.ngc ../implementation/system.ngc -sd ../implementation -i -ise\r\r
 812 ../__xps/ise/system.ise\r\r
 813 \r\r
 814 Reading NGO file\r\r
 815 "c:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/synthesis/\r\r
 816 system.ngc" ...\r\r
 817 Loading design module "../implementation/ppc440_0_wrapper.ngc"...\r\r
 818 Loading design module "../implementation/plb_v46_0_wrapper.ngc"...\r\r
 819 Loading design module "../implementation/xps_bram_if_cntlr_1_wrapper.ngc"...\r\r
 820 Loading design module\r\r
 821 "../implementation/xps_bram_if_cntlr_1_bram_wrapper.ngc"...\r\r
 822 Loading design module "../implementation/rs232_uart_1_wrapper.ngc"...\r\r
 823 Loading design module "../implementation/leds_8bit_wrapper.ngc"...\r\r
 824 Loading design module "../implementation/leds_positions_wrapper.ngc"...\r\r
 825 Loading design module "../implementation/push_buttons_5bit_wrapper.ngc"...\r\r
 826 Loading design module "../implementation/dip_switches_8bit_wrapper.ngc"...\r\r
 827 Loading design module "../implementation/iic_eeprom_wrapper.ngc"...\r\r
 828 Loading design module "../implementation/sram_wrapper.ngc"...\r\r
 829 Loading design module "../implementation/pcie_bridge_wrapper.ngc"...\r\r
 830 Loading design module "../implementation/ppc440_0_splb0_wrapper.ngc"...\r\r
 831 Loading design module "../implementation/ethernet_mac_wrapper.ngc"...\r\r
 832 Loading design module "../implementation/ddr2_sdram_wrapper.ngc"...\r\r
 833 Loading design module "../implementation/sysace_compactflash_wrapper.ngc"...\r\r
 834 Loading design module "../implementation/ppc440_0_fcb_v20_wrapper.ngc"...\r\r
 835 Loading design module\r\r
 836 "../implementation/ppc440_0_apu_fpu_virtex5_wrapper.ngc"...\r\r
 837 Loading design module "../implementation/clock_generator_0_wrapper.ngc"...\r\r
 838 Loading design module "../implementation/jtagppc_cntlr_inst_wrapper.ngc"...\r\r
 839 Loading design module "../implementation/proc_sys_reset_0_wrapper.ngc"...\r\r
 840 Loading design module "../implementation/xps_intc_0_wrapper.ngc"...\r\r
 841 \r\r
 842 Partition Implementation Status\r\r
 843 -------------------------------\r\r
 844 \r\r
 845   No Partitions were found in this design.\r\r
 846 \r\r
 847 -------------------------------\r\r
 848 \r\r
 849 NGCBUILD Design Results Summary:\r\r
 850   Number of errors:     0\r\r
 851   Number of warnings:   0\r\r
 852 \r\r
 853 Writing NGC file "../implementation/system.ngc" ...\r\r
 854 Total REAL time to NGCBUILD completion:  15 sec\r\r
 855 Total CPU time to NGCBUILD completion:   11 sec\r\r
 856 \r\r
 857 Writing NGCBUILD log file "../implementation/system.blc"...\r\r
 858 \r\r
 859 NGCBUILD done.\r\r
 860 *********************************************\r
 861 Running Xilinx Implementation tools..\r
 862 *********************************************\r
 863 xflow -wd implementation -p xc5vfx70tff1136-1 -implement xflow.opt -ise ../__xps/ise/system.ise system.ngc\r
 864 Release 11.2 - Xflow L.46 (nt)\r\r
 865 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
 866 xflow.exe -wd implementation -p xc5vfx70tff1136-1 -implement xflow.opt -ise\r\r
 867 ../__xps/ise/system.ise system.ngc  \r\r
 868 PMSPEC -- Overriding Xilinx file\r\r
 869 <C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
 870 <c:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
 871 .... Copying flowfile c:/devtools/Xilinx/11.1/ISE/xilinx/data/fpga.flw into\r\r
 872 working directory\r\r
 873 C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/implementat\r\r
 874 ion \r\r
 875 \r\r
 876 Using Flow File:\r\r
 877 C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/implementat\r\r
 878 ion/fpga.flw \r\r
 879 Using Option File(s): \r\r
 880  C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/implementa\r\r
 881 tion/xflow.opt \r\r
 882 \r\r
 883 Creating Script File ... \r\r
 884 \r\r
 885 #----------------------------------------------#\r\r
 886 # Starting program ngdbuild\r\r
 887 # ngdbuild -ise ../__xps/ise/system.ise -p xc5vfx70tff1136-1 -nt timestamp -bm\r\r
 888 system.bmm\r\r
 889 "C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/implementa\r\r
 890 tion/system.ngc" -uc system.ucf system.ngd \r\r
 891 #----------------------------------------------#\r\r
 892 Release 11.2 - ngdbuild L.46 (nt)\r\r
 893 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
 894 PMSPEC -- Overriding Xilinx file\r\r
 895 <C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
 896 <c:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
 897 \r\r
 898 Command Line: ngdbuild -ise ../__xps/ise/system.ise -p xc5vfx70tff1136-1 -nt\r\r
 899 timestamp -bm system.bmm\r\r
 900 C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/implementat\r\r
 901 ion/system.ngc -uc system.ucf system.ngd\r\r
 902 \r\r
 903 Reading NGO file\r\r
 904 "C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/implementa\r\r
 905 tion/system.ngc" ...\r\r
 906 Gathering constraint information from source properties...\r\r
 907 Done.\r\r
 908 \r\r
 909 Applying constraints in "system.ucf" to the design...\r\r
 910 WARNING:NgdBuild:931 - The value of SIM_DEVICE on instance\r\r
 911    'clock_generator_0/clock_generator_0/Using_DCM0.DCM0_INST/DCM_INST/Using_DCM_\r\r
 912    ADV.DCM_ADV_INST' of type DCM_ADV has been changed from 'VIRTEX4' to\r\r
 913    'VIRTEX5' to correct post-ngdbuild and timing simulation for this primitive. \r\r
 914    In order for functional simulation to be correct, the value of SIM_DEVICE\r\r
 915    should be changed in this same manner in the source netlist or constraint\r\r
 916    file.\r\r
 917 Resolving constraint associations...\r\r
 918 Checking Constraint Associations...\r\r
 919 WARNING:ConstraintSystem:3 - Constraint <TIMESPEC "TS_MC_RD_DATA_SEL" = FROM\r\r
 920    "TNM_RD_DATA_SEL" TO "TNM_CLK0" "TS_clk_div_slow_0_clk_div_slow_0_DDR2_CLK_i"\r\r
 921    * 4;> [system.ucf(264)]: This constraint will be ignored because the relative\r\r
 922    clock constraint named 'TS_clk_div_slow_0_clk_div_slow_0_DDR2_CLK_i' was not\r\r
 923    found.\r\r
 924 \r\r
 925 INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification\r\r
 926    'TS_sys_clk_pin', was traced into PLL_ADV instance\r\r
 927    clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.\r\r
 928    The following new TNM groups and period specifications were generated at the\r\r
 929    PLL_ADV output(s): \r\r
 930    CLKOUT0: <TIMESPEC TS_clock_generator_0_clock_generator_0_PLL0_CLK_OUT_0_ =\r\r
 931    PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_0_" TS_sys_clk_pin *\r\r
 932    1.25 PHASE 2 ns HIGH 50%>\r\r
 933 \r\r
 934 INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification\r\r
 935    'TS_sys_clk_pin', was traced into PLL_ADV instance\r\r
 936    clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.\r\r
 937    The following new TNM groups and period specifications were generated at the\r\r
 938    PLL_ADV output(s): \r\r
 939    CLKOUT1: <TIMESPEC TS_clock_generator_0_clock_generator_0_PLL0_CLK_OUT_1_ =\r\r
 940    PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_1_" TS_sys_clk_pin *\r\r
 941    1.25 HIGH 50%>\r\r
 942 \r\r
 943 INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification\r\r
 944    'TS_sys_clk_pin', was traced into PLL_ADV instance\r\r
 945    clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.\r\r
 946    The following new TNM groups and period specifications were generated at the\r\r
 947    PLL_ADV output(s): \r\r
 948    CLKOUT2: <TIMESPEC TS_clock_generator_0_clock_generator_0_PLL0_CLK_OUT_2_ =\r\r
 949    PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_2_" TS_sys_clk_pin *\r\r
 950    1.25 HIGH 50%>\r\r
 951 \r\r
 952 INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification\r\r
 953    'TS_sys_clk_pin', was traced into PLL_ADV instance\r\r
 954    clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.\r\r
 955    The following new TNM groups and period specifications were generated at the\r\r
 956    PLL_ADV output(s): \r\r
 957    CLKOUT3: <TIMESPEC TS_clock_generator_0_clock_generator_0_PLL0_CLK_OUT_3_ =\r\r
 958    PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_3_" TS_sys_clk_pin *\r\r
 959    2 HIGH 50%>\r\r
 960 \r\r
 961 INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification\r\r
 962    'TS_sys_clk_pin', was traced into PLL_ADV instance\r\r
 963    clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.\r\r
 964    The following new TNM groups and period specifications were generated at the\r\r
 965    PLL_ADV output(s): \r\r
 966    CLKOUT4: <TIMESPEC TS_clock_generator_0_clock_generator_0_PLL0_CLK_OUT_4_ =\r\r
 967    PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_4_" TS_sys_clk_pin *\r\r
 968    0.625 HIGH 50%>\r\r
 969 \r\r
 970 Done...\r\r
 971 Checking Partitions ...\r\r
 972 \r\r
 973 Processing BMM file ...\r\r
 974 \r\r
 975 WARNING:NgdBuild:1212 - User specified non-default attribute value\r\r
 976    (8.0000000000000000) was detected for the CLKIN_PERIOD attribute on DCM\r\r
 977    "clock_generator_0/Using_DCM0.DCM0_INST/DCM_INST/Using_DCM_ADV.DCM_ADV_INST".\r\r
 978     This does not match the PERIOD constraint value (5 ns.).  The uncertainty\r\r
 979    calculation will use the non-default attribute value.  This could result in\r\r
 980    incorrect uncertainty calculated for DCM output clocks.\r\r
 981 Checking expanded design ...\r\r
 982 WARNING:NgdBuild:443 - SFF primitive\r\r
 983    'xps_bram_if_cntlr_1/xps_bram_if_cntlr_1/INCLUDE_BURST_SUPPORT.I_SLAVE_BURST_\r\r
 984    ATTACH/I_DBEAT_CONTROL/I_DBEAT_CNTR/STRUCTURAL_A_GEN.I_ADDSUB_GEN[4].FDRE_I'\r\r
 985    has unconnected output pin\r\r
 986 WARNING:NgdBuild:443 - SFF primitive\r\r
 987    'SRAM/SRAM/EMC_CTRL_I/MEM_STEER_I/SYNC_MEM_DQT.REG_DQT_GEN[2].DQT_REG' has\r\r
 988    unconnected output pin\r\r
 989 WARNING:NgdBuild:443 - SFF primitive\r\r
 990    'SRAM/SRAM/EMC_CTRL_I/MEM_STEER_I/GSYNC_MEM_RDACK_GEN.ADDR_ALIGN_PIPE_GEN[3].\r\r
 991    ALIGN_PIPE' has unconnected output pin\r\r
 992 WARNING:NgdBuild:443 - SFF primitive\r\r
 993    'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
 994    ENT/I_DECODER/GEN_CE_FOR_SHARED.GEN_BKEND_CE_REGISTERS[0].I_BKEND_WRCE_REG'\r\r
 995    has unconnected output pin\r\r
 996 WARNING:NgdBuild:443 - SFF primitive\r\r
 997    'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
 998    ENT/I_DECODER/GEN_CE_FOR_SHARED.GEN_BKEND_CE_REGISTERS[0].I_BKEND_RDCE_REG'\r\r
 999    has unconnected output pin\r\r
1000 WARNING:NgdBuild:443 - SFF primitive\r\r
1001    'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
1002    ENT/I_BURST_SUPPORT/RESPONSE_DBEAT_CNTR_I/STRUCTURAL_A_GEN.I_ADDSUB_GEN[7].FD\r\r
1003    RE_I' has unconnected output pin\r\r
1004 WARNING:NgdBuild:443 - SFF primitive\r\r
1005    'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
1006    ENT/I_BURST_SUPPORT/CONTROL_DBEAT_CNTR_I/STRUCTURAL_A_GEN.I_ADDSUB_GEN[7].FDR\r\r
1007    E_I' has unconnected output pin\r\r
1008 WARNING:NgdBuild:443 - SFF primitive\r\r
1009    'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
1010    ENT/I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[0].I_FDRSE_BE0to3\r\r
1011    ' has unconnected output pin\r\r
1012 WARNING:NgdBuild:443 - SFF primitive\r\r
1013    'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
1014    ENT/I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[1].I_FDRSE_BE0to3\r\r
1015    ' has unconnected output pin\r\r
1016 WARNING:NgdBuild:443 - SFF primitive\r\r
1017    'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
1018    ENT/I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[2].I_FDRSE_BE0to3\r\r
1019    ' has unconnected output pin\r\r
1020 WARNING:NgdBuild:443 - SFF primitive\r\r
1021    'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
1022    ENT/I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[3].I_FDRSE_BE0to3\r\r
1023    ' has unconnected output pin\r\r
1024 WARNING:NgdBuild:443 - SFF primitive\r\r
1025    'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
1026    ENT/I_BUS_ADDRESS_COUNTER/GEN_FOR_SHARED.GEN_S_H_SIZE_REG[0].I_SIZE_S_H_REG'\r\r
1027    has unconnected output pin\r\r
1028 WARNING:NgdBuild:443 - SFF primitive\r\r
1029    'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM\r\r
1030    ENT/I_STEER_ADDRESS_COUNTER/GEN_FOR_SHARED.GEN_S_H_SIZE_REG[0].I_SIZE_S_H_REG\r\r
1031    ' has unconnected output pin\r\r
1032 WARNING:NgdBuild:486 - Attribute "CLK_FEEDBACK" is not allowed on symbol\r\r
1033    "PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.pll_ad\r\r
1034    v_i" of type "PLL_ADV".  This attribute will be ignored.\r\r
1035 WARNING:NgdBuild:443 - SFF primitive\r\r
1036    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
1037    URSTXFER.I_STEER_ADDRESS_COUNTER/GEN_S_H_SIZE_REG[0].I_SIZE_S_H_REG' has\r\r
1038    unconnected output pin\r\r
1039 WARNING:NgdBuild:443 - SFF primitive\r\r
1040    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
1041    URSTXFER.I_BUS_ADDRESS_COUNTER/GEN_S_H_SIZE_REG[0].I_SIZE_S_H_REG' has\r\r
1042    unconnected output pin\r\r
1043 WARNING:NgdBuild:443 - SFF primitive\r\r
1044    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
1045    URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_DWIDTH_64_128.LDMUX_FDRSE\r\r
1046    _4to7[7].I_FDRSE_BE4to7' has unconnected output pin\r\r
1047 WARNING:NgdBuild:443 - SFF primitive\r\r
1048    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
1049    URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_DWIDTH_64_128.LDMUX_FDRSE\r\r
1050    _4to7[6].I_FDRSE_BE4to7' has unconnected output pin\r\r
1051 WARNING:NgdBuild:443 - SFF primitive\r\r
1052    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
1053    URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_DWIDTH_64_128.LDMUX_FDRSE\r\r
1054    _4to7[5].I_FDRSE_BE4to7' has unconnected output pin\r\r
1055 WARNING:NgdBuild:443 - SFF primitive\r\r
1056    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
1057    URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_DWIDTH_64_128.LDMUX_FDRSE\r\r
1058    _4to7[4].I_FDRSE_BE4to7' has unconnected output pin\r\r
1059 WARNING:NgdBuild:443 - SFF primitive\r\r
1060    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
1061    URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[3].I_FDRSE_B\r\r
1062    E0to3' has unconnected output pin\r\r
1063 WARNING:NgdBuild:443 - SFF primitive\r\r
1064    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
1065    URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[2].I_FDRSE_B\r\r
1066    E0to3' has unconnected output pin\r\r
1067 WARNING:NgdBuild:443 - SFF primitive\r\r
1068    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
1069    URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[1].I_FDRSE_B\r\r
1070    E0to3' has unconnected output pin\r\r
1071 WARNING:NgdBuild:443 - SFF primitive\r\r
1072    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/GEN_FAST_MODE_B\r\r
1073    URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[0].I_FDRSE_B\r\r
1074    E0to3' has unconnected output pin\r\r
1075 WARNING:NgdBuild:443 - SFF primitive\r\r
1076    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_S\r\r
1077    _H_ADDR_REG[6].I_ADDR_S_H_REG' has unconnected output pin\r\r
1078 WARNING:NgdBuild:443 - SFF primitive\r\r
1079    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_S\r\r
1080    _H_ADDR_REG[7].I_ADDR_S_H_REG' has unconnected output pin\r\r
1081 WARNING:NgdBuild:443 - SFF primitive\r\r
1082    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1083    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[0].I_BKend_CE_REG' has unconnected\r\r
1084    output pin\r\r
1085 WARNING:NgdBuild:443 - SFF primitive\r\r
1086    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1087    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[0].I_BKend_RDCE_REG' has unconnected\r\r
1088    output pin\r\r
1089 WARNING:NgdBuild:443 - SFF primitive\r\r
1090    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1091    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[0].I_BKend_WRCE_REG' has unconnected\r\r
1092    output pin\r\r
1093 WARNING:NgdBuild:443 - SFF primitive\r\r
1094    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1095    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[1].I_BKend_CE_REG' has unconnected\r\r
1096    output pin\r\r
1097 WARNING:NgdBuild:443 - SFF primitive\r\r
1098    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1099    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[1].I_BKend_RDCE_REG' has unconnected\r\r
1100    output pin\r\r
1101 WARNING:NgdBuild:443 - SFF primitive\r\r
1102    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1103    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[1].I_BKend_WRCE_REG' has unconnected\r\r
1104    output pin\r\r
1105 WARNING:NgdBuild:443 - SFF primitive\r\r
1106    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1107    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[2].I_BKend_CE_REG' has unconnected\r\r
1108    output pin\r\r
1109 WARNING:NgdBuild:443 - SFF primitive\r\r
1110    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1111    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[2].I_BKend_RDCE_REG' has unconnected\r\r
1112    output pin\r\r
1113 WARNING:NgdBuild:443 - SFF primitive\r\r
1114    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1115    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[2].I_BKend_WRCE_REG' has unconnected\r\r
1116    output pin\r\r
1117 WARNING:NgdBuild:443 - SFF primitive\r\r
1118    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1119    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[3].I_BKend_CE_REG' has unconnected\r\r
1120    output pin\r\r
1121 WARNING:NgdBuild:443 - SFF primitive\r\r
1122    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1123    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[3].I_BKend_RDCE_REG' has unconnected\r\r
1124    output pin\r\r
1125 WARNING:NgdBuild:443 - SFF primitive\r\r
1126    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1127    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[3].I_BKend_WRCE_REG' has unconnected\r\r
1128    output pin\r\r
1129 WARNING:NgdBuild:443 - SFF primitive\r\r
1130    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1131    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[4].I_BKend_CE_REG' has unconnected\r\r
1132    output pin\r\r
1133 WARNING:NgdBuild:443 - SFF primitive\r\r
1134    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1135    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[4].I_BKend_RDCE_REG' has unconnected\r\r
1136    output pin\r\r
1137 WARNING:NgdBuild:443 - SFF primitive\r\r
1138    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1139    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[4].I_BKend_WRCE_REG' has unconnected\r\r
1140    output pin\r\r
1141 WARNING:NgdBuild:443 - SFF primitive\r\r
1142    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1143    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[5].I_BKend_CE_REG' has unconnected\r\r
1144    output pin\r\r
1145 WARNING:NgdBuild:443 - SFF primitive\r\r
1146    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1147    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[5].I_BKend_RDCE_REG' has unconnected\r\r
1148    output pin\r\r
1149 WARNING:NgdBuild:443 - SFF primitive\r\r
1150    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1151    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[5].I_BKend_WRCE_REG' has unconnected\r\r
1152    output pin\r\r
1153 WARNING:NgdBuild:443 - SFF primitive\r\r
1154    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1155    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[6].I_BKend_CE_REG' has unconnected\r\r
1156    output pin\r\r
1157 WARNING:NgdBuild:443 - SFF primitive\r\r
1158    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1159    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[6].I_BKend_RDCE_REG' has unconnected\r\r
1160    output pin\r\r
1161 WARNING:NgdBuild:443 - SFF primitive\r\r
1162    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1163    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[6].I_BKend_WRCE_REG' has unconnected\r\r
1164    output pin\r\r
1165 WARNING:NgdBuild:443 - SFF primitive\r\r
1166    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1167    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[7].I_BKend_CE_REG' has unconnected\r\r
1168    output pin\r\r
1169 WARNING:NgdBuild:443 - SFF primitive\r\r
1170    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1171    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[7].I_BKend_RDCE_REG' has unconnected\r\r
1172    output pin\r\r
1173 WARNING:NgdBuild:443 - SFF primitive\r\r
1174    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1175    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[7].I_BKend_WRCE_REG' has unconnected\r\r
1176    output pin\r\r
1177 WARNING:NgdBuild:443 - SFF primitive\r\r
1178    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1179    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[8].I_BKend_CE_REG' has unconnected\r\r
1180    output pin\r\r
1181 WARNING:NgdBuild:443 - SFF primitive\r\r
1182    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1183    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[8].I_BKend_RDCE_REG' has unconnected\r\r
1184    output pin\r\r
1185 WARNING:NgdBuild:443 - SFF primitive\r\r
1186    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1187    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[8].I_BKend_WRCE_REG' has unconnected\r\r
1188    output pin\r\r
1189 WARNING:NgdBuild:443 - SFF primitive\r\r
1190    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1191    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[9].I_BKend_CE_REG' has unconnected\r\r
1192    output pin\r\r
1193 WARNING:NgdBuild:443 - SFF primitive\r\r
1194    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1195    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[9].I_BKend_RDCE_REG' has unconnected\r\r
1196    output pin\r\r
1197 WARNING:NgdBuild:443 - SFF primitive\r\r
1198    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1199    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[9].I_BKend_WRCE_REG' has unconnected\r\r
1200    output pin\r\r
1201 WARNING:NgdBuild:443 - SFF primitive\r\r
1202    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1203    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[10].I_BKend_CE_REG' has unconnected\r\r
1204    output pin\r\r
1205 WARNING:NgdBuild:443 - SFF primitive\r\r
1206    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1207    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[10].I_BKend_RDCE_REG' has\r\r
1208    unconnected output pin\r\r
1209 WARNING:NgdBuild:443 - SFF primitive\r\r
1210    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1211    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[10].I_BKend_WRCE_REG' has\r\r
1212    unconnected output pin\r\r
1213 WARNING:NgdBuild:443 - SFF primitive\r\r
1214    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1215    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[11].I_BKend_CE_REG' has unconnected\r\r
1216    output pin\r\r
1217 WARNING:NgdBuild:443 - SFF primitive\r\r
1218    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1219    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[11].I_BKend_RDCE_REG' has\r\r
1220    unconnected output pin\r\r
1221 WARNING:NgdBuild:443 - SFF primitive\r\r
1222    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1223    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[11].I_BKend_WRCE_REG' has\r\r
1224    unconnected output pin\r\r
1225 WARNING:NgdBuild:443 - SFF primitive\r\r
1226    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1227    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[12].I_BKend_CE_REG' has unconnected\r\r
1228    output pin\r\r
1229 WARNING:NgdBuild:443 - SFF primitive\r\r
1230    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1231    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[12].I_BKend_RDCE_REG' has\r\r
1232    unconnected output pin\r\r
1233 WARNING:NgdBuild:443 - SFF primitive\r\r
1234    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1235    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[12].I_BKend_WRCE_REG' has\r\r
1236    unconnected output pin\r\r
1237 WARNING:NgdBuild:443 - SFF primitive\r\r
1238    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1239    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[13].I_BKend_CE_REG' has unconnected\r\r
1240    output pin\r\r
1241 WARNING:NgdBuild:443 - SFF primitive\r\r
1242    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1243    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[13].I_BKend_RDCE_REG' has\r\r
1244    unconnected output pin\r\r
1245 WARNING:NgdBuild:443 - SFF primitive\r\r
1246    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1247    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[13].I_BKend_WRCE_REG' has\r\r
1248    unconnected output pin\r\r
1249 WARNING:NgdBuild:443 - SFF primitive\r\r
1250    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1251    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[14].I_BKend_CE_REG' has unconnected\r\r
1252    output pin\r\r
1253 WARNING:NgdBuild:443 - SFF primitive\r\r
1254    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1255    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[14].I_BKend_RDCE_REG' has\r\r
1256    unconnected output pin\r\r
1257 WARNING:NgdBuild:443 - SFF primitive\r\r
1258    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1259    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[14].I_BKend_WRCE_REG' has\r\r
1260    unconnected output pin\r\r
1261 WARNING:NgdBuild:443 - SFF primitive\r\r
1262    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1263    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[15].I_BKend_CE_REG' has unconnected\r\r
1264    output pin\r\r
1265 WARNING:NgdBuild:443 - SFF primitive\r\r
1266    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1267    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[15].I_BKend_RDCE_REG' has\r\r
1268    unconnected output pin\r\r
1269 WARNING:NgdBuild:443 - SFF primitive\r\r
1270    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1271    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[15].I_BKend_WRCE_REG' has\r\r
1272    unconnected output pin\r\r
1273 WARNING:NgdBuild:443 - SFF primitive\r\r
1274    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1275    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[16].I_BKend_CE_REG' has unconnected\r\r
1276    output pin\r\r
1277 WARNING:NgdBuild:443 - SFF primitive\r\r
1278    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1279    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[16].I_BKend_RDCE_REG' has\r\r
1280    unconnected output pin\r\r
1281 WARNING:NgdBuild:443 - SFF primitive\r\r
1282    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1283    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[16].I_BKend_WRCE_REG' has\r\r
1284    unconnected output pin\r\r
1285 WARNING:NgdBuild:443 - SFF primitive\r\r
1286    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1287    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[17].I_BKend_CE_REG' has unconnected\r\r
1288    output pin\r\r
1289 WARNING:NgdBuild:443 - SFF primitive\r\r
1290    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1291    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[17].I_BKend_RDCE_REG' has\r\r
1292    unconnected output pin\r\r
1293 WARNING:NgdBuild:443 - SFF primitive\r\r
1294    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1295    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[17].I_BKend_WRCE_REG' has\r\r
1296    unconnected output pin\r\r
1297 WARNING:NgdBuild:443 - SFF primitive\r\r
1298    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1299    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[18].I_BKend_CE_REG' has unconnected\r\r
1300    output pin\r\r
1301 WARNING:NgdBuild:443 - SFF primitive\r\r
1302    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1303    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[18].I_BKend_RDCE_REG' has\r\r
1304    unconnected output pin\r\r
1305 WARNING:NgdBuild:443 - SFF primitive\r\r
1306    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1307    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[18].I_BKend_WRCE_REG' has\r\r
1308    unconnected output pin\r\r
1309 WARNING:NgdBuild:443 - SFF primitive\r\r
1310    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1311    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[19].I_BKend_CE_REG' has unconnected\r\r
1312    output pin\r\r
1313 WARNING:NgdBuild:443 - SFF primitive\r\r
1314    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1315    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[19].I_BKend_RDCE_REG' has\r\r
1316    unconnected output pin\r\r
1317 WARNING:NgdBuild:443 - SFF primitive\r\r
1318    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1319    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[19].I_BKend_WRCE_REG' has\r\r
1320    unconnected output pin\r\r
1321 WARNING:NgdBuild:443 - SFF primitive\r\r
1322    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1323    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[20].I_BKend_CE_REG' has unconnected\r\r
1324    output pin\r\r
1325 WARNING:NgdBuild:443 - SFF primitive\r\r
1326    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1327    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[20].I_BKend_RDCE_REG' has\r\r
1328    unconnected output pin\r\r
1329 WARNING:NgdBuild:443 - SFF primitive\r\r
1330    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1331    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[20].I_BKend_WRCE_REG' has\r\r
1332    unconnected output pin\r\r
1333 WARNING:NgdBuild:443 - SFF primitive\r\r
1334    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1335    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[21].I_BKend_CE_REG' has unconnected\r\r
1336    output pin\r\r
1337 WARNING:NgdBuild:443 - SFF primitive\r\r
1338    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1339    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[21].I_BKend_RDCE_REG' has\r\r
1340    unconnected output pin\r\r
1341 WARNING:NgdBuild:443 - SFF primitive\r\r
1342    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1343    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[21].I_BKend_WRCE_REG' has\r\r
1344    unconnected output pin\r\r
1345 WARNING:NgdBuild:443 - SFF primitive\r\r
1346    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1347    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[22].I_BKend_CE_REG' has unconnected\r\r
1348    output pin\r\r
1349 WARNING:NgdBuild:443 - SFF primitive\r\r
1350    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1351    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[22].I_BKend_RDCE_REG' has\r\r
1352    unconnected output pin\r\r
1353 WARNING:NgdBuild:443 - SFF primitive\r\r
1354    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1355    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[22].I_BKend_WRCE_REG' has\r\r
1356    unconnected output pin\r\r
1357 WARNING:NgdBuild:443 - SFF primitive\r\r
1358    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1359    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[23].I_BKend_CE_REG' has unconnected\r\r
1360    output pin\r\r
1361 WARNING:NgdBuild:443 - SFF primitive\r\r
1362    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1363    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[23].I_BKend_RDCE_REG' has\r\r
1364    unconnected output pin\r\r
1365 WARNING:NgdBuild:443 - SFF primitive\r\r
1366    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1367    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[23].I_BKend_WRCE_REG' has\r\r
1368    unconnected output pin\r\r
1369 WARNING:NgdBuild:443 - SFF primitive\r\r
1370    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1371    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[24].I_BKend_CE_REG' has unconnected\r\r
1372    output pin\r\r
1373 WARNING:NgdBuild:443 - SFF primitive\r\r
1374    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1375    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[24].I_BKend_RDCE_REG' has\r\r
1376    unconnected output pin\r\r
1377 WARNING:NgdBuild:443 - SFF primitive\r\r
1378    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1379    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[24].I_BKend_WRCE_REG' has\r\r
1380    unconnected output pin\r\r
1381 WARNING:NgdBuild:443 - SFF primitive\r\r
1382    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1383    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[25].I_BKend_CE_REG' has unconnected\r\r
1384    output pin\r\r
1385 WARNING:NgdBuild:443 - SFF primitive\r\r
1386    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1387    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[25].I_BKend_RDCE_REG' has\r\r
1388    unconnected output pin\r\r
1389 WARNING:NgdBuild:443 - SFF primitive\r\r
1390    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1391    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[25].I_BKend_WRCE_REG' has\r\r
1392    unconnected output pin\r\r
1393 WARNING:NgdBuild:443 - SFF primitive\r\r
1394    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1395    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[26].I_BKend_CE_REG' has unconnected\r\r
1396    output pin\r\r
1397 WARNING:NgdBuild:443 - SFF primitive\r\r
1398    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1399    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[26].I_BKend_RDCE_REG' has\r\r
1400    unconnected output pin\r\r
1401 WARNING:NgdBuild:443 - SFF primitive\r\r
1402    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1403    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[26].I_BKend_WRCE_REG' has\r\r
1404    unconnected output pin\r\r
1405 WARNING:NgdBuild:443 - SFF primitive\r\r
1406    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1407    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[27].I_BKend_CE_REG' has unconnected\r\r
1408    output pin\r\r
1409 WARNING:NgdBuild:443 - SFF primitive\r\r
1410    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1411    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[27].I_BKend_RDCE_REG' has\r\r
1412    unconnected output pin\r\r
1413 WARNING:NgdBuild:443 - SFF primitive\r\r
1414    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1415    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[27].I_BKend_WRCE_REG' has\r\r
1416    unconnected output pin\r\r
1417 WARNING:NgdBuild:443 - SFF primitive\r\r
1418    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1419    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[28].I_BKend_CE_REG' has unconnected\r\r
1420    output pin\r\r
1421 WARNING:NgdBuild:443 - SFF primitive\r\r
1422    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1423    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[28].I_BKend_RDCE_REG' has\r\r
1424    unconnected output pin\r\r
1425 WARNING:NgdBuild:443 - SFF primitive\r\r
1426    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1427    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[28].I_BKend_WRCE_REG' has\r\r
1428    unconnected output pin\r\r
1429 WARNING:NgdBuild:443 - SFF primitive\r\r
1430    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1431    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[29].I_BKend_CE_REG' has unconnected\r\r
1432    output pin\r\r
1433 WARNING:NgdBuild:443 - SFF primitive\r\r
1434    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1435    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[29].I_BKend_RDCE_REG' has\r\r
1436    unconnected output pin\r\r
1437 WARNING:NgdBuild:443 - SFF primitive\r\r
1438    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1439    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[29].I_BKend_WRCE_REG' has\r\r
1440    unconnected output pin\r\r
1441 WARNING:NgdBuild:443 - SFF primitive\r\r
1442    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1443    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[30].I_BKend_CE_REG' has unconnected\r\r
1444    output pin\r\r
1445 WARNING:NgdBuild:443 - SFF primitive\r\r
1446    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1447    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[30].I_BKend_RDCE_REG' has\r\r
1448    unconnected output pin\r\r
1449 WARNING:NgdBuild:443 - SFF primitive\r\r
1450    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1451    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[30].I_BKend_WRCE_REG' has\r\r
1452    unconnected output pin\r\r
1453 WARNING:NgdBuild:443 - SFF primitive\r\r
1454    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1455    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[31].I_BKend_CE_REG' has unconnected\r\r
1456    output pin\r\r
1457 WARNING:NgdBuild:443 - SFF primitive\r\r
1458    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1459    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[31].I_BKend_RDCE_REG' has\r\r
1460    unconnected output pin\r\r
1461 WARNING:NgdBuild:443 - SFF primitive\r\r
1462    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1463    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[31].I_BKend_WRCE_REG' has\r\r
1464    unconnected output pin\r\r
1465 WARNING:NgdBuild:443 - SFF primitive\r\r
1466    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1467    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[32].I_BKend_CE_REG' has unconnected\r\r
1468    output pin\r\r
1469 WARNING:NgdBuild:443 - SFF primitive\r\r
1470    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1471    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[33].I_BKend_CE_REG' has unconnected\r\r
1472    output pin\r\r
1473 WARNING:NgdBuild:443 - SFF primitive\r\r
1474    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1475    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[34].I_BKend_CE_REG' has unconnected\r\r
1476    output pin\r\r
1477 WARNING:NgdBuild:443 - SFF primitive\r\r
1478    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1479    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[35].I_BKend_CE_REG' has unconnected\r\r
1480    output pin\r\r
1481 WARNING:NgdBuild:443 - SFF primitive\r\r
1482    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1483    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[36].I_BKend_CE_REG' has unconnected\r\r
1484    output pin\r\r
1485 WARNING:NgdBuild:443 - SFF primitive\r\r
1486    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1487    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[37].I_BKend_CE_REG' has unconnected\r\r
1488    output pin\r\r
1489 WARNING:NgdBuild:443 - SFF primitive\r\r
1490    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1491    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[38].I_BKend_CE_REG' has unconnected\r\r
1492    output pin\r\r
1493 WARNING:NgdBuild:443 - SFF primitive\r\r
1494    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1495    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[39].I_BKend_CE_REG' has unconnected\r\r
1496    output pin\r\r
1497 WARNING:NgdBuild:443 - SFF primitive\r\r
1498    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1499    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[40].I_BKend_CE_REG' has unconnected\r\r
1500    output pin\r\r
1501 WARNING:NgdBuild:443 - SFF primitive\r\r
1502    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1503    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[41].I_BKend_CE_REG' has unconnected\r\r
1504    output pin\r\r
1505 WARNING:NgdBuild:443 - SFF primitive\r\r
1506    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1507    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[42].I_BKend_CE_REG' has unconnected\r\r
1508    output pin\r\r
1509 WARNING:NgdBuild:443 - SFF primitive\r\r
1510    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1511    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[43].I_BKend_CE_REG' has unconnected\r\r
1512    output pin\r\r
1513 WARNING:NgdBuild:443 - SFF primitive\r\r
1514    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1515    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[44].I_BKend_CE_REG' has unconnected\r\r
1516    output pin\r\r
1517 WARNING:NgdBuild:443 - SFF primitive\r\r
1518    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1519    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[44].I_BKend_RDCE_REG' has\r\r
1520    unconnected output pin\r\r
1521 WARNING:NgdBuild:443 - SFF primitive\r\r
1522    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1523    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[44].I_BKend_WRCE_REG' has\r\r
1524    unconnected output pin\r\r
1525 WARNING:NgdBuild:443 - SFF primitive\r\r
1526    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1527    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[45].I_BKend_CE_REG' has unconnected\r\r
1528    output pin\r\r
1529 WARNING:NgdBuild:443 - SFF primitive\r\r
1530    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1531    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[45].I_BKend_RDCE_REG' has\r\r
1532    unconnected output pin\r\r
1533 WARNING:NgdBuild:443 - SFF primitive\r\r
1534    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1535    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[45].I_BKend_WRCE_REG' has\r\r
1536    unconnected output pin\r\r
1537 WARNING:NgdBuild:443 - SFF primitive\r\r
1538    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1539    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[46].I_BKend_CE_REG' has unconnected\r\r
1540    output pin\r\r
1541 WARNING:NgdBuild:443 - SFF primitive\r\r
1542    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1543    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[46].I_BKend_RDCE_REG' has\r\r
1544    unconnected output pin\r\r
1545 WARNING:NgdBuild:443 - SFF primitive\r\r
1546    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1547    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[46].I_BKend_WRCE_REG' has\r\r
1548    unconnected output pin\r\r
1549 WARNING:NgdBuild:443 - SFF primitive\r\r
1550    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1551    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[47].I_BKend_CE_REG' has unconnected\r\r
1552    output pin\r\r
1553 WARNING:NgdBuild:443 - SFF primitive\r\r
1554    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1555    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[47].I_BKend_RDCE_REG' has\r\r
1556    unconnected output pin\r\r
1557 WARNING:NgdBuild:443 - SFF primitive\r\r
1558    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1559    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[47].I_BKend_WRCE_REG' has\r\r
1560    unconnected output pin\r\r
1561 WARNING:NgdBuild:443 - SFF primitive\r\r
1562    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1563    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[48].I_BKend_CE_REG' has unconnected\r\r
1564    output pin\r\r
1565 WARNING:NgdBuild:443 - SFF primitive\r\r
1566    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1567    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[48].I_BKend_RDCE_REG' has\r\r
1568    unconnected output pin\r\r
1569 WARNING:NgdBuild:443 - SFF primitive\r\r
1570    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1571    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[48].I_BKend_WRCE_REG' has\r\r
1572    unconnected output pin\r\r
1573 WARNING:NgdBuild:443 - SFF primitive\r\r
1574    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1575    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[49].I_BKend_CE_REG' has unconnected\r\r
1576    output pin\r\r
1577 WARNING:NgdBuild:443 - SFF primitive\r\r
1578    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1579    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[49].I_BKend_RDCE_REG' has\r\r
1580    unconnected output pin\r\r
1581 WARNING:NgdBuild:443 - SFF primitive\r\r
1582    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1583    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[49].I_BKend_WRCE_REG' has\r\r
1584    unconnected output pin\r\r
1585 WARNING:NgdBuild:443 - SFF primitive\r\r
1586    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1587    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[50].I_BKend_CE_REG' has unconnected\r\r
1588    output pin\r\r
1589 WARNING:NgdBuild:443 - SFF primitive\r\r
1590    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1591    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[50].I_BKend_RDCE_REG' has\r\r
1592    unconnected output pin\r\r
1593 WARNING:NgdBuild:443 - SFF primitive\r\r
1594    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1595    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[50].I_BKend_WRCE_REG' has\r\r
1596    unconnected output pin\r\r
1597 WARNING:NgdBuild:443 - SFF primitive\r\r
1598    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1599    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[51].I_BKend_CE_REG' has unconnected\r\r
1600    output pin\r\r
1601 WARNING:NgdBuild:443 - SFF primitive\r\r
1602    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1603    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[51].I_BKend_RDCE_REG' has\r\r
1604    unconnected output pin\r\r
1605 WARNING:NgdBuild:443 - SFF primitive\r\r
1606    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1607    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[51].I_BKend_WRCE_REG' has\r\r
1608    unconnected output pin\r\r
1609 WARNING:NgdBuild:443 - SFF primitive\r\r
1610    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1611    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[52].I_BKend_CE_REG' has unconnected\r\r
1612    output pin\r\r
1613 WARNING:NgdBuild:443 - SFF primitive\r\r
1614    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1615    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[52].I_BKend_RDCE_REG' has\r\r
1616    unconnected output pin\r\r
1617 WARNING:NgdBuild:443 - SFF primitive\r\r
1618    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1619    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[52].I_BKend_WRCE_REG' has\r\r
1620    unconnected output pin\r\r
1621 WARNING:NgdBuild:443 - SFF primitive\r\r
1622    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1623    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[53].I_BKend_CE_REG' has unconnected\r\r
1624    output pin\r\r
1625 WARNING:NgdBuild:443 - SFF primitive\r\r
1626    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1627    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[53].I_BKend_RDCE_REG' has\r\r
1628    unconnected output pin\r\r
1629 WARNING:NgdBuild:443 - SFF primitive\r\r
1630    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1631    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[53].I_BKend_WRCE_REG' has\r\r
1632    unconnected output pin\r\r
1633 WARNING:NgdBuild:443 - SFF primitive\r\r
1634    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1635    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[54].I_BKend_CE_REG' has unconnected\r\r
1636    output pin\r\r
1637 WARNING:NgdBuild:443 - SFF primitive\r\r
1638    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1639    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[54].I_BKend_RDCE_REG' has\r\r
1640    unconnected output pin\r\r
1641 WARNING:NgdBuild:443 - SFF primitive\r\r
1642    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1643    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[54].I_BKend_WRCE_REG' has\r\r
1644    unconnected output pin\r\r
1645 WARNING:NgdBuild:443 - SFF primitive\r\r
1646    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1647    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[55].I_BKend_CE_REG' has unconnected\r\r
1648    output pin\r\r
1649 WARNING:NgdBuild:443 - SFF primitive\r\r
1650    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1651    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[55].I_BKend_RDCE_REG' has\r\r
1652    unconnected output pin\r\r
1653 WARNING:NgdBuild:443 - SFF primitive\r\r
1654    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1655    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[55].I_BKend_WRCE_REG' has\r\r
1656    unconnected output pin\r\r
1657 WARNING:NgdBuild:443 - SFF primitive\r\r
1658    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1659    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[56].I_BKend_CE_REG' has unconnected\r\r
1660    output pin\r\r
1661 WARNING:NgdBuild:443 - SFF primitive\r\r
1662    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1663    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[57].I_BKend_CE_REG' has unconnected\r\r
1664    output pin\r\r
1665 WARNING:NgdBuild:443 - SFF primitive\r\r
1666    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1667    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[58].I_BKend_CE_REG' has unconnected\r\r
1668    output pin\r\r
1669 WARNING:NgdBuild:443 - SFF primitive\r\r
1670    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1671    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[59].I_BKend_CE_REG' has unconnected\r\r
1672    output pin\r\r
1673 WARNING:NgdBuild:443 - SFF primitive\r\r
1674    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1675    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[60].I_BKend_CE_REG' has unconnected\r\r
1676    output pin\r\r
1677 WARNING:NgdBuild:443 - SFF primitive\r\r
1678    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1679    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[61].I_BKend_CE_REG' has unconnected\r\r
1680    output pin\r\r
1681 WARNING:NgdBuild:443 - SFF primitive\r\r
1682    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1683    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[61].I_BKend_RDCE_REG' has\r\r
1684    unconnected output pin\r\r
1685 WARNING:NgdBuild:443 - SFF primitive\r\r
1686    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1687    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[61].I_BKend_WRCE_REG' has\r\r
1688    unconnected output pin\r\r
1689 WARNING:NgdBuild:443 - SFF primitive\r\r
1690    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1691    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[62].I_BKend_CE_REG' has unconnected\r\r
1692    output pin\r\r
1693 WARNING:NgdBuild:443 - SFF primitive\r\r
1694    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1695    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[62].I_BKend_RDCE_REG' has\r\r
1696    unconnected output pin\r\r
1697 WARNING:NgdBuild:443 - SFF primitive\r\r
1698    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1699    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[62].I_BKend_WRCE_REG' has\r\r
1700    unconnected output pin\r\r
1701 WARNING:NgdBuild:443 - SFF primitive\r\r
1702    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1703    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[63].I_BKend_CE_REG' has unconnected\r\r
1704    output pin\r\r
1705 WARNING:NgdBuild:443 - SFF primitive\r\r
1706    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1707    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[63].I_BKend_RDCE_REG' has\r\r
1708    unconnected output pin\r\r
1709 WARNING:NgdBuild:443 - SFF primitive\r\r
1710    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1711    E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[63].I_BKend_WRCE_REG' has\r\r
1712    unconnected output pin\r\r
1713 WARNING:NgdBuild:443 - SFF primitive\r\r
1714    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1715    E_ASSIGNMENTS[1].GEN_USER_CE.GEN_ALL_CEs[64].I_BKend_CE_REG' has unconnected\r\r
1716    output pin\r\r
1717 WARNING:NgdBuild:443 - SFF primitive\r\r
1718    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1719    E_ASSIGNMENTS[1].GEN_USER_CE.GEN_ALL_CEs[64].I_BKend_RDCE_REG' has\r\r
1720    unconnected output pin\r\r
1721 WARNING:NgdBuild:443 - SFF primitive\r\r
1722    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1723    E_ASSIGNMENTS[1].GEN_USER_CE.GEN_ALL_CEs[64].I_BKend_WRCE_REG' has\r\r
1724    unconnected output pin\r\r
1725 WARNING:NgdBuild:443 - SFF primitive\r\r
1726    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1727    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[65].I_BKend_CE_REG' has\r\r
1728    unconnected output pin\r\r
1729 WARNING:NgdBuild:443 - SFF primitive\r\r
1730    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1731    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[66].I_BKend_CE_REG' has\r\r
1732    unconnected output pin\r\r
1733 WARNING:NgdBuild:443 - SFF primitive\r\r
1734    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1735    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[66].I_BKend_WRCE_REG' has\r\r
1736    unconnected output pin\r\r
1737 WARNING:NgdBuild:443 - SFF primitive\r\r
1738    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1739    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[67].I_BKend_CE_REG' has\r\r
1740    unconnected output pin\r\r
1741 WARNING:NgdBuild:443 - SFF primitive\r\r
1742    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1743    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[68].I_BKend_CE_REG' has\r\r
1744    unconnected output pin\r\r
1745 WARNING:NgdBuild:443 - SFF primitive\r\r
1746    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1747    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[68].I_BKend_RDCE_REG' has\r\r
1748    unconnected output pin\r\r
1749 WARNING:NgdBuild:443 - SFF primitive\r\r
1750    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1751    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[68].I_BKend_WRCE_REG' has\r\r
1752    unconnected output pin\r\r
1753 WARNING:NgdBuild:443 - SFF primitive\r\r
1754    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1755    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[69].I_BKend_CE_REG' has\r\r
1756    unconnected output pin\r\r
1757 WARNING:NgdBuild:443 - SFF primitive\r\r
1758    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1759    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[69].I_BKend_RDCE_REG' has\r\r
1760    unconnected output pin\r\r
1761 WARNING:NgdBuild:443 - SFF primitive\r\r
1762    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1763    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[69].I_BKend_WRCE_REG' has\r\r
1764    unconnected output pin\r\r
1765 WARNING:NgdBuild:443 - SFF primitive\r\r
1766    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1767    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[70].I_BKend_CE_REG' has\r\r
1768    unconnected output pin\r\r
1769 WARNING:NgdBuild:443 - SFF primitive\r\r
1770    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1771    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[70].I_BKend_RDCE_REG' has\r\r
1772    unconnected output pin\r\r
1773 WARNING:NgdBuild:443 - SFF primitive\r\r
1774    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1775    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[70].I_BKend_WRCE_REG' has\r\r
1776    unconnected output pin\r\r
1777 WARNING:NgdBuild:443 - SFF primitive\r\r
1778    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1779    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[71].I_BKend_CE_REG' has\r\r
1780    unconnected output pin\r\r
1781 WARNING:NgdBuild:443 - SFF primitive\r\r
1782    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1783    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[71].I_BKend_WRCE_REG' has\r\r
1784    unconnected output pin\r\r
1785 WARNING:NgdBuild:443 - SFF primitive\r\r
1786    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1787    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[72].I_BKend_CE_REG' has\r\r
1788    unconnected output pin\r\r
1789 WARNING:NgdBuild:443 - SFF primitive\r\r
1790    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1791    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[73].I_BKend_CE_REG' has\r\r
1792    unconnected output pin\r\r
1793 WARNING:NgdBuild:443 - SFF primitive\r\r
1794    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1795    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[74].I_BKend_CE_REG' has\r\r
1796    unconnected output pin\r\r
1797 WARNING:NgdBuild:443 - SFF primitive\r\r
1798    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1799    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[74].I_BKend_RDCE_REG' has\r\r
1800    unconnected output pin\r\r
1801 WARNING:NgdBuild:443 - SFF primitive\r\r
1802    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1803    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[74].I_BKend_WRCE_REG' has\r\r
1804    unconnected output pin\r\r
1805 WARNING:NgdBuild:443 - SFF primitive\r\r
1806    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1807    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[75].I_BKend_CE_REG' has\r\r
1808    unconnected output pin\r\r
1809 WARNING:NgdBuild:443 - SFF primitive\r\r
1810    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1811    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[76].I_BKend_CE_REG' has\r\r
1812    unconnected output pin\r\r
1813 WARNING:NgdBuild:443 - SFF primitive\r\r
1814    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1815    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[76].I_BKend_RDCE_REG' has\r\r
1816    unconnected output pin\r\r
1817 WARNING:NgdBuild:443 - SFF primitive\r\r
1818    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1819    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[76].I_BKend_WRCE_REG' has\r\r
1820    unconnected output pin\r\r
1821 WARNING:NgdBuild:443 - SFF primitive\r\r
1822    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1823    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[77].I_BKend_CE_REG' has\r\r
1824    unconnected output pin\r\r
1825 WARNING:NgdBuild:443 - SFF primitive\r\r
1826    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1827    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[77].I_BKend_RDCE_REG' has\r\r
1828    unconnected output pin\r\r
1829 WARNING:NgdBuild:443 - SFF primitive\r\r
1830    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1831    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[77].I_BKend_WRCE_REG' has\r\r
1832    unconnected output pin\r\r
1833 WARNING:NgdBuild:443 - SFF primitive\r\r
1834    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1835    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[78].I_BKend_CE_REG' has\r\r
1836    unconnected output pin\r\r
1837 WARNING:NgdBuild:443 - SFF primitive\r\r
1838    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1839    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[78].I_BKend_RDCE_REG' has\r\r
1840    unconnected output pin\r\r
1841 WARNING:NgdBuild:443 - SFF primitive\r\r
1842    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1843    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[78].I_BKend_WRCE_REG' has\r\r
1844    unconnected output pin\r\r
1845 WARNING:NgdBuild:443 - SFF primitive\r\r
1846    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1847    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[79].I_BKend_CE_REG' has\r\r
1848    unconnected output pin\r\r
1849 WARNING:NgdBuild:443 - SFF primitive\r\r
1850    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1851    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[79].I_BKend_RDCE_REG' has\r\r
1852    unconnected output pin\r\r
1853 WARNING:NgdBuild:443 - SFF primitive\r\r
1854    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1855    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[79].I_BKend_WRCE_REG' has\r\r
1856    unconnected output pin\r\r
1857 WARNING:NgdBuild:443 - SFF primitive\r\r
1858    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1859    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[80].I_BKend_CE_REG' has\r\r
1860    unconnected output pin\r\r
1861 WARNING:NgdBuild:443 - SFF primitive\r\r
1862    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1863    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[80].I_BKend_RDCE_REG' has\r\r
1864    unconnected output pin\r\r
1865 WARNING:NgdBuild:443 - SFF primitive\r\r
1866    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1867    E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[80].I_BKend_WRCE_REG' has\r\r
1868    unconnected output pin\r\r
1869 WARNING:NgdBuild:443 - SFF primitive\r\r
1870    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1871    E_ASSIGNMENTS[3].GEN_RESET_CE.I_BKend_CE_REG' has unconnected output pin\r\r
1872 WARNING:NgdBuild:443 - SFF primitive\r\r
1873    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1874    E_ASSIGNMENTS[3].GEN_RESET_CE.I_BKend_RDCE_REG' has unconnected output pin\r\r
1875 WARNING:NgdBuild:443 - SFF primitive\r\r
1876    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1877    E_ASSIGNMENTS[4].GEN_USER_CE.GEN_ALL_CEs[82].I_BKend_CE_REG' has unconnected\r\r
1878    output pin\r\r
1879 WARNING:NgdBuild:443 - SFF primitive\r\r
1880    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1881    E_ASSIGNMENTS[4].GEN_USER_CE.GEN_ALL_CEs[82].I_BKend_RDCE_REG' has\r\r
1882    unconnected output pin\r\r
1883 WARNING:NgdBuild:443 - SFF primitive\r\r
1884    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1885    E_ASSIGNMENTS[4].GEN_USER_CE.GEN_ALL_CEs[82].I_BKend_WRCE_REG' has\r\r
1886    unconnected output pin\r\r
1887 WARNING:NgdBuild:443 - SFF primitive\r\r
1888    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1889    E_ASSIGNMENTS[5].GEN_USER_CE.GEN_ALL_CEs[83].I_BKend_CE_REG' has unconnected\r\r
1890    output pin\r\r
1891 WARNING:NgdBuild:443 - SFF primitive\r\r
1892    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1893    E_ASSIGNMENTS[5].GEN_USER_CE.GEN_ALL_CEs[83].I_BKend_RDCE_REG' has\r\r
1894    unconnected output pin\r\r
1895 WARNING:NgdBuild:443 - SFF primitive\r\r
1896    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C\r\r
1897    E_ASSIGNMENTS[5].GEN_USER_CE.GEN_ALL_CEs[83].I_BKend_WRCE_REG' has\r\r
1898    unconnected output pin\r\r
1899 WARNING:NgdBuild:443 - SFF primitive\r\r
1900    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/I_CS_\r\r
1901    SIZE2_REG0' has unconnected output pin\r\r
1902 WARNING:NgdBuild:443 - SFF primitive\r\r
1903    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/I_CS_\r\r
1904    SIZE2_REG1' has unconnected output pin\r\r
1905 WARNING:NgdBuild:443 - SFF primitive\r\r
1906    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/I_CS_\r\r
1907    SIZE2_REG2' has unconnected output pin\r\r
1908 WARNING:NgdBuild:443 - SFF primitive\r\r
1909    'PCIe_Bridge/PCIe_Bridge/comp_plbv46_master/I_RD_CONTROL/I_RD_ABORT_REG' has\r\r
1910    unconnected output pin\r\r
1911 WARNING:NgdBuild:443 - SFF primitive\r\r
1912    'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/COLLISION_SYNC' has unconnected\r\r
1913    output pin\r\r
1914 WARNING:NgdBuild:440 - FF primitive\r\r
1915    'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU10'\r\r
1916    has unconnected output pin\r\r
1917 WARNING:NgdBuild:440 - FF primitive\r\r
1918    'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU15'\r\r
1919    has unconnected output pin\r\r
1920 WARNING:NgdBuild:440 - FF primitive\r\r
1921    'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU20'\r\r
1922    has unconnected output pin\r\r
1923 WARNING:NgdBuild:440 - FF primitive\r\r
1924    'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU25'\r\r
1925    has unconnected output pin\r\r
1926 WARNING:NgdBuild:440 - FF primitive\r\r
1927    'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU30'\r\r
1928    has unconnected output pin\r\r
1929 WARNING:NgdBuild:440 - FF primitive\r\r
1930    'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU35'\r\r
1931    has unconnected output pin\r\r
1932 WARNING:NgdBuild:440 - FF primitive\r\r
1933    'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU130'\r\r
1934    has unconnected output pin\r\r
1935 WARNING:NgdBuild:440 - FF primitive\r\r
1936    'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU237'\r\r
1937    has unconnected output pin\r\r
1938 WARNING:NgdBuild:440 - FF primitive\r\r
1939    'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU10'\r\r
1940    has unconnected output pin\r\r
1941 WARNING:NgdBuild:440 - FF primitive\r\r
1942    'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU15'\r\r
1943    has unconnected output pin\r\r
1944 WARNING:NgdBuild:440 - FF primitive\r\r
1945    'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU20'\r\r
1946    has unconnected output pin\r\r
1947 WARNING:NgdBuild:440 - FF primitive\r\r
1948    'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU25'\r\r
1949    has unconnected output pin\r\r
1950 WARNING:NgdBuild:440 - FF primitive\r\r
1951    'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU30'\r\r
1952    has unconnected output pin\r\r
1953 WARNING:NgdBuild:440 - FF primitive\r\r
1954    'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU35'\r\r
1955    has unconnected output pin\r\r
1956 WARNING:NgdBuild:440 - FF primitive\r\r
1957    'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU130'\r\r
1958    has unconnected output pin\r\r
1959 WARNING:NgdBuild:440 - FF primitive\r\r
1960    'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU237'\r\r
1961    has unconnected output pin\r\r
1962 WARNING:NgdBuild:440 - FF primitive\r\r
1963    'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib\r\r
1964    /gen_rden[1].u_calib_rden_r' has unconnected output pin\r\r
1965 WARNING:NgdBuild:440 - FF primitive\r\r
1966    'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib\r\r
1967    /gen_rden[2].u_calib_rden_r' has unconnected output pin\r\r
1968 WARNING:NgdBuild:440 - FF primitive\r\r
1969    'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib\r\r
1970    /gen_rden[3].u_calib_rden_r' has unconnected output pin\r\r
1971 WARNING:NgdBuild:440 - FF primitive\r\r
1972    'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib\r\r
1973    /gen_rden[4].u_calib_rden_r' has unconnected output pin\r\r
1974 WARNING:NgdBuild:440 - FF primitive\r\r
1975    'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib\r\r
1976    /gen_rden[5].u_calib_rden_r' has unconnected output pin\r\r
1977 WARNING:NgdBuild:440 - FF primitive\r\r
1978    'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib\r\r
1979    /gen_rden[6].u_calib_rden_r' has unconnected output pin\r\r
1980 WARNING:NgdBuild:440 - FF primitive\r\r
1981    'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib\r\r
1982    /gen_rden[7].u_calib_rden_r' has unconnected output pin\r\r
1983 WARNING:NgdBuild:486 - Attribute "CLK_FEEDBACK" is not allowed on symbol\r\r
1984    "clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst"\r\r
1985    of type "PLL_ADV".  This attribute will be ignored.\r\r
1986 WARNING:NgdBuild:452 - logical net 'N194' has no driver\r\r
1987 WARNING:NgdBuild:452 - logical net 'N195' has no driver\r\r
1988 WARNING:NgdBuild:452 - logical net 'N196' has no driver\r\r
1989 WARNING:NgdBuild:452 - logical net 'N197' has no driver\r\r
1990 WARNING:NgdBuild:452 - logical net 'N198' has no driver\r\r
1991 WARNING:NgdBuild:452 - logical net 'N199' has no driver\r\r
1992 WARNING:NgdBuild:452 - logical net 'N200' has no driver\r\r
1993 WARNING:NgdBuild:452 - logical net 'N201' has no driver\r\r
1994 WARNING:NgdBuild:452 - logical net 'N202' has no driver\r\r
1995 WARNING:NgdBuild:452 - logical net 'N203' has no driver\r\r
1996 WARNING:NgdBuild:452 - logical net 'N204' has no driver\r\r
1997 WARNING:NgdBuild:452 - logical net 'N205' has no driver\r\r
1998 WARNING:NgdBuild:452 - logical net 'N206' has no driver\r\r
1999 WARNING:NgdBuild:452 - logical net 'N207' has no driver\r\r
2000 WARNING:NgdBuild:452 - logical net 'N208' has no driver\r\r
2001 WARNING:NgdBuild:452 - logical net 'N209' has no driver\r\r
2002 WARNING:NgdBuild:452 - logical net 'N210' has no driver\r\r
2003 WARNING:NgdBuild:452 - logical net 'N211' has no driver\r\r
2004 WARNING:NgdBuild:452 - logical net 'N212' has no driver\r\r
2005 WARNING:NgdBuild:452 - logical net 'N213' has no driver\r\r
2006 WARNING:NgdBuild:452 - logical net 'N214' has no driver\r\r
2007 WARNING:NgdBuild:452 - logical net 'N215' has no driver\r\r
2008 WARNING:NgdBuild:452 - logical net 'N216' has no driver\r\r
2009 WARNING:NgdBuild:452 - logical net 'N217' has no driver\r\r
2010 WARNING:NgdBuild:452 - logical net 'N218' has no driver\r\r
2011 WARNING:NgdBuild:452 - logical net 'N219' has no driver\r\r
2012 WARNING:NgdBuild:452 - logical net 'N220' has no driver\r\r
2013 WARNING:NgdBuild:452 - logical net 'N221' has no driver\r\r
2014 WARNING:NgdBuild:452 - logical net 'N222' has no driver\r\r
2015 WARNING:NgdBuild:452 - logical net 'N223' has no driver\r\r
2016 WARNING:NgdBuild:452 - logical net 'N224' has no driver\r\r
2017 WARNING:NgdBuild:452 - logical net 'N225' has no driver\r\r
2018 WARNING:NgdBuild:452 - logical net 'N226' has no driver\r\r
2019 WARNING:NgdBuild:452 - logical net 'N227' has no driver\r\r
2020 WARNING:NgdBuild:452 - logical net 'N228' has no driver\r\r
2021 WARNING:NgdBuild:452 - logical net 'N229' has no driver\r\r
2022 WARNING:NgdBuild:452 - logical net 'N230' has no driver\r\r
2023 WARNING:NgdBuild:452 - logical net 'N231' has no driver\r\r
2024 WARNING:NgdBuild:452 - logical net 'N232' has no driver\r\r
2025 WARNING:NgdBuild:452 - logical net 'N233' has no driver\r\r
2026 WARNING:NgdBuild:452 - logical net 'N234' has no driver\r\r
2027 WARNING:NgdBuild:452 - logical net 'N235' has no driver\r\r
2028 WARNING:NgdBuild:452 - logical net 'N236' has no driver\r\r
2029 WARNING:NgdBuild:452 - logical net 'N237' has no driver\r\r
2030 WARNING:NgdBuild:452 - logical net 'N238' has no driver\r\r
2031 WARNING:NgdBuild:452 - logical net 'N239' has no driver\r\r
2032 WARNING:NgdBuild:452 - logical net 'N240' has no driver\r\r
2033 WARNING:NgdBuild:452 - logical net 'N241' has no driver\r\r
2034 WARNING:NgdBuild:452 - logical net 'N242' has no driver\r\r
2035 WARNING:NgdBuild:452 - logical net 'N243' has no driver\r\r
2036 WARNING:NgdBuild:452 - logical net 'N244' has no driver\r\r
2037 WARNING:NgdBuild:452 - logical net 'N245' has no driver\r\r
2038 WARNING:NgdBuild:452 - logical net 'N246' has no driver\r\r
2039 WARNING:NgdBuild:452 - logical net 'N247' has no driver\r\r
2040 WARNING:NgdBuild:452 - logical net 'N248' has no driver\r\r
2041 WARNING:NgdBuild:452 - logical net 'N249' has no driver\r\r
2042 WARNING:NgdBuild:452 - logical net 'N250' has no driver\r\r
2043 WARNING:NgdBuild:452 - logical net 'N251' has no driver\r\r
2044 WARNING:NgdBuild:452 - logical net 'N252' has no driver\r\r
2045 WARNING:NgdBuild:452 - logical net 'N253' has no driver\r\r
2046 WARNING:NgdBuild:452 - logical net 'N254' has no driver\r\r
2047 WARNING:NgdBuild:452 - logical net 'N255' has no driver\r\r
2048 WARNING:NgdBuild:452 - logical net 'N256' has no driver\r\r
2049 WARNING:NgdBuild:452 - logical net 'N257' has no driver\r\r
2050 WARNING:NgdBuild:452 - logical net 'N266' has no driver\r\r
2051 WARNING:NgdBuild:452 - logical net 'N267' has no driver\r\r
2052 WARNING:NgdBuild:452 - logical net 'N268' has no driver\r\r
2053 WARNING:NgdBuild:452 - logical net 'N269' has no driver\r\r
2054 WARNING:NgdBuild:452 - logical net 'N270' has no driver\r\r
2055 WARNING:NgdBuild:452 - logical net 'N271' has no driver\r\r
2056 WARNING:NgdBuild:452 - logical net 'N272' has no driver\r\r
2057 WARNING:NgdBuild:452 - logical net 'N273' has no driver\r\r
2058 WARNING:NgdBuild:452 - logical net 'N306' has no driver\r\r
2059 WARNING:NgdBuild:452 - logical net 'N307' has no driver\r\r
2060 WARNING:NgdBuild:452 - logical net 'N308' has no driver\r\r
2061 WARNING:NgdBuild:452 - logical net 'N309' has no driver\r\r
2062 WARNING:NgdBuild:452 - logical net 'N310' has no driver\r\r
2063 WARNING:NgdBuild:452 - logical net 'N311' has no driver\r\r
2064 WARNING:NgdBuild:452 - logical net 'N312' has no driver\r\r
2065 WARNING:NgdBuild:452 - logical net 'N313' has no driver\r\r
2066 WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_terrfwd_n'\r\r
2067    has no driver\r\r
2068 WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_rerrfwd_n'\r\r
2069    has no driver\r\r
2070 WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_tsrc_dsc_n'\r\r
2071    has no driver\r\r
2072 WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_tbuf_av<3>'\r\r
2073    has no driver\r\r
2074 WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_trem_n<4>'\r\r
2075    has no driver\r\r
2076 \r\r
2077 Partition Implementation Status\r\r
2078 -------------------------------\r\r
2079 \r\r
2080   No Partitions were found in this design.\r\r
2081 \r\r
2082 -------------------------------\r\r
2083 \r\r
2084 NGDBUILD Design Results Summary:\r\r
2085   Number of errors:     0\r\r
2086   Number of warnings: 348\r\r
2087 \r\r
2088 Writing NGD file "system.ngd" ...\r\r
2089 Total REAL time to NGDBUILD completion: 2 min  3 sec\r\r
2090 Total CPU time to NGDBUILD completion:  1 min  21 sec\r\r
2091 \r\r
2092 Writing NGDBUILD log file "system.bld"...\r\r
2093 \r\r
2094 NGDBUILD done.\r\r
2095 \r\r
2096 \r\r
2097 \r\r
2098 #----------------------------------------------#\r\r
2099 # Starting program map\r\r
2100 # map -ise ../__xps/ise/system.ise -o system_map.ncd -w -pr b -ol high -timing\r\r
2101 system.ngd system.pcf \r\r
2102 #----------------------------------------------#\r\r
2103 Release 11.2 - Map L.46 (nt)\r\r
2104 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
2105 PMSPEC -- Overriding Xilinx file\r\r
2106 <C:/devtools/Xilinx/11.1/EDK/data/Xdh_PrimTypeLib.xda> with local file\r\r
2107 <c:/devtools/Xilinx/11.1/ISE/data/Xdh_PrimTypeLib.xda>\r\r
2108 Using target part "5vfx70tff1136-1".\r\r
2109 WARNING:LIT:243 - Logical network N194 has no load.\r\r
2110 WARNING:LIT:395 - The above warning message is repeated 1028 more times for the\r\r
2111    following (max. 5 shown):\r\r
2112    N195,\r\r
2113    N196,\r\r
2114    N197,\r\r
2115    N198,\r\r
2116    N199\r\r
2117    To see the details of these warning messages, please use the -detail switch.\r\r
2118 Mapping design into LUTs...\r\r
2119 WARNING:MapLib:701 - Signal fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin\r\r
2120    connected to top level port fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin has\r\r
2121    been removed.\r\r
2122 WARNING:MapLib:701 - Signal fpga_0_Ethernet_MAC_PHY_col_pin connected to top\r\r
2123    level port fpga_0_Ethernet_MAC_PHY_col_pin has been removed.\r\r
2124 WARNING:MapLib:41 - All members of TNM group "ppc440_0_PPCS0PLBMBUSY" have been\r\r
2125    optimized out of the design.\r\r
2126 Writing file system_map.ngm...\r\r
2127 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2128    xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0\r\r
2129    of frag REGCLKAU connected to power/ground net\r\r
2130    xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0_REGCLKAU_tiesig\r\r
2131 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2132    xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0\r\r
2133    of frag REGCLKAL connected to power/ground net\r\r
2134    xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0_REGCLKAL_tiesig\r\r
2135 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2136    xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1\r\r
2137    of frag REGCLKAU connected to power/ground net\r\r
2138    xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1_REGCLKAU_tiesig\r\r
2139 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2140    xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1\r\r
2141    of frag REGCLKAL connected to power/ground net\r\r
2142    xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1_REGCLKAL_tiesig\r\r
2143 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2144    PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
2145    er_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst\r\r
2146    of frag REGCLKAU connected to power/ground net\r\r
2147    PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
2148    er_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst_REGCLKAU_tiesig\r\r
2149 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2150    PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
2151    er_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst\r\r
2152    of frag REGCLKAL connected to power/ground net\r\r
2153    PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
2154    er_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst_REGCLKAL_tiesig\r\r
2155 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2156    PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
2157    er_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst\r\r
2158    of frag REGCLKAU connected to power/ground net\r\r
2159    PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
2160    er_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst_REGCLKAU_tiesig\r\r
2161 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2162    PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
2163    er_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst\r\r
2164    of frag REGCLKAL connected to power/ground net\r\r
2165    PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp\r\r
2166    er_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst_REGCLKAL_tiesig\r\r
2167 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2168    PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/r\r\r
2169    x_bridge/fifo_inst/oq_fifo/Mram_regBank\r\r
2170    of frag RDRCLKU connected to power/ground net\r\r
2171    PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/r\r\r
2172    x_bridge/fifo_inst/oq_fifo/Mram_regBank_RDRCLKU_tiesig\r\r
2173 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2174    PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/r\r\r
2175    x_bridge/fifo_inst/oq_fifo/Mram_regBank\r\r
2176    of frag RDRCLKL connected to power/ground net\r\r
2177    PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/r\r\r
2178    x_bridge/fifo_inst/oq_fifo/Mram_regBank_RDRCLKL_tiesig\r\r
2179 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2180    PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0\r\r
2181    /blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.\r\r
2182    noeccerr.SDP\r\r
2183    of frag RDRCLKU connected to power/ground net\r\r
2184    PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0\r\r
2185    /blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.\r\r
2186    noeccerr.SDP_RDRCLKU_tiesig\r\r
2187 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2188    PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0\r\r
2189    /blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.\r\r
2190    noeccerr.SDP\r\r
2191    of frag RDRCLKL connected to power/ground net\r\r
2192    PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0\r\r
2193    /blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.\r\r
2194    noeccerr.SDP_RDRCLKL_tiesig\r\r
2195 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2196    PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m\r\r
2197    em/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.\r\r
2198    ram/SDP.WIDE_PRIM36.noeccerr.SDP\r\r
2199    of frag RDRCLKU connected to power/ground net\r\r
2200    PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m\r\r
2201    em/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.\r\r
2202    ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig\r\r
2203 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2204    PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m\r\r
2205    em/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.\r\r
2206    ram/SDP.WIDE_PRIM36.noeccerr.SDP\r\r
2207    of frag RDRCLKL connected to power/ground net\r\r
2208    PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m\r\r
2209    em/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.\r\r
2210    ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig\r\r
2211 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2212    PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM\r\r
2213    P_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noi\r\r
2214    nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP\r\r
2215    of frag RDRCLKU connected to power/ground net\r\r
2216    PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM\r\r
2217    P_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noi\r\r
2218    nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig\r\r
2219 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2220    PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM\r\r
2221    P_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noi\r\r
2222    nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP\r\r
2223    of frag RDRCLKL connected to power/ground net\r\r
2224    PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM\r\r
2225    P_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noi\r\r
2226    nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig\r\r
2227 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2228    PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2\r\r
2229    /U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM\r\r
2230    36.noeccerr.SDP\r\r
2231    of frag RDRCLKU connected to power/ground net\r\r
2232    PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2\r\r
2233    /U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM\r\r
2234    36.noeccerr.SDP_RDRCLKU_tiesig\r\r
2235 WARNING:Pack:2874 - Trimming timing constraints from pin\r\r
2236    PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2\r\r
2237    /U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM\r\r
2238    36.noeccerr.SDP\r\r
2239    of frag RDRCLKL connected to power/ground net\r\r
2240    PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2\r\r
2241    /U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM\r\r
2242    36.noeccerr.SDP_RDRCLKL_tiesig\r\r
2243 Running directed packing...\r\r
2244 Running delay-based LUT packing...\r\r
2245 Updating timing models...\r\r
2246 WARNING:Timing:3223 - Timing constraint TS_MC_RDEN_SEL_MUX = MAXDELAY FROM\r\r
2247    TIMEGRP "TNM_RDEN_SEL_MUX" TO TIMEGRP "TNM_CLK0" TS_MC_CLK * 4 ignored during\r\r
2248    timing analysis.\r\r
2249 INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report\r\r
2250    (.mrp).\r\r
2251 Running timing-driven placement...\r\r
2252 Total REAL time at the beginning of Placer: 2 mins 41 secs \r\r
2253 Total CPU  time at the beginning of Placer: 2 mins 8 secs \r\r
2254 \r\r
2255 Phase 1.1  Initial Placement Analysis\r\r
2256 Phase 1.1  Initial Placement Analysis (Checksum:9d0c7baf) REAL time: 3 mins 15 secs \r\r
2257 \r\r
2258 Phase 2.7  Design Feasibility Check\r\r
2259 WARNING:Place:838 - An IO Bus with more than one IO standard is found.\r\r
2260    Components associated with this bus are as follows: \r\r
2261          Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<7>   IOSTANDARD = LVCMOS25\r\r
2262          Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<6>   IOSTANDARD = LVCMOS25\r\r
2263          Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<5>   IOSTANDARD = LVCMOS25\r\r
2264          Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<4>   IOSTANDARD = LVCMOS18\r\r
2265          Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<3>   IOSTANDARD = LVCMOS25\r\r
2266          Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<2>   IOSTANDARD = LVCMOS18\r\r
2267          Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<1>   IOSTANDARD = LVCMOS18\r\r
2268          Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<0>   IOSTANDARD = LVCMOS18\r\r
2269 \r\r
2270 \r\r
2271 WARNING:Place:838 - An IO Bus with more than one IO standard is found.\r\r
2272    Components associated with this bus are as follows: \r\r
2273          Comp: fpga_0_SRAM_Mem_DQ_pin<31>   IOSTANDARD = LVDCI_33\r\r
2274          Comp: fpga_0_SRAM_Mem_DQ_pin<30>   IOSTANDARD = LVDCI_33\r\r
2275          Comp: fpga_0_SRAM_Mem_DQ_pin<29>   IOSTANDARD = LVDCI_33\r\r
2276          Comp: fpga_0_SRAM_Mem_DQ_pin<28>   IOSTANDARD = LVDCI_33\r\r
2277          Comp: fpga_0_SRAM_Mem_DQ_pin<27>   IOSTANDARD = LVDCI_33\r\r
2278          Comp: fpga_0_SRAM_Mem_DQ_pin<26>   IOSTANDARD = LVDCI_33\r\r
2279          Comp: fpga_0_SRAM_Mem_DQ_pin<25>   IOSTANDARD = LVDCI_33\r\r
2280          Comp: fpga_0_SRAM_Mem_DQ_pin<24>   IOSTANDARD = LVDCI_33\r\r
2281          Comp: fpga_0_SRAM_Mem_DQ_pin<23>   IOSTANDARD = LVDCI_33\r\r
2282          Comp: fpga_0_SRAM_Mem_DQ_pin<22>   IOSTANDARD = LVDCI_33\r\r
2283          Comp: fpga_0_SRAM_Mem_DQ_pin<21>   IOSTANDARD = LVDCI_33\r\r
2284          Comp: fpga_0_SRAM_Mem_DQ_pin<20>   IOSTANDARD = LVDCI_33\r\r
2285          Comp: fpga_0_SRAM_Mem_DQ_pin<19>   IOSTANDARD = LVDCI_33\r\r
2286          Comp: fpga_0_SRAM_Mem_DQ_pin<18>   IOSTANDARD = LVDCI_33\r\r
2287          Comp: fpga_0_SRAM_Mem_DQ_pin<17>   IOSTANDARD = LVDCI_33\r\r
2288          Comp: fpga_0_SRAM_Mem_DQ_pin<16>   IOSTANDARD = LVDCI_33\r\r
2289          Comp: fpga_0_SRAM_Mem_DQ_pin<15>   IOSTANDARD = LVCMOS33\r\r
2290          Comp: fpga_0_SRAM_Mem_DQ_pin<14>   IOSTANDARD = LVCMOS33\r\r
2291          Comp: fpga_0_SRAM_Mem_DQ_pin<13>   IOSTANDARD = LVCMOS33\r\r
2292          Comp: fpga_0_SRAM_Mem_DQ_pin<12>   IOSTANDARD = LVCMOS33\r\r
2293          Comp: fpga_0_SRAM_Mem_DQ_pin<11>   IOSTANDARD = LVCMOS33\r\r
2294          Comp: fpga_0_SRAM_Mem_DQ_pin<10>   IOSTANDARD = LVCMOS33\r\r
2295          Comp: fpga_0_SRAM_Mem_DQ_pin<9>   IOSTANDARD = LVCMOS33\r\r
2296          Comp: fpga_0_SRAM_Mem_DQ_pin<8>   IOSTANDARD = LVCMOS33\r\r
2297          Comp: fpga_0_SRAM_Mem_DQ_pin<7>   IOSTANDARD = LVCMOS33\r\r
2298          Comp: fpga_0_SRAM_Mem_DQ_pin<6>   IOSTANDARD = LVCMOS33\r\r
2299          Comp: fpga_0_SRAM_Mem_DQ_pin<5>   IOSTANDARD = LVCMOS33\r\r
2300          Comp: fpga_0_SRAM_Mem_DQ_pin<4>   IOSTANDARD = LVCMOS33\r\r
2301          Comp: fpga_0_SRAM_Mem_DQ_pin<3>   IOSTANDARD = LVCMOS33\r\r
2302          Comp: fpga_0_SRAM_Mem_DQ_pin<2>   IOSTANDARD = LVCMOS33\r\r
2303          Comp: fpga_0_SRAM_Mem_DQ_pin<1>   IOSTANDARD = LVCMOS33\r\r
2304          Comp: fpga_0_SRAM_Mem_DQ_pin<0>   IOSTANDARD = LVCMOS33\r\r
2305 \r\r
2306 \r\r
2307 Phase 2.7  Design Feasibility Check (Checksum:9d0c7baf) REAL time: 3 mins 16 secs \r\r
2308 \r\r
2309 Phase 3.31  Local Placement Optimization\r\r
2310 Phase 3.31  Local Placement Optimization (Checksum:dec56134) REAL time: 3 mins 16 secs \r\r
2311 \r\r
2312 Phase 4.37  Local Placement Optimization\r\r
2313 Phase 4.37  Local Placement Optimization (Checksum:dec56134) REAL time: 3 mins 16 secs \r\r
2314 \r\r
2315 Phase 5.33  Local Placement Optimization\r\r
2316 Phase 5.33  Local Placement Optimization (Checksum:dec56134) REAL time: 13 mins \r\r
2317 \r\r
2318 Phase 6.32  Local Placement Optimization\r\r
2319 Phase 6.32  Local Placement Optimization (Checksum:dec56134) REAL time: 13 mins 5 secs \r\r
2320 \r\r
2321 Phase 7.2  Initial Clock and IO Placement\r\r
2322 \r\r
2323 \r\r
2324 \r\r
2325 There are 16 clock regions on the target FPGA device:\r\r
2326 |------------------------------------------|------------------------------------------|\r\r
2327 | CLOCKREGION_X0Y7:                        | CLOCKREGION_X1Y7:                        |\r\r
2328 |   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |\r\r
2329 |   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use      |\r\r
2330 |   4 edge BUFIOs available, 0 in use      |   4 edge BUFIOs available, 0 in use      |\r\r
2331 |   4 center BUFIOs available, 0 in use    |                                          |\r\r
2332 |                                          |                                          |\r\r
2333 |------------------------------------------|------------------------------------------|\r\r
2334 | CLOCKREGION_X0Y6:                        | CLOCKREGION_X1Y6:                        |\r\r
2335 |   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |\r\r
2336 |   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use      |\r\r
2337 |   4 edge BUFIOs available, 3 in use      |   4 edge BUFIOs available, 0 in use      |\r\r
2338 |   0 center BUFIOs available, 0 in use    |                                          |\r\r
2339 |                                          |                                          |\r\r
2340 |------------------------------------------|------------------------------------------|\r\r
2341 | CLOCKREGION_X0Y5:                        | CLOCKREGION_X1Y5:                        |\r\r
2342 |   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |\r\r
2343 |   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use      |\r\r
2344 |   4 edge BUFIOs available, 0 in use      |   4 edge BUFIOs available, 0 in use      |\r\r
2345 |   2 center BUFIOs available, 0 in use    |                                          |\r\r
2346 |                                          |                                          |\r\r
2347 |------------------------------------------|------------------------------------------|\r\r
2348 | CLOCKREGION_X0Y4:                        | CLOCKREGION_X1Y4:                        |\r\r
2349 |   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |\r\r
2350 |   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use      |\r\r
2351 |   4 edge BUFIOs available, 0 in use      |   4 edge BUFIOs available, 0 in use      |\r\r
2352 |   2 center BUFIOs available, 0 in use    |                                          |\r\r
2353 |                                          |                                          |\r\r
2354 |------------------------------------------|------------------------------------------|\r\r
2355 | CLOCKREGION_X0Y3:                        | CLOCKREGION_X1Y3:                        |\r\r
2356 |   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |\r\r
2357 |   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use      |\r\r
2358 |   4 edge BUFIOs available, 0 in use      |   4 edge BUFIOs available, 0 in use      |\r\r
2359 |   2 center BUFIOs available, 0 in use    |                                          |\r\r
2360 |                                          |                                          |\r\r
2361 |------------------------------------------|------------------------------------------|\r\r
2362 | CLOCKREGION_X0Y2:                        | CLOCKREGION_X1Y2:                        |\r\r
2363 |   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |\r\r
2364 |   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use      |\r\r
2365 |   4 edge BUFIOs available, 3 in use      |   4 edge BUFIOs available, 0 in use      |\r\r
2366 |   2 center BUFIOs available, 0 in use    |                                          |\r\r
2367 |                                          |                                          |\r\r
2368 |------------------------------------------|------------------------------------------|\r\r
2369 | CLOCKREGION_X0Y1:                        | CLOCKREGION_X1Y1:                        |\r\r
2370 |   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |\r\r
2371 |   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use\r
2372       |\r\r
2373 |   4 edge BUFIOs available, 2 in use      |   4 edge BUFIOs available, 0 in use      |\r\r
2374 |   0 center BUFIOs available, 0 in use    |                                          |\r\r
2375 |                                          |                                          |\r\r
2376 |------------------------------------------|------------------------------------------|\r\r
2377 | CLOCKREGION_X0Y0:                        | CLOCKREGION_X1Y0:                        |\r\r
2378 |   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |\r\r
2379 |   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use      |\r\r
2380 |   4 edge BUFIOs available, 0 in use      |   4 edge BUFIOs available, 0 in use      |\r\r
2381 |   4 center BUFIOs available, 0 in use    |                                          |\r\r
2382 |                                          |                                          |\r\r
2383 |------------------------------------------|------------------------------------------|\r\r
2384 \r\r
2385 \r\r
2386 Clock-Region: <CLOCKREGION_X0Y1>\r\r
2387   key resource utilizations (used/available): edge-bufios - 2/4; bufrs - 0/2; regional-clock-spines - 0/4\r\r
2388 |-----------------------------------------------------------------------------------------------------------------------------------------------------------\r\r
2389 |       |    clock    | BRAM |     |    |        |        |       |       |       |      |      |     |      |\r\r
2390 |       |    region   | FIFO | DCM | GT | ILOGIC | OLOGIC |   FF  |  LUTM |  LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region)\r\r
2391 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2392 |       | Upper Region|  24  |  2  |  0 |   60   |   60   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the upper region\r\r
2393 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2394 |       |CurrentRegion|  24  |  4  |  0 |   40   |   40   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the current region\r\r
2395 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2396 |       | Lower Region|  24  |  0  |  0 |   80   |   80   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the lower region\r\r
2397 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2398 | clock |    region   |                                                                                      -----------------------------------------------\r\r
2399 |  type |  expansion  |                                                                                      | <IO/Regional clock Net Name>\r\r
2400 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2401 | BUFIO |             |   0  |  0  |  0 |    9   |    0   |     0 |     0 |     0 |   0  |   0  |  0  |   0  | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>"\r\r
2402 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2403 | BUFIO |             |   0  |  0  |  0 |    9   |    0   |     0 |     0 |     0 |   0  |   0  |  0  |   0  | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>"\r\r
2404 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2405 \r\r
2406 \r\r
2407 Clock-Region: <CLOCKREGION_X0Y2>\r\r
2408   key resource utilizations (used/available): edge-bufios - 3/4; center-bufios - 0/2; bufrs - 0/2; regional-clock-spines - 0/4\r\r
2409 |-------------------------------------------------------------------------------------------------------------------------------------------------------\r
2410 ----\r\r
2411 |       |    clock    | BRAM |     |    |        |        |       |       |       |      |      |     |      |\r\r
2412 |       |    region   | FIFO | DCM | GT | ILOGIC | OLOGIC |   FF  |  LUTM |  LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region)\r\r
2413 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2414 |       | Upper Region|   8  |  0  |  0 |   60   |   60   |  1280 |   640 |  1920 |   0  |   0  |  1  |   0  | <- Available resources in the upper region\r\r
2415 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2416 |       |CurrentRegion|  24  |  2  |  0 |   60   |   60   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the current region\r\r
2417 |-------|-------------|------|-----|----|--------|-------\r
2418 -|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2419 |       | Lower Region|  24  |  4  |  0 |   40   |   40   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the lower region\r\r
2420 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2421 | clock |    region   |                                                                                      -----------------------------------------------\r\r
2422 |  type |  expansion  |                                                                                      | <IO/Regional clock Net Name>\r\r
2423 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2424 | BUFIO |             |   0  |  0  |  0 |    9   |    0   |     0 |     0 |     0 |   0  |   0  |  0  |   0  | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>"\r\r
2425 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2426 | BUFIO |             |   0  |  0  |  0 |    9   |    0   |     0 |     0 |     0 |   0  |   0  |  0  |   0  | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>"\r\r
2427 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2428 | BUFIO |             |   0  |  0  |  0 |    9   |    0   |     0 |     0 |     0 |   0  |   0  |  0  |   0  | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>"\r\r
2429 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2430 \r\r
2431 \r\r
2432 Clock-Region: <CLOCKREGION_X0Y6>\r\r
2433   key resource utilizations (used/available): edge-bufios - 3/4; bufrs - 0/2; regional-clock-spines - 0/4\r\r
2434 |-----------------------------------------------------------------------------------------------------------------------------------------------------------\r\r
2435 |       |    clock    | BRAM |     |    |        |        |       |       |       |      |      |     |      |\r\r
2436 |       |    region   | FIFO | DCM | GT | ILOGIC | OLOGIC |   FF  |  LUTM |  LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region)\r\r
2437 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2438 |       | Upper Region|  24  |  0  |  0 |   80   |   80   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the upper region\r\r
2439 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2440 |       |CurrentRegion|  24  |  4  |  0 |   40   |   40   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the current region\r\r
2441 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2442 |       | Lower Region|  24  |  2  |  0 |   60   |   60   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the lower region\r\r
2443 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2444 | clock |    region   |                                                                                      -----------------------------------------------\r\r
2445 |  type |  expansion  |                                                                                      | <IO/Regional clock Net Name>\r\r
2446 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2447 | BUFIO |             |   0  |  0  |  0 |    9   |    0   |     0 |     0 | \r
2448     0 |   0  |   0  |  0  |   0  | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>"\r\r
2449 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2450 | BUFIO |             |   0  |  0  |  0 |    9   |    0   |     0 |     0 |     0 |   0  |   0  |  0  |   0  | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>"\r\r
2451 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2452 | BUFIO |             |   0  |  0  |  0 |    9   |    0   |     0 |     0 |     0 |   0  |   0  |  0  |   0  | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>"\r\r
2453 |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------\r\r
2454 \r\r
2455 \r\r
2456 \r\r
2457 \r\r
2458 ######################################################################################\r\r
2459 # REGIONAL CLOCKING RESOURCE DISTRIBUTION UCF REPORT:\r\r
2460 #\r\r
2461 # Number of Regional Clocking Regions in the device: 16  (4 clock spines in each)\r\r
2462 # Number of Regional Clock Networks used in this design: 8 (each network can be\r\r
2463 # composed of up to 3 clock spines and cover up to 3 regional clock regions)\r\r
2464 # \r\r
2465 ######################################################################################\r\r
2466 \r\r
2467 # IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" driven by "BUFIO_X0Y27"\r\r
2468 INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[7].u_iob_dqs/u_bufio_dqs" LOC =\r\r
2469 "BUFIO_X0Y27" ;\r\r
2470 NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" TNM_NET =\r\r
2471 "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" ;\r\r
2472 TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" AREA_GROUP =\r\r
2473 "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" ;\r\r
2474 AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" RANGE =\r\r
2475 CLOCKREGION_X0Y6;\r\r
2476 \r\r
2477 \r\r
2478 # IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" driven by "BUFIO_X0Y9"\r\r
2479 INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[0].u_iob_dqs/u_bufio_dqs" LOC =\r\r
2480 "BUFIO_X0Y9" ;\r\r
2481 NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" TNM_NET =\r\r
2482 "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" ;\r\r
2483 TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" AREA_GROUP =\r\r
2484 "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" ;\r\r
2485 AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" RANGE =\r\r
2486 CLOCKREGION_X0Y2;\r\r
2487 \r\r
2488 \r\r
2489 # IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" driven by "BUFIO_X0Y11"\r\r
2490 INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[4].u_iob_dqs/u_bufio_dqs" LOC =\r\r
2491 "BUFIO_X0Y11" ;\r\r
2492 NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" TNM_NET =\r\r
2493 "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" ;\r\r
2494 TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" AREA_GROUP =\r\r
2495 "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" ;\r\r
2496 AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" RANGE =\r\r
2497 CLOCKREGION_X0Y2;\r\r
2498 \r\r
2499 \r\r
2500 # IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" driven by "BUFIO_X0Y4"\r\r
2501 INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[1].u_iob_dqs/u_bufio_dqs" LOC =\r\r
2502 "BUFIO_X0Y4" ;\r\r
2503 NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" TNM_NET =\r\r
2504 "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" ;\r\r
2505 TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" AREA_GROUP =\r\r
2506 "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" ;\r\r
2507 AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" RANGE =\r\r
2508 CLOCKREGION_X0Y1;\r\r
2509 \r\r
2510 \r\r
2511 # IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" driven by "BUFIO_X0Y25"\r\r
2512 INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[5].u_iob_dqs/u_bufio_dqs" LOC =\r\r
2513 "BUFIO_X0Y25" ;\r\r
2514 NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" TNM_NET =\r\r
2515 "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" ;\r\r
2516 TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" AREA_GROUP =\r\r
2517 "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" ;\r\r
2518 AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" RANGE =\r\r
2519 CLOCKREGION_X0Y6;\r\r
2520 \r\r
2521 \r\r
2522 # IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" driven by "BUFIO_X0Y7"\r\r
2523 INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[2].u_iob_dqs/u_bufio_dqs" LOC =\r\r
2524 "BUFIO_X0Y7" ;\r\r
2525 NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" TNM_NET =\r\r
2526 "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" ;\r\r
2527 TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" AREA_GROUP =\r\r
2528 "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" ;\r\r
2529 AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" RANGE =\r\r
2530 CLOCKREGION_X0Y1;\r\r
2531 \r\r
2532 \r\r
2533 # IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" driven by "BUFIO_X0Y26"\r\r
2534 INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[6].u_iob_dqs/u_bufio_dqs" LOC =\r\r
2535 "BUFIO_X0Y26" ;\r\r
2536 NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" TNM_NET =\r\r
2537 "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" ;\r\r
2538 TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" AREA_GROUP =\r\r
2539 "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" ;\r\r
2540 AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" RANGE =\r\r
2541 CLOCKREGION_X0Y6;\r\r
2542 \r\r
2543 \r\r
2544 # IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" driven by "BUFIO_X0Y10"\r\r
2545 INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[3].u_iob_dqs/u_bufio_dqs" LOC =\r\r
2546 "BUFIO_X0Y10" ;\r\r
2547 NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" TNM_NET =\r\r
2548 "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" ;\r\r
2549 TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" AREA_GROUP =\r\r
2550 "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" ;\r\r
2551 AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" RANGE =\r\r
2552 CLOCKREGION_X0Y2;\r\r
2553 \r\r
2554 \r\r
2555 Phase 7.2  Initial Clock and IO Placement (Checksum:e5ad4bb9) REAL time: 13 mins 24 secs \r\r
2556 \r\r
2557 Phase 8.36  Local Placement Optimization\r\r
2558 Phase 8.36  Local Placement Optimization (Checksum:e5ad4bb9) REAL time: 13 mins 24 secs \r\r
2559 \r\r
2560 .........................\r
2561 .\r\r
2562 .\r
2563 ......\r
2564 .....\r
2565 .....\r
2566 .....\r
2567 .....\r
2568 ......\r
2569 ......\r
2570 .......\r
2571 ......\r
2572 .......\r
2573 .......\r
2574 ........\r
2575 .........\r
2576 ........\r
2577 ..\r\r
2578 Phase 9.30  Global Clock Region Assignment\r\r
2579 \r\r
2580 \r\r
2581 ######################################################################################\r\r
2582 # GLOBAL CLOCK NET DISTRIBUTION UCF REPORT:\r\r
2583 #\r\r
2584 # Number of Global Clock Regions : 16\r\r
2585 # Number of Global Clock Networks: 15\r\r
2586 #\r\r
2587 # Clock Region Assignment: SUCCESSFUL\r\r
2588 \r\r
2589 # Location of Clock Components\r\r
2590 INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT1.CLKOUT1_BUFG_INST" LOC = "BUFGCTRL_X0Y1" ;\r\r
2591 INST "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP/BUFG" LOC = "BUFGCTRL_X0Y30" ;\r\r
2592 INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.gtxclk_pll_bufg" LOC = "BUFGCTRL_X0Y29" ;\r\r
2593 INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.coreclk_pll_bufg" LOC = "BUFGCTRL_X0Y27" ;\r\r
2594 INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT2.CLKOUT2_BUFG_INST" LOC = "BUFGCTRL_X0Y2" ;\r\r
2595 INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_BUFG_for_CLKFBOUT.CLKFB_BUFG_INST" LOC = "BUFGCTRL_X0Y3" ;\r\r
2596 INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/notsame.usrclk_pll_bufg" LOC = "BUFGCTRL_X0Y28" ;\r\r
2597 INST "fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP/BUFG" LOC = "BUFGCTRL_X0Y8" ;\r\r
2598 INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.clkfbin_pll_bufg" LOC = "BUFGCTRL_X0Y26" ;\r\r
2599 INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT3.CLKOUT3_BUFG_INST" LOC = "BUFGCTRL_X0Y4" ;\r\r
2600 INST "clock_generator_0/clock_generator_0/Using_DCM0.DCM0_INST/Using_BUFG_for_CLK0.CLK0_BUFG_INST" LOC = "BUFGCTRL_X0Y7" ;\r\r
2601 INST "fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP/BUFG" LOC = "BUFGCTRL_X0Y31" ;\r\r
2602 INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT0.CLKOUT0_BUFG_INST" LOC = "BUFGCTRL_X0Y5" ;\r\r
2603 INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT4.CLKOUT4_BUFG_INST" LOC = "BUFGCTRL_X0Y6" ;\r\r
2604 INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_wrapper_i/bufg2" LOC = "BUFGCTRL_X0Y0" ;\r\r
2605 INST "clock_generator_0/clock_generator_0/Using_DCM0.DCM0_INST/DCM_INST/Using_DCM_ADV.DCM_ADV_INST" LOC = "DCM_ADV_X0Y0" ;\r\r
2606 INST "fpga_0_SRAM_ZBT_CLK_FB_pin" LOC = "IOB_X1Y111" ;\r\r
2607 INST "fpga_0_clk_1_sys_clk_pin" LOC = "IOB_X1Y109" ;\r\r
2608 INST "fpga_0_Ethernet_MAC_PHY_rx_clk_pin" LOC = "IOB_X1Y219" ;\r\r
2609 INST "fpga_0_Ethernet_MAC_PHY_tx_clk_pin" LOC = "IOB_X1Y217" ;\r\r
2610 INST "fpga_0_SysACE_CompactFlash_SysACE_CLK_pin" LOC = "IOB_X1Y105" ;\r\r
2611 INST "fpga_0_PCIe_Bridge_RXN_pin" LOC = "IPAD_X1Y12" ;\r\r
2612 INST "fpga_0_PCIe_Bridge_RXP_pin" LOC = "IPAD_X1Y13" ;\r\r
2613 INST "fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin" LOC = "IPAD_X1Y16" ;\r\r
2614 INST "fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin" LOC = "IPAD_X1Y17" ;\r\r
2615 INST "fpga_0_PCIe_Bridge_TXN_pin" LOC = "OPAD_X0Y8" ;\r\r
2616 INST "fpga_0_PCIe_Bridge_TXP_pin" LOC = "OPAD_X0Y9" ;\r\r
2617 INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.pll_adv_i" LOC = "PLL_ADV_X0Y5" ;\r\r
2618 INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst" LOC = "PLL_ADV_X0Y0" ;\r\r
2619 INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i" LOC = "GTX_DUAL_X0Y2" ;\r\r
2620 INST "ibufgds_76" LOC = "BUFDS_X0Y2" ;\r\r
2621 \r\r
2622 # clk_125_0000MHzPLL0 driven by BUFGCTRL_X0Y1\r\r
2623 NET "clk_125_0000MHzPLL0" TNM_NET = "TN_clk_125_0000MHzPLL0" ;\r\r
2624 TIMEGRP "TN_clk_125_0000MHzPLL0" AREA_GROUP = "CLKAG_clk_125_0000MHzPLL0" ;\r\r
2625 AREA_GROUP "CLKAG_clk_125_0000MHzPLL0" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
2626 \r\r
2627 # fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP driven by BUFGCTRL_X0Y30\r\r
2628 NET "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" TNM_NET = "TN_fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" ;\r\r
2629 TIMEGRP "TN_fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" AREA_GROUP = "CLKAG_fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" ;\r\r
2630 AREA_GROUP "CLKAG_fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X0Y1, CLOCKREGION_X0Y2, CLOCKREGION_X0Y3, CLOCKREGION_X0Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
2631 \r\r
2632 # PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk driven by BUFGCTRL_X0Y29\r\r
2633 NET "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" TNM_NET = "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" ;\r\r
2634 TIMEGRP "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" AREA_GROUP = "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" ;\r\r
2635 AREA_GROUP "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 ;\r\r
2636 \r\r
2637 # PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk driven by BUFGCTRL_X0Y27\r\r
2638 NET "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" TNM_NET = "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" ;\r\r
2639 TIMEGRP "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" AREA_GROUP = "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" ;\r\r
2640 AREA_GROUP "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
2641 \r\r
2642 # clk_125_0000MHzPLL0_ADJUST driven by BUFGCTRL_X0Y2\r\r
2643 NET "clk_125_0000MHzPLL0_ADJUST" TNM_NET = "TN_clk_125_0000MHzPLL0_ADJUST" ;\r\r
2644 TIMEGRP "TN_clk_125_0000MHzPLL0_ADJUST" AREA_GROUP = "CLKAG_clk_125_0000MHzPLL0_ADJUST" ;\r\r
2645 AREA_GROUP "CLKAG_clk_125_0000MHzPLL0_ADJUST" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
2646 \r\r
2647 # clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6> driven by BUFGCTRL_X0Y3\r\r
2648 NET "clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" TNM_NET = "TN_clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" ;\r\r
2649 TIMEGRP "TN_clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" AREA_GROUP = "CLKAG_clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" ;\r\r
2650 AREA_GROUP "CLKAG_clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X0Y1 ;\r\r
2651 \r\r
2652 # PCIe_Bridge/Bridge_Clk driven by BUFGCTRL_X0Y28\r\r
2653 NET "PCIe_Bridge/Bridge_Clk" TNM_NET = "TN_PCIe_Bridge/Bridge_Clk" ;\r\r
2654 TIMEGRP "TN_PCIe_Bridge/Bridge_Clk" AREA_GROUP = "CLKAG_PCIe_Bridge/Bridge_Clk" ;\r\r
2655 AREA_GROUP "CLKAG_PCIe_Bridge/Bridge_Clk" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
2656 \r\r
2657 # fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP driven by BUFGCTRL_X0Y8\r\r
2658 NET "fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" TNM_NET = "TN_fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" ;\r\r
2659 TIMEGRP "TN_fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" AREA_GROUP = "CLKAG_fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" ;\r\r
2660 AREA_GROUP "CLKAG_fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" RANGE =   CLOCKREGION_X1Y0, CLOCKREGION_X1Y1, CLOCKREGION_X1Y2, CLOCKREGION_X1Y3, CLOCKREGION_X1Y4 ;\r\r
2661 \r\r
2662 # PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin driven by BUFGCTRL_X0Y26\r\r
2663 NET "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" TNM_NET = "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" ;\r\r
2664 TIMEGRP "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" AREA_GROUP = "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" ;\r\r
2665 AREA_GROUP "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" RANGE =   CLOCKREGION_X0Y6, CLOCKREGION_X0Y7 ;\r\r
2666 \r\r
2667 # clk_200_0000MHz driven by BUFGCTRL_X0Y4\r\r
2668 NET "clk_200_0000MHz" TNM_NET = "TN_clk_200_0000MHz" ;\r\r
2669 TIMEGRP "TN_clk_200_0000MHz" AREA_GROUP = "CLKAG_clk_200_0000MHz" ;\r\r
2670 AREA_GROUP "CLKAG_clk_200_0000MHz" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
2671 \r\r
2672 # fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF driven by BUFGCTRL_X0Y7\r\r
2673 NET "fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" TNM_NET = "TN_fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" ;\r\r
2674 TIMEGRP "TN_fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" AREA_GROUP = "CLKAG_fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" ;\r\r
2675 AREA_GROUP "CLKAG_fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" RANGE =   CLOCKREGION_X1Y6, CLOCKREGION_X1Y7 ;\r\r
2676 \r\r
2677 # fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP driven by BUFGCTRL_X0Y31\r\r
2678 NET "fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" TNM_NET = "TN_fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" ;\r\r
2679 TIMEGRP "TN_fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" AREA_GROUP = "CLKAG_fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" ;\r\r
2680 AREA_GROUP "CLKAG_fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" RANGE =   CLOCKREGION_X1Y0, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X1Y6, CLOCKREGION_X1Y7 ;\r\r
2681 \r\r
2682 # clk_125_0000MHz90PLL0_ADJUST driven by BUFGCTRL_X0Y5\r\r
2683 NET "clk_125_0000MHz90PLL0_ADJUST" TNM_NET = "TN_clk_125_0000MHz90PLL0_ADJUST" ;\r\r
2684 TIMEGRP "TN_clk_125_0000MHz90PLL0_ADJUST" AREA_GROUP = "CLKAG_clk_125_0000MHz90PLL0_ADJUST" ;\r\r
2685 AREA_GROUP "CLKAG_clk_125_0000MHz90PLL0_ADJUST" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
2686 \r\r
2687 # clk_62_5000MHzPLL0_ADJUST driven by BUFGCTRL_X0Y6\r\r
2688 NET "clk_62_5000MHzPLL0_ADJUST" TNM_NET = "TN_clk_62_5000MHzPLL0_ADJUST" ;\r\r
2689 TIMEGRP "TN_clk_62_5000MHzPLL0_ADJUST" AREA_GROUP = "CLKAG_clk_62_5000MHzPLL0_ADJUST" ;\r\r
2690 AREA_GROUP "CLKAG_clk_62_5000MHzPLL0_ADJUST" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;\r\r
2691 \r\r
2692 # PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg driven by BUFGCTRL_X0Y0\r\r
2693 NET "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" TNM_NET = "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" ;\r\r
2694 TIMEGRP "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" AREA_GROUP = "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" ;\r\r
2695 AREA_GROUP "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" RANGE =   CLOCKREGION_X0Y6, CLOCKREGION_X0Y7 ;\r\r
2696 \r\r
2697 # NOTE: \r\r
2698 # This report is provided to help reproduce successful clock-region \r\r
2699 # assignments. The report provides range constraints for all global \r\r
2700 # clock networks, in a format that is directly usable in ucf files. \r\r
2701 #\r\r
2702 #END of Global Clock Net Distribution UCF Constraints\r\r
2703 ######################################################################################\r\r
2704 \r\r
2705 \r\r
2706 ######################################################################################\r\r
2707 GLOBAL CLOCK NET LOADS DISTRIBUTION REPORT:\r\r
2708 \r\r
2709 Number of Global Clock Regions : 16\r\r
2710 Number of Global Clock Networks: 15\r\r
2711 \r\r
2712 Clock Region Assignment: SUCCESSFUL\r\r
2713 \r\r
2714 Clock-Region: <CLOCKREGION_X0Y0> \r\r
2715  key resource utilizations (used/available): global-clocks - 2/10 ;\r\r
2716 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2717    BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
2718    FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
2719 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2720      12 |      0 |      0 |      0 |     80 |     80 |      0 |      0 |      0 |      0 |      2 |      0 |   1600 |   3200 | <- (Available Resources in this Region)\r\r
2721 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2722         |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
2723 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2724       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     17 |    656 |PCIe_Bridge/Bridge_Clk\r\r
2725       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      2 |    255 |clk_125_0000MHzPLL0_ADJUST\r\r
2726 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2727       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     19 |    911 | Total \r\r
2728 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2729 \r\r
2730 \r\r
2731 Clock-Region: <CLOCKREGION_X1Y0> \r\r
2732  key resource utilizations (used/available): global-clocks - 2/10 ;\r\r
2733 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2734    BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
2735    FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
2736 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2737       8 |      0 |      0 |      0 |     40 |     40 |     16 |      0 |      0 |      1 |      1 |      0 |   1920 |   2880 | <- (Available Resources in this Region)\r\r
2738 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2739         |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
2740 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2741       4 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      1 |      0 |      0 |     80 |   1263 |PCIe_Bridge/Bridge_Clk\r\r
2742       4 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      1 |      0 |      0 |     24 |     52 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk\r\r
2743 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2744       8 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      2 |      0 |      0 |    104 |   1315 | Total \r\r
2745 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2746 \r\r
2747 \r\r
2748 Clock-Region: <CLOCKREGION_X0Y1> \r\r
2749  key resource utilizations (used/available): global-clocks - 6/10 ;\r\r
2750 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2751    BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
2752    FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
2753 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2754      12 |      4 |      2 |      0 |     40 |     40 |      0 |      0 |      0 |      0 |      1 |      0 |   1600 |   3200 | <- (Available Resources in this Region)\r\r
2755 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2756         |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
2757 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2758       2 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      6 |    156 |PCIe_Bridge/Bridge_Clk\r\r
2759       0 |      0 |      0 |      0 |      0 |     18 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |clk_125_0000MHz90PLL0_ADJUST\r\r
2760       2 |      1 |      0 |      0 |      0 |     17 |      0 |      0 |      0 |      0 |      0 |      0 |     10 |    991 |clk_125_0000MHzPLL0_ADJUST\r\r
2761       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      1 |      0 |      0 |      0 |clk_200_0000MHz\r\r
2762       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      8 |clk_62_5000MHzPLL0_ADJUST\r\r
2763       0 |      0 |      1 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>\r\r
2764 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2765       4 |      1 |      1 |      0 |      0 |     35 |      0 |      0 |      0 |      0 |      1 |      0 |     16 |   1155 | Total \r\r
2766 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2767 \r\r
2768 \r\r
2769 Clock-Region: <CLOCKREGION_X1Y1> \r\r
2770  key resource utilizations (used/available): global-clocks - 4/10 ;\r\r
2771 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2772    BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
2773    FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
2774 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2775       8 |      0 |      0 |      0 |     40 |     40 |     16 |      0 |      0 |      0 |      1 |      0 |   1920 |   2880 | <- (Available Resources in this Region)\r\r
2776 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2777         |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
2778 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2779       1 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |    240 |   1088 |PCIe_Bridge/Bridge_Clk\r\r
2780       1 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     11 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk\r\r
2781       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |    104 |clk_125_0000MHzPLL0_ADJUST\r\r
2782       0 |      0 |      0 |      0 |      0 |      5 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP\r\r
2783 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2784       2 |      0 |      0 |      0 |      0 |      5 |      0 |      0 |      0 |      0 |      0 |      0 |    240 |   1203 | Total \r\r
2785 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2786 \r\r
2787 \r\r
2788 Clock-Region: <CLOCKREGION_X0Y2> \r\r
2789  key resource utilizations (used/available): global-clocks - 4/10 ;\r\r
2790 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2791    BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
2792    FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
2793 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2794      12 |      2 |      1 |      0 |     60 |     60 |      0 |      0 |      0 |      0 |      2 |      0 |   1600 |   3200 | <- (Available Resources in this Region)\r\r
2795 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2796         |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
2797 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2798       0 |      0 |      0 |      0 |      0 |     27 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     12 |clk_125_0000MHz90PLL0_ADJUST\r\r
2799       5 |      0 |      0 |      0 |      9 |     15 |      0 |      0 |      0 |      0 |      0 |      0 |     24 |   1156 |clk_125_0000MHzPLL0_ADJUST\r\r
2800       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      1 |      0 |      0 |      0 |clk_200_0000MHz\r\r
2801       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     99 |clk_62_5000MHzPLL0_ADJUST\r\r
2802 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2803       5 |      0 |      0 |      0 |      9 |     42 |      0 |      0 |      0 |      0 |      1 |      0 |     24 |   1267 | Total \r\r
2804 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2805 \r\r
2806 \r\r
2807 Clock-Region: <CLOCKREGION_X1Y2> \r\r
2808  key resource utilizations (used/available): global-clocks - 4/10 ;\r\r
2809 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2810    BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
2811    FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
2812 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2813       8 |      0 |      0 |      0 |     40 |     40 |     16 |      0 |      0 |      1 |      1 |      0 |   1920 |   2880 | <- (Available Resources in this Region)\r\r
2814 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2815         |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
2816 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2817       2 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     28 |    382 |PCIe_Bridge/Bridge_Clk\r\r
2818       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     90 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk\r\r
2819       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      2 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk\r\r
2820       3 |      0 |      0 |      0 |      0 |      5 |      0 |      0 |      0 |      0 |      0 |      0 |     48 |    725 |clk_125_0000MHzPLL0_ADJUST\r\r
2821 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2822       5 |      0 |      0 |      0 |      0 |      5 |      0 |      0 |      0 |      0 |      0 |      0 |     76 |   1199 | Total \r\r
2823 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2824 \r\r
2825 \r\r
2826 Clock-Region: <CLOCKREGION_X0Y3> \r\r
2827  key resource utilizations (used/available): global-clocks - 4/10 ;\r\r
2828 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2829    BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
2830    FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
2831 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2832       4 |      0 |      0 |      0 |     60 |     60 |      0 |      0 |      1 |      0 |      2 |     16 |    640 |   1280 | <- (Available Resources in this Region)\r\r
2833 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2834         |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
2835 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2836       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     86 |clk_125_0000MHz90PLL0_ADJUST\r\r
2837       0 |      0 |      0 |      0 |      8 |     17 |      0 |      0 |      1 |      0 |      0 |      0 |     12 |    281 |clk_125_0000MHzPLL0_ADJUST\r\r
2838       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      3 |clk_200_0000MHz\r\r
2839       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |    210 |clk_62_5000MHzPLL0_ADJUST\r\r
2840 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2841       0 |      0 |      0 |      0 |      8 |     17 |      0 |      0 |      1 |      0 |      0 |      0 |     12 |    580 | Total \r\r
2842 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2843 \r\r
2844 \r\r
2845 Clock-Region: <CLOCKREGION_X1Y3> \r\r
2846  key resource utilizations (used/available): global-clocks - 2/10 ;\r\r
2847 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2848    BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
2849    FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
2850 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2851       8 |      0 |      0 |      0 |     40 |     40 |     16 |      0 |      0 |      0 |      1 |      0 |   1920 |   2880 | <- (Available Resources in this Region)\r\r
2852 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2853         |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
2854 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2855       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     43 |PCIe_Bridge/Bridge_Clk\r\r
2856       4 |      0 |      0 |      0 |      0 |      0 |      3 |      0 |      0 |      0 |      0 |      0 |     99 |   1148 |clk_125_0000MHzPLL0_ADJUST\r\r
2857 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2858       4 |      0 |      0 |      0 |      0 |      0 |      3 |      0 |      0 |      0 |      0 |      0 |     99 |   1191 | Total \r\r
2859 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2860 \r\r
2861 \r\r
2862 Clock-Region: <CLOCKREGION_X0Y4> \r\r
2863  key resource utilizations (used/available): global-clocks - 4/10 ;\r\r
2864 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2865    BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
2866    FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
2867 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2868       4 |      0 |      0 |      0 |     60 |     60 |      0 |      0 |      1 |      0 |      2 |     16 |    640 |   1280 | <- (Available Resources in this Region)\r\r
2869 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2870         |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
2871 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2872       2 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     36 |clk_125_0000MHz90PLL0_ADJUST\r\r
2873       4 |      0 |      0 |      0 |      1 |     20 |      0 |      0 |      0 |      0 |      0 |      0 |     37 |    263 |clk_125_0000MHzPLL0_ADJUST\r\r
2874       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |    219 |clk_62_5000MHzPLL0_ADJUST\r\r
2875       0 |      0 |      0 |      0 |      6 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP\r\r
2876 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2877       6 |      0 |      0 |      0 |      7 |     20 |      0 |      0 |      0 |      0 |      0 |      0 |     37 |    518 | Total \r\r
2878 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2879 \r\r
2880 \r\r
2881 Clock-Region: <CLOCKREGION_X1Y4> \r\r
2882  key resource utilizations (used/available): global-clocks - 4/10 ;\r\r
2883 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2884    BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
2885    FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
2886 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2887      10 |      0 |      0 |      0 |     40 |     40 |     16 |      1 |      0 |      0 |      1 |      0 |   1920 |   2880 | <- (Available Resources in this Region)\r\r
2888 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2889         |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
2890 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2891       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     20 |PCIe_Bridge/Bridge_Clk\r\r
2892       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     83 |    834 |clk_125_0000MHzPLL0_ADJUST\r\r
2893       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      1 |fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP\r\r
2894       0 |      0 |      0 |      0 |     16 |     26 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     37 |fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP\r\r
2895 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2896       0 |      0 |      0 |      0 |     16 |     26 |      0 |      0 |      0 |      0 |      0 |      0 |     83 |    892 | Total \r\r
2897 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2898 \r\r
2899 \r\r
2900 Clock-Region: <CLOCKREGION_X0Y5> \r\r
2901  key resource utilizations (used/available): global-clocks - 4/10 ;\r\r
2902 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2903    BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
2904    FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
2905 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2906      12 |      2 |      1 |      0 |     60 |     60 |      0 |      0 |      0 |      0 |      2 |      0 |   1600 |   3200 | <- (Available Resources in this Region)\r\r
2907 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2908         |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
2909 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2910       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     48 |clk_125_0000MHz90PLL0_ADJUST\r\r
2911       0 |      0 |      0 |      0 |      0 |     27 |      0 |      0 |      0 |      0 |      0 |      0 |     74 |    579 |clk_125_0000MHzPLL0_ADJUST\r\r
2912       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      8 |    227 |clk_62_5000MHzPLL0_ADJUST\r\r
2913       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     15 |      4 |fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP\r\r
2914 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2915       0 |      0 |      0 |      0 |      0 |     27 |      0 |      0 |      0 |      0 |      0 |      0 |     97 |    858 | Total \r\r
2916 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2917 \r\r
2918 \r\r
2919 Clock-Region: <CLOCKREGION_X1Y5> \r\r
2920  key resource utilizations (used/available): global-clocks - 1/10 ;\r\r
2921 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2922    BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
2923    FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
2924 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2925      10 |      0 |      0 |      0 |     40 |     40 |     16 |      1 |      0 |      0 |      1 |      0 |   1920 |   2880 | <- (Available Resources in this Region)\r\r
2926 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2927         |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
2928 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2929       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     64 |    646 |clk_125_0000MHzPLL0_ADJUST\r\r
2930 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2931       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     64 |    646 | Total \r\r
2932 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2933 \r\r
2934 \r\r
2935 Clock-Region: <CLOCKREGION_X0Y6> \r\r
2936  key resource utilizations (used/available): global-clocks - 7/10 ;\r\r
2937 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2938    BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
2939    FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
2940 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2941      12 |      4 |      2 |      0 |     40 |     40 |      0 |      0 |      0 |      0 |      1 |      0 |   1600 |   3200 | <- (Available Resources in this Region)\r\r
2942 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2943         |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
2944 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2945       0 |      0 |      1 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg\r\r
2946       0 |      0 |      1 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin\r\r
2947       0 |      0 |      0 |      0 |      0 |     27 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      2 |clk_125_0000MHz90PLL0_ADJUST\r\r
2948       0 |      0 |      0 |      0 |      0 |      8 |      0 |      0 |      0 |      0 |      0 |      0 |     65 |    555 |clk_125_0000MHzPLL0_ADJUST\r\r
2949       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      1 |      0 |      0 |      0 |clk_200_0000MHz\r\r
2950       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      2 |    100 |clk_62_5000MHzPLL0_ADJUST\r\r
2951       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      9 |fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP\r\r
2952 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2953       0 |      0 |      2 |      0 |      0 |     35 |      0 |      0 |      0 |      0 |      1 |      0 |     67 |    666 | Total \r\r
2954 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2955 \r\r
2956 \r\r
2957 Clock-Region: <CLOCKREGION_X1Y6> \r\r
2958  key resource utilizations (used/available): global-clocks - 1/10 ;\r\r
2959 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2960    BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
2961    FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
2962 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2963       8 |      0 |      0 |      0 |     40 |     40 |     16 |      0 |      0 |      1 |      1 |      0 |   1920 |   2880 | <- (Available Resources in this Region)\r\r
2964 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2965         |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
2966 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2967       0 |      0 |      0 |      0 |     19 |     23 |      0 |      0 |      0 |      0 |      0 |      0 |     63 |    449 |clk_125_0000MHzPLL0_ADJUST\r\r
2968 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2969       0 |      0 |      0 |      0 |     19 |     23 |      0 |      0 |      0 |      0 |      0 |      0 |     63 |    449 | Total \r\r
2970 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2971 \r\r
2972 \r\r
2973 Clock-Region: <CLOCKREGION_X0Y7> \r\r
2974  key resource utilizations (used/available): global-clocks - 2/10 ;\r\r
2975 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2976    BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
2977    FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
2978 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2979      12 |      0 |      0 |      0 |     80 |     80 |      0 |      0 |      0 |      0 |      2 |      0 |   1600 |   3200 | <- (Available Resources in this Region)\r\r
2980 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2981         |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
2982 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2983       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      8 |    327 |clk_125_0000MHzPLL0_ADJUST\r\r
2984       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     20 |clk_62_5000MHzPLL0_ADJUST\r\r
2985 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2986       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      8 |    347 | Total \r\r
2987 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2988 \r\r
2989 \r\r
2990 Clock-Region: <CLOCKREGION_X1Y7> \r\r
2991  key resource utilizations (used/available): global-clocks - 1/10 ;\r\r
2992 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2993    BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)\r\r
2994    FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |\r\r
2995 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2996       8 |      0 |      0 |      0 |     40 |     40 |     16 |      0 |      0 |      0 |      1 |      0 |   1920 |   2880 | <- (Available Resources in this Region)\r\r
2997 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
2998         |        |        |        |        |        |        |        |        |        |        |        |        |        | <Global clock Net Name>\r\r
2999 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3000       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     34 |    208 |clk_125_0000MHzPLL0_ADJUST\r\r
3001 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3002       0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     34 |    208 | Total \r\r
3003 --------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------\r\r
3004 \r\r
3005 NOTE:\r\r
3006 The above detailed report is the initial placement of the logic after the clock region assignment. The final placement\r\r
3007 may be significantly different because of the various optimization steps which will follow. Specifically, logic blocks\r\r
3008 maybe moved to adjacent clock-regions as long as the "number of clocks per region" constraint is not violated.\r\r
3009 \r\r
3010 \r\r
3011 # END of Global Clock Net Loads Distribution Report:\r\r
3012 ######################################################################################\r\r
3013 \r\r
3014 \r\r
3015 Phase 9.30  Global Clock Region Assignment (Checksum:e5ad4bb9) REAL time: 14 mins 49 secs \r\r
3016 \r\r
3017 Phase 10.3  Local Placement Optimization\r\r
3018 Phase 10.3  Local Placement Optimization (Checksum:e5ad4bb9) REAL time: 14 mins 49 secs \r\r
3019 \r\r
3020 Phase 11.5  Local Placement Optimization\r\r
3021 Phase 11.5  Local Placement Optimization (Checksum:e5ad4bb9) REAL time: 14 mins 50 secs \r\r
3022 \r\r
3023 Phase 12.8  Global Placement\r\r
3024 ....\r
3025 ............................\r\r
3026 .....\r
3027 .......\r
3028 ........\r
3029 .......\r
3030 .......\r
3031 ......\r
3032 .......\r
3033 .......\r
3034 ......\r
3035 .......\r
3036 .......\r
3037 .......\r
3038 ......\r
3039 ........\r
3040 .......\r
3041 .........\r
3042 .........\r
3043 .........\r
3044 .........\r
3045 .........\r
3046 ....\r\r
3047 .\r
3048 .......\r
3049 ........\r
3050 .........\r
3051 ..\r\r
3052 .....\r
3053 .......\r
3054 .......\r
3055 ......\r
3056 .......\r
3057 .......\r
3058 .\r
3059 ....\r
3060 ......\r
3061 ......\r
3062 .....\r
3063 .....\r
3064 .....\r
3065 ....\r
3066 ..\r
3067 ......\r
3068 .....\r
3069 ......\r
3070 ..\r
3071 ...\r
3072 ......\r
3073 ......\r
3074 ........\r
3075 ......\r
3076 ......\r
3077 ..\r\r
3078 .\r
3079 ..\r
3080 ....\r
3081 ....\r
3082 .....\r
3083 ......\r
3084 ...\r
3085 ......\r
3086 ......\r
3087 .......\r\r
3088 ....\r
3089 ....\r
3090 ...\r
3091 ....\r
3092 .....\r
3093 ....\r
3094 .\r
3095 ..\r
3096 .....\r
3097 .....\r
3098 .....\r
3099 ..\r\r
3100 .\r
3101 .....\r
3102 ..\r
3103 .\r
3104 ......\r
3105 ......\r
3106 .\r
3107 ...\r
3108 .....\r\r
3109 .\r
3110 .....\r
3111 .....\r
3112 .....\r
3113 ......\r
3114 ......\r
3115 ......\r\r
3116 Phase 12.8  Global Placement (Checksum:651fc219) REAL time: 20 mins 14 secs \r\r
3117 \r\r
3118 Phase 13.29  Local Placement Optimization\r\r
3119 Phase 13.29  Local Placement Optimization (Checksum:651fc219) REAL time: 20 mins 14 secs \r\r
3120 \r\r
3121 Phase 14.5  Local Placement Optimization\r\r
3122 Phase 14.5  Local Placement Optimization (Checksum:651fc219) REAL time: 20 mins 19 secs \r\r
3123 \r\r
3124 Phase 15.18  Placement Optimization\r\r
3125 Phase 15.18  Placement Optimization (Checksum:11e1af7) REAL time: 23 mins 42 secs \r\r
3126 \r\r
3127 Phase 16.5  Local Placement Optimization\r\r
3128 Phase 16.5  Local Placement Optimization (Checksum:11e1af7) REAL time: 23 mins 46 secs \r\r
3129 \r\r
3130 Phase 17.34  Placement Validation\r\r
3131 Phase 17.34  Placement Validation (Checksum:11e1af7) REAL time: 23 mins 47 secs \r\r
3132 \r\r
3133 Total REAL time to Placer completion: 23 mins 51 secs \r\r
3134 Total CPU  time to Placer completion: 21 mins \r\r
3135 Running post-placement packing...\r\r
3136 Writing output files...\r\r
3137 \r\r
3138 Design Summary:\r\r
3139 Number of errors:      0\r\r
3140 Number of warnings:   50\r\r
3141 Slice Logic Utilization:\r\r
3142   Number of Slice Registers:                13,531 out of  44,800   30%\r\r
3143     Number used as Flip Flops:              13,529\r\r
3144     Number used as Latches:                      1\r\r
3145     Number used as Latch-thrus:                  1\r\r
3146   Number of Slice LUTs:                     14,602 out of  44,800   32%\r\r
3147     Number used as logic:                   13,948 out of  44,800   31%\r\r
3148       Number using O6 output only:          12,711\r\r
3149       Number using O5 output only:             318\r\r
3150       Number using O5 and O6:                  919\r\r
3151     Number used as Memory:                     541 out of  13,120    4%\r\r
3152       Number used as Dual Port RAM:            164\r\r
3153         Number using O6 output only:            12\r\r
3154         Number using O5 output only:            32\r\r
3155         Number using O5 and O6:                120\r\r
3156       Number used as Single Port RAM:            4\r\r
3157         Number using O6 output only:             4\r\r
3158       Number used as Shift Register:           373\r\r
3159         Number using O6 output only:           373\r\r
3160     Number used as exclusive route-thru:       113\r\r
3161   Number of route-thrus:                       497\r\r
3162     Number using O6 output only:               417\r\r
3163     Number using O5 output only:                70\r\r
3164     Number using O5 and O6:                     10\r\r
3165 \r\r
3166 Slice Logic Distribution:\r\r
3167   Number of occupied Slices:                 7,119 out of  11,200   63%\r\r
3168   Number of LUT Flip Flop pairs used:       19,423\r\r
3169     Number with an unused Flip Flop:         5,892 out of  19,423   30%\r\r
3170     Number with an unused LUT:               4,821 out of  19,423   24%\r\r
3171     Number of fully used LUT-FF pairs:       8,710 out of  19,423   44%\r\r
3172     Number of unique control sets:           1,396\r\r
3173     Number of slice register sites lost\r\r
3174       to control set restrictions:           3,277 out of  44,800    7%\r\r
3175 \r\r
3176   A LUT Flip Flop pair for this architecture represents one LUT paired with\r\r
3177   one Flip Flop within a slice.  A control set is a unique combination of\r\r
3178   clock, reset, set, and enable signals for a registered element.\r\r
3179   The Slice Logic Distribution report is not meaningful if the design is\r\r
3180   over-mapped for a non-slice resource or if Placement fails.\r\r
3181   OVERMAPPING of BRAM resources should be ignored if the design is\r\r
3182   over-mapped for a non-BRAM resource or if placement fails.\r\r
3183 \r\r
3184 IO Utilization:\r\r
3185   Number of bonded IOBs:                       255 out of     640   39%\r\r
3186     Number of LOCed IOBs:                      255 out of     255  100%\r\r
3187     IOB Flip Flops:                            494\r\r
3188     Number of bonded IPADs:                      4 out of      50    8%\r\r
3189     Number of bonded OPADs:                      2 out of      32    6%\r\r
3190 \r\r
3191 Specific Feature Utilization:\r\r
3192   Number of BlockRAM/FIFO:                      22 out of     148   14%\r\r
3193     Number using BlockRAM only:                 20\r\r
3194     Number using FIFO only:                      2\r\r
3195     Total primitives used:\r\r
3196       Number of 36k BlockRAM used:              16\r\r
3197       Number of 18k BlockRAM used:               6\r\r
3198       Number of 36k FIFO used:                   2\r\r
3199     Total Memory used (KB):                    756 out of   5,328   14%\r\r
3200   Number of BUFG/BUFGCTRLs:                     15 out of      32   46%\r\r
3201     Number used as BUFGs:                       15\r\r
3202   Number of IDELAYCTRLs:                         3 out of      22   13%\r\r
3203   Number of BUFDSs:                              1 out of       8   12%\r\r
3204   Number of BUFIOs:                              8 out of      80   10%\r\r
3205   Number of DCM_ADVs:                            1 out of      12    8%\r\r
3206   Number of DSP48Es:                             3 out of     128    2%\r\r
3207   Number of GTX_DUALs:                           1 out of       8   12%\r\r
3208   Number of PCIEs:                               1 out of       3   33%\r\r
3209     Number of LOCed PCIEs:                       1 out of       1  100%\r\r
3210   Number of PLL_ADVs:                            2 out of       6   33%\r\r
3211   Number of PPC440s:                             1 out of       1  100%\r\r
3212 \r\r
3213   Number of RPM macros:           64\r\r
3214 Average Fanout of Non-Clock Nets:                3.81\r\r
3215 \r\r
3216 Peak Memory Usage:  789 MB\r\r
3217 Total REAL time to MAP completion:  24 mins 34 secs \r\r
3218 Total CPU time to MAP completion:   21 mins 42 secs \r\r
3219 \r\r
3220 Mapping completed.\r\r
3221 See MAP report file "system_map.mrp" for details.\r\r
3222 \r\r
3223 \r\r
3224 \r\r
3225 #----------------------------------------------#\r\r
3226 # Starting program par\r\r
3227 # par -ise ../__xps/ise/system.ise -w -ol high system_map.ncd system.ncd\r\r
3228 system.pcf \r\r
3229 #----------------------------------------------#\r\r
3230 Release 11.2 - par L.46 (nt)\r\r
3231 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
3232 PMSPEC -- Overriding Xilinx file <C:/devtools/Xilinx/11.1/EDK/data/parBmgr.acd> with local file\r\r
3233 <c:/devtools/Xilinx/11.1/ISE/data/parBmgr.acd>\r\r
3234 \r\r
3235 \r\r
3236 Loading device for application Rf_Device from file '5vfx70t.nph' in environment\r\r
3237 c:\devtools\Xilinx\11.1\ISE;C:\devtools\Xilinx\11.1\EDK.\r\r
3238    "system" is an NCD, version 3.2, device xc5vfx70t, package ff1136, speed -1\r\r
3239 \r\r
3240 Constraints file: system.pcf.\r\r
3241    "system" is an NCD, version 3.2, device xc5vfx70t, package ff1136, speed -1\r\r
3242 WARNING:ConstraintSystem:65 - Constraint <NET "PCIe_Bridge/Bridge_Clk" PERIOD = 8 ns HIGH 50%;> [system.pcf(78662)]\r\r
3243    overrides constraint <NET "PCIe_Bridge/Bridge_Clk" PERIOD = 8 ns HIGH 50%;> [system.pcf(78661)].\r\r
3244 \r\r
3245 \r\r
3246 Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)\r\r
3247 Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts)\r\r
3248 \r\r
3249 WARNING:Timing:3223 - Timing constraint TS_MC_RDEN_SEL_MUX = MAXDELAY FROM TIMEGRP "TNM_RDEN_SEL_MUX" TO TIMEGRP       \r\r
3250    "TNM_CLK0" TS_MC_CLK * 4; ignored during timing analysis.\r\r
3251 INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more information, see the TSI report.  Please\r\r
3252    consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.\r\r
3253 \r\r
3254 Device speed data version:  "PRODUCTION 1.65 2009-06-01".\r\r
3255 \r\r
3256 \r\r
3257 \r\r
3258 Device Utilization Summary:\r\r
3259 \r\r
3260    Number of BUFDSs                          1 out of 8      12%\r\r
3261    Number of BUFGs                          15 out of 32     46%\r\r
3262    Number of BUFIOs                          8 out of 80     10%\r\r
3263    Number of DCM_ADVs                        1 out of 12      8%\r\r
3264    Number of DSP48Es                         3 out of 128     2%\r\r
3265    Number of FIFO36_72_EXPs                  2 out of 148     1%\r\r
3266       Number of LOCed FIFO36_72_EXPs         2 out of 2     100%\r\r
3267 \r\r
3268    Number of GTX_DUALs                       1 out of 8      12%\r\r
3269    Number of IDELAYCTRLs                     3 out of 22     13%\r\r
3270       Number of LOCed IDELAYCTRLs            3 out of 3     100%\r\r
3271 \r\r
3272    Number of ILOGICs                       131 out of 800    16%\r\r
3273       Number of LOCed ILOGICs                8 out of 131     6%\r\r
3274 \r\r
3275    Number of External IOBs                 255 out of 640    39%\r\r
3276       Number of LOCed IOBs                 255 out of 255   100%\r\r
3277 \r\r
3278    Number of IODELAYs                       80 out of 800    10%\r\r
3279       Number of LOCed IODELAYs               8 out of 80     10%\r\r
3280 \r\r
3281    Number of External IPADs                  4 out of 690     1%\r\r
3282       Number of LOCed IPADs                  4 out of 4     100%\r\r
3283 \r\r
3284    Number of JTAGPPCs                        1 out of 1     100%\r\r
3285    Number of OLOGICs                       236 out of 800    29%\r\r
3286    Number of External OPADs                  2 out of 32      6%\r\r
3287       Number of LOCed OPADs                  2 out of 2     100%\r\r
3288 \r\r
3289    Number of PCIEs                           1 out of 3      33%\r\r
3290       Number of LOCed PCIEs                  1 out of 1     100%\r\r
3291 \r\r
3292    Number of PLL_ADVs                        2 out of 6      33%\r\r
3293    Number of PPC440s                         1 out of 1     100%\r\r
3294    Number of RAMB18X2SDPs                    4 out of 148     2%\r\r
3295    Number of RAMB36SDP_EXPs                  6 out of 148     4%\r\r
3296       Number of LOCed RAMB36SDP_EXPs         1 out of 6      16%\r\r
3297 \r\r
3298    Number of RAMB36_EXPs                    10 out of 148     6%\r\r
3299       Number of LOCed RAMB36_EXPs            6 out of 10     60%\r\r
3300 \r\r
3301    Number of Slice Registers             13531 out of 44800  30%\r\r
3302       Number used as Flip Flops          13529\r\r
3303       Number used as Latches                 1\r\r
3304       Number used as LatchThrus              1\r\r
3305 \r\r
3306    Number of Slice LUTS                  14602 out of 44800  32%\r\r
3307    Number of Slice LUT-Flip Flop pairs   19423 out of 44800  43%\r\r
3308 \r\r
3309 \r\r
3310 Overall effort level (-ol):   High \r\r
3311 Router effort level (-rl):    High \r\r
3312 \r\r
3313 Starting initial Timing Analysis.  REAL time: 1 mins 3 secs \r\r
3314 Finished initial Timing Analysis.  REAL time: 1 mins 5 secs \r\r
3315 \r\r
3316 WARNING:Par:288 - The signal PCIe_Bridge/PCIe_Bridge/sig_sb_txrem_n<0> has no load.  PAR will not attempt to route this\r\r
3317    signal.\r\r
3318 WARNING:Par:288 - The signal PCIe_Bridge/PCIe_Bridge/sig_MB_TxREMn<0> has no load.  PAR will not attempt to route this\r\r
3319    signal.\r\r
3320 WARNING:Par:288 - The signal xps_bram_if_cntlr_1_port_BRAM_Addr<31> has no load.  PAR will not attempt to route this\r\r
3321    signal.\r\r
3322 WARNING:Par:288 - The signal xps_bram_if_cntlr_1_port_BRAM_Addr<30> has no load.  PAR will not attempt to route this\r\r
3323    signal.\r\r
3324 WARNING:Par:288 - The signal PCIe_Bridge/PCIe_Bridge/sig_MB_RxFull has no load.  PAR will not attempt to route this\r\r
3325    signal.\r\r
3326 Starting Router\r\r
3327 \r\r
3328 INFO:Route:501 - One or more directed routing (DIRT) constraints generated for a specific device have been found. Note\r\r
3329    that DIRT strings are guaranteed to work only on the same device they were created for. If the DIRT constraints fail,\r\r
3330    verify that the same connectivity is available in the target device for this implementation. \r\r
3331 \r\r
3332 Phase  1  : 95521 unrouted;      REAL time: 1 mins 22 secs \r\r
3333 \r\r
3334 Phase  2  : 84728 unrouted;      REAL time: 1 mins 35 secs \r\r
3335 \r\r
3336 Phase  3  : 34551 unrouted;      REAL time: 3 mins 59 secs \r\r
3337 \r\r
3338 Phase  4  : 34616 unrouted; (Setup:0, Hold:93713, Component Switching Limit:0)     REAL time: 4 mins 32 secs \r\r
3339 \r\r
3340 Updating file: system.ncd with current fully routed design.\r\r
3341 \r\r
3342 Phase  5  : 0 unrouted; (Setup:0, Hold:92310, Component Switching Limit:0)     REAL time: 5 mins 40 secs \r\r
3343 \r\r
3344 Phase  6  : 0 unrouted; (Setup:0, Hold:92310, Component Switching Limit:0)     REAL time: 5 mins 40 secs \r\r
3345 \r\r
3346 Phase  7  : 0 unrouted; (Setup:0, Hold:92310, Component Switching Limit:0)     REAL time: 5 mins 40 secs \r\r
3347 \r\r
3348 Phase  8  : 0 unrouted; (Setup:0, Hold:92310, Component Switching Limit:0)     REAL time: 5 mins 40 secs \r\r
3349 \r\r
3350 Phase  9  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 6 mins 40 secs \r\r
3351 \r\r
3352 Phase 10  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 6 mins 55 secs \r\r
3353 Total REAL time to Router completion: 6 mins 55 secs \r\r
3354 Total CPU time to Router completion: 6 mins 44 secs \r\r
3355 \r\r
3356 Partition Implementation Status\r\r
3357 -------------------------------\r\r
3358 \r\r
3359   No Partitions were found in this design.\r\r
3360 \r\r
3361 -------------------------------\r\r
3362 \r\r
3363 Generating "PAR" statistics.\r\r
3364 \r\r
3365 **************************\r\r
3366 Generating Clock Report\r\r
3367 **************************\r\r
3368 \r\r
3369 +---------------------+--------------+------+------+------------+-------------+\r\r
3370 |        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|\r\r
3371 +---------------------+--------------+------+------+------------+-------------+\r\r
3372 |clk_125_0000MHzPLL0_ |              |      |      |            |             |\r\r
3373 |              ADJUST | BUFGCTRL_X0Y2| No   | 3788 |  0.520     |  2.062      |\r\r
3374 +---------------------+--------------+------+------+------------+-------------+\r\r
3375 |PCIe_Bridge/Bridge_C |              |      |      |            |             |\r\r
3376 |                  lk |BUFGCTRL_X0Y28| No   | 1452 |  0.412     |  2.085      |\r\r
3377 +---------------------+--------------+------+------+------------+-------------+\r\r
3378 |clk_62_5000MHzPLL0_A |              |      |      |            |             |\r\r
3379 |               DJUST | BUFGCTRL_X0Y6| No   |  504 |  0.299     |  2.065      |\r\r
3380 +---------------------+--------------+------+------+------------+-------------+\r\r
3381 |PCIe_Bridge/PCIe_Bri |              |      |      |            |             |\r\r
3382 |dge/comp_block_plus/ |              |      |      |            |             |\r\r
3383 |comp_endpoint/core_c |              |      |      |            |             |\r\r
3384 |                  lk |BUFGCTRL_X0Y27| No   |   93 |  0.266     |  2.085      |\r\r
3385 +---------------------+--------------+------+------+------------+-------------+\r\r
3386 |fpga_0_SysACE_Compac |              |      |      |            |             |\r\r
3387 |tFlash_SysACE_CLK_pi |              |      |      |            |             |\r\r
3388 |             n_BUFGP | BUFGCTRL_X0Y8| No   |   55 |  0.163     |  1.770      |\r\r
3389 +---------------------+--------------+------+------+------------+-------------+\r\r
3390 |fpga_0_Ethernet_MAC_ |              |      |      |            |             |\r\r
3391 |PHY_rx_clk_pin_BUFGP |              |      |      |            |             |\r\r
3392 |                     |BUFGCTRL_X0Y30| No   |   12 |  0.038     |  1.879      |\r\r
3393 +---------------------+--------------+------+------+------------+-------------+\r\r
3394 |clk_125_0000MHz90PLL |              |      |      |            |             |\r\r
3395 |            0_ADJUST | BUFGCTRL_X0Y5| No   |  167 |  0.285     |  2.028      |\r\r
3396 +---------------------+--------------+------+------+------------+-------------+\r\r
3397 |PCIe_Bridge/PCIe_Bri |              |      |      |            |             |\r\r
3398 |dge/comp_block_plus/ |              |      |      |            |             |\r\r
3399 |comp_endpoint/pcie_b |              |      |      |            |             |\r\r
3400 |        lk/gt_usrclk |BUFGCTRL_X0Y29| No   |    6 |  0.058     |  1.886      |\r\r
3401 +---------------------+--------------+------+------+------------+-------------+\r\r
3402 |     clk_200_0000MHz | BUFGCTRL_X0Y4| No   |    4 |  0.100     |  1.879      |\r\r
3403 +---------------------+--------------+------+------+------------+-------------+\r\r
3404 |DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |\r\r
3405 |M/u_ddr2_top/u_mem_i |              |      |      |            |             |\r\r
3406 |f_top/u_phy_top/u_ph |              |      |      |            |             |\r\r
3407 | y_io/delayed_dqs<0> |        IO Clk| No   |   18 |  0.095     |  0.419      |\r\r
3408 +---------------------+--------------+------+------+------------+-------------+\r\r
3409 |DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |\r\r
3410 |M/u_ddr2_top/u_mem_i |              |      |      |            |             |\r\r
3411 |f_top/u_phy_top/u_ph |              |      |      |            |             |\r\r
3412 | y_io/delayed_dqs<1> |        IO Clk| No   |   18 |  0.083     |  0.380      |\r\r
3413 +---------------------+--------------+------+------+------------+-------------+\r\r
3414 |fpga_0_Ethernet_MAC_ |              |      |      |            |             |\r\r
3415 |PHY_tx_clk_pin_BUFGP |              |      |      |            |             |\r\r
3416 |                     |BUFGCTRL_X0Y31| No   |    6 |  0.004     |  1.941      |\r\r
3417 +---------------------+--------------+------+------+------------+-------------+\r\r
3418 |DDR2_SDRAM/DDR2_SDRA |              |      |\r
3419       |            |             |\r\r
3420 |M/u_ddr2_top/u_mem_i |              |      |      |            |             |\r\r
3421 |f_top/u_phy_top/u_ph |              |      |      |            |             |\r\r
3422 | y_io/delayed_dqs<2> |        IO Clk| No   |   18 |  0.101     |  0.425      |\r\r
3423 +---------------------+--------------+------+------+------------+-------------+\r\r
3424 |DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |\r\r
3425 |M/u_ddr2_top/u_mem_i |              |      |      |            |             |\r\r
3426 |f_top/u_phy_top/u_ph |              |      |      |            |             |\r\r
3427 | y_io/delayed_dqs<3> |        IO Clk| No   |   18 |  0.107     |  0.404      |\r\r
3428 +---------------------+--------------+------+------+------------+-------------+\r\r
3429 |DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |\r\r
3430 |M/u_ddr2_top/u_mem_i |              |      |      |            |             |\r\r
3431 |f_top/u_phy_top/u_ph |              |      |      |            |             |\r\r
3432 | y_io/delayed_dqs<5> |        IO Clk| No   |   18 |  0.101     |  0.425      |\r\r
3433 +---------------------+--------------+------+------+------------+-------------+\r\r
3434 |DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |\r\r
3435 |M/u_ddr2_top/u_mem_i |              |      |      |            |             |\r\r
3436 |f_top/u_phy_top/u_ph |              |      |      |            |             |\r\r
3437 | y_io/delayed_dqs<4> |        IO Clk| No   |   18 |  0.101     |  0.425      |\r\r
3438 +---------------------+--------------+------+------+------------+-------------+\r\r
3439 |DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |\r\r
3440 |M/u_ddr2_top/u_mem_i |              |      |      |            |             |\r\r
3441 |f_top/u_phy_top/u_ph |              |      |      |            |             |\r\r
3442 | y_io/delayed_dqs<6> |        IO Clk| No   |   18 |  0.096     |  0.393      |\r\r
3443 +---------------------+--------------+------+------+------------+-------------+\r\r
3444 |DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |\r\r
3445 |M/u_ddr2_top/u_mem_i |              |      |      |            |             |\r\r
3446 |f_top/u_phy_top/u_ph |              |      |      |            |             |\r\r
3447 | y_io/delayed_dqs<7> |        IO Clk| No   |   18 |  0.101     |  0.425      |\r\r
3448 +---------------------+--------------+------+------+------------+-------------+\r\r
3449 | clk_125_0000MHzPLL0 | BUFGCTRL_X0Y1| No   |    2 |  0.000     |  1.739      |\r\r
3450 +---------------------+--------------+------+------+------------+-------------+\r\r
3451 |PCIe_Bridge/PCIe_Bri |              |      |      |            |             |\r\r
3452 |dge/comp_block_plus/ |              |      |      |            |             |\r\r
3453 |comp_endpoint/pcie_b |              |      |      |            |             |\r\r
3454 |lk/SIO/.pcie_gt_wrap |              |      |      |            |             |\r\r
3455 |  per_i/icdrreset<0> |         Local|      |    1 |  0.000     |  0.585      |\r\r
3456 +---------------------+--------------+------+------+------------+-------------+\r\r
3457 |Ethernet_MAC/Etherne |              |      |      |            |             |\r\r
3458 |  t_MAC/phy_tx_clk_i |         Local|      |    9 |  2.887     |  3.720      |\r\r
3459 +---------------------+--------------+------+------+------------+-------------+\r\r
3460 |RS232_Uart_1_Interru |              |      |      |            |             |\r\r
3461 |                  pt |         Local|      |    1 |  0.000     |  0.743      |\r\r
3462 +---------------------+--------------+------+------+------------+-------------+\r\r
3463 |ppc440_0_jtagppc_bus |              |      |      |            |             |\r\r
3464 |         _JTGC405TCK |         Local|      |    1 |  0.000     |  1.526      |\r\r
3465 +---------------------+--------------+------+------+------------+-------------+\r\r
3466 \r\r
3467 * Net Skew is the difference between the minimum and maximum routing\r\r
3468 only delays for the net. Note this is different from Clock Skew which\r\r
3469 is reported in TRCE timing report. Clock Skew is the difference between\r\r
3470 the minimum and maximum path delays which includes logic delays.\r\r
3471 \r\r
3472 Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)\r\r
3473 \r\r
3474 Number of Timing Constraints that were not applied: 5\r\r
3475 \r\r
3476 Asterisk (*) preceding a constraint indicates it was not met.\r\r
3477    This may be due to a setup or hold violation.\r\r
3478 \r\r
3479 ----------------------------------------------------------------------------------------------------------\r\r
3480   Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   \r\r
3481                                             |             |    Slack   | Achievable | Errors |    Score   \r\r
3482 ----------------------------------------------------------------------------------------------------------\r\r
3483   NET "PCIe_Bridge/Bridge_Clk" PERIOD = 8 n | SETUP       |     0.067ns|     7.933ns|       0|           0\r\r
3484   s HIGH 50%                                | HOLD        |     0.035ns|            |       0|           0\r\r
3485                                             | MINPERIOD   |     0.000ns|     8.000ns|       0|           0\r\r
3486 ------------------------------------------------------------------------------------------------------\r\r
3487   NET "PCIe_Bridge/PCIe_Bridge/comp_block_p | SETUP       |     0.051ns|     3.949ns|       0|           0\r\r
3488   lus/comp_endpoint/core_clk" PERIOD =      | HOLD        |     0.349ns|            |       0|           0\r\r
3489       4 ns HIGH 50%                         | MINPERIOD   |     0.000ns|     4.000ns|       0|           0\r\r
3490 ------------------------------------------------------------------------------------------------------\r\r
3491   TS_clock_generator_0_clock_generator_0_PL | SETUP       |     0.028ns|     7.972ns|       0|           0\r\r
3492   L0_CLK_OUT_2_ = PERIOD TIMEGRP         "c | HOLD        |     0.021ns|            |       0|           0\r\r
3493   lock_generator_0_clock_generator_0_PLL0_C |             |            |            |        |            \r\r
3494   LK_OUT_2_" TS_sys_clk_pin *         1.25  |             |            |            |        |            \r\r
3495   HIGH 50%                                  |             |            |            |        |            \r\r
3496 ------------------------------------------------------------------------------------------------------\r\r
3497   TS_DQ_CE = MAXDELAY FROM TIMEGRP "TNM_DQ_ | SETUP       |     0.030ns|     1.870ns|       0|           0\r\r
3498   CE_IDDR" TO TIMEGRP "TNM_DQS_FLOPS"       | HOLD        |     1.027ns|            |       0|           0\r\r
3499      1.9 ns                                 |             |            |            |        |            \r\r
3500 ------------------------------------------------------------------------------------------------------\r\r
3501   NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.045ns|     0.805ns|       0|           0\r\r
3502   _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |            \r\r
3503   dqs[0].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |            \r\r
3504   DELAY = 0.85 ns                           |             |            |            |        |            \r\r
3505 ------------------------------------------------------------------------------------------------------\r\r
3506   NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.045ns|     0.805ns|       0|           0\r\r
3507   _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |            \r\r
3508   dqs[1].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |            \r\r
3509   DELAY = 0.85 ns                           |             |            |            |        |            \r\r
3510 ------------------------------------------------------------------------------------------------------\r\r
3511   NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.045ns|     0.805ns|       0|           0\r\r
3512   _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |            \r\r
3513   dqs[5].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |            \r\r
3514   DELAY = 0.85 ns                           |             |            |            |        |            \r\r
3515 ------------------------------------------------------------------------------------------------------\r\r
3516   NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.047ns|     0.803ns|       0|           0\r\r
3517   _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |            \r\r
3518   dqs[2].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |            \r\r
3519   DELAY = 0.85 ns                           |             |            |            |        |            \r\r
3520 ------------------------------------------------------------------------------------------------------\r\r
3521   NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.047ns|     0.803ns|       0|           0\r\r
3522   _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |            \r\r
3523   dqs[3].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |            \r\r
3524   DELAY = 0.85 ns                           |             |            |            |        |            \r\r
3525 ------------------------------------------------------------------------------------------------------\r\r
3526   NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.047ns|     0.803ns|       0|           0\r\r
3527   _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |            \r\r
3528   dqs[4].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |            \r\r
3529   DELAY = 0.85 ns                           |             |            |            |        |            \r\r
3530 ------------------------------------------------------------------------------------------------------\r\r
3531   NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.047ns|     0.803ns|       0|           0\r\r
3532   _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |            \r\r
3533   dqs[6].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |            \r\r
3534   DELAY = 0.85 ns                           |             |            |            |        |            \r\r
3535 ------------------------------------------------------------------------------------------------------\r\r
3536   NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.047ns|     0.803ns|       0|           0\r\r
3537   _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |            \r\r
3538   dqs[7].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |            \r\r
3539   DELAY = 0.85 ns                           |             |            |            |        |            \r\r
3540 ------------------------------------------------------------------------------------------------------\r\r
3541   NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.071ns|     0.529ns|       0|           0\r\r
3542   _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |            \r\r
3543   qs<0>"         MAXDELAY = 0.6 ns          |             |            |            |        |            \r\r
3544 ------------------------------------------------------------------------------------------------------\r\r
3545   NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.071ns|     0.529ns|       0|           0\r\r
3546   _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |            \r\r
3547   qs<1>"         MAXDELAY = 0.6 ns          |             |            |            |        |            \r\r
3548 ------------------------------------------------------------------------------------------------------\r\r
3549   NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.071ns|     0.529ns|       0|           0\r\r
3550   _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |            \r\r
3551   qs<2>"         MAXDELAY = 0.6 ns          |             |            |            |        |            \r\r
3552 ------------------------------------------------------------------------------------------------------\r\r
3553   NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.071ns|     0.529ns|       0|           0\r\r
3554   _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |            \r\r
3555   qs<3>"         MAXDELAY = 0.6 ns          |             |            |            |        |            \r\r
3556 ------------------------------------------------------------------------------------------------------\r\r
3557   NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.071ns|     0.529ns|       0|           0\r\r
3558   _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |            \r\r
3559   qs<4>"         MAXDELAY = 0.6 ns          |             |            |            |        |            \r\r
3560 ------------------------------------------------------------------------------------------------------\r\r
3561   NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.071ns|     0.529ns|       0|           0\r\r
3562   _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |            \r\r
3563   qs<5>"         MAXDELAY = 0.6 ns          |             |            |            |        |            \r\r
3564 ------------------------------------------------------------------------------------------------------\r\r
3565   NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.071ns|     0.529ns|       0|           0\r\r
3566   _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |            \r\r
3567   qs<6>"         MAXDELAY = 0.6 ns          |             |            |            |        |            \r\r
3568 ------------------------------------------------------------------------------------------------------\r\r
3569   NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.071ns|     0.529ns|       0|           0\r\r
3570   _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |            \r\r
3571   qs<7>"         MAXDELAY = 0.6 ns          |             |            |            |        |            \r\r
3572 ------------------------------------------------------------------------------------------------------\r\r
3573   TS_PCIe_PLB = MAXDELAY FROM TIMEGRP "Brid | SETUP       |     0.187ns|     7.813ns|       0|           0\r\r
3574   ge_Clk" TO TIMEGRP "SPLB_Clk" 8 ns        | HOLD        |     0.502ns|            |       0|           0\r\r
3575     DATAPATHONLY                            |             |            |            |        |            \r\r
3576 ------------------------------------------------------------------------------------------------------\r\r
3577   TS_PLB_PCIe = MAXDELAY FROM TIMEGRP "SPLB | SETUP       |     0.510ns|     7.490ns|       0|           0\r\r
3578   _Clk" TO TIMEGRP "Bridge_Clk" 8 ns        | HOLD        |     0.456ns|            |       0|           0\r\r
3579     DATAPATHONLY                            |             |            |            |        |            \r\r
3580 ------------------------------------------------------------------------------------------------------\r\r
3581   TS_MC_CLK = PERIOD TIMEGRP "mc_clk" 5 ns  | MINPERIOD   |     1.010ns|     3.990ns|       0|           0\r\r
3582   HIGH 50%                                  |             |            |            |        |            \r\r
3583 ------------------------------------------------------------------------------------------------------\r\r
3584   TSRXIN_Ethernet_MAC = MAXDELAY FROM TIMEG | MAXDELAY    |     1.695ns|     4.305ns|       0|           0\r\r
3585   RP "PADS" TO TIMEGRP         "RXCLK_GRP_E | HOLD        |     1.060ns|            |       0|           0\r\r
3586   thernet_MAC" 6 ns                         |             |            |            |        |            \r\r
3587 ------------------------------------------------------------------------------------------------------\r\r
3588   TS_clock_generator_0_clock_generator_0_PL | SETUP       |     2.151ns|     4.917ns|       0|           0\r\r
3589   L0_CLK_OUT_0_ = PERIOD TIMEGRP         "c | HOLD        |     0.404ns|            |       0|           0\r\r
3590   lock_generator_0_clock_generator_0_PLL0_C |             |            |            |        |            \r\r
3591   LK_OUT_0_" TS_sys_clk_pin *         1.25  |             |            |            |        |            \r\r
3592   PHASE 2 ns HIGH 50%                       |             |            |            |        |            \r\r
3593 ------------------------------------------------------------------------------------------------------\r\r
3594   TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_ | MINLOWPULSE |     6.000ns|     4.000ns|       0|           0\r\r
3595   pin" 100 MHz HIGH 50%                     |             |            |            |        |            \r\r
3596 ------------------------------------------------------------------------------------------------------\r\r
3597   TS_clock_generator_0_clock_generator_0_PL | SETUP       |     3.664ns|     1.336ns|       0|           0\r\r
3598   L0_CLK_OUT_3_ = PERIOD TIMEGRP         "c | HOLD        |     0.465ns|            |       0|           0\r\r
3599   lock_generator_0_clock_generator_0_PLL0_C |             |            |            |        |            \r\r
3600   LK_OUT_3_" TS_sys_clk_pin *         2 HIG |             |            |            |        |            \r\r
3601   H 50%                                     |             |            |            |        |            \r\r
3602 ------------------------------------------------------------------------------------------------------\r\r
3603   TS_clock_generator_0_clock_generator_0_PL | SETUP       |     3.842ns|     8.316ns|       0|           0\r\r
3604   L0_CLK_OUT_4_ = PERIOD TIMEGRP         "c | HOLD        |     0.116ns|            |       0|           0\r\r
3605   lock_generator_0_clock_generator_0_PLL0_C |             |            |            |        |            \r\r
3606   LK_OUT_4_" TS_sys_clk_pin *         0.625 |             |            |            |        |            \r\r
3607    HIGH 50%                                 |             |            |            |        |            \r\r
3608 ------------------------------------------------------------------------------------------------------\r\r
3609   NET "fpga_0_Ethernet_MAC_PHY_tx_clk_pin_B | NETSKEW     |     4.455ns|     0.545ns|       0|           0\r\r
3610   UFGP" MAXSKEW = 5 ns                      |             |            |            |        |            \r\r
3611 ------------------------------------------------------------------------------------------------------\r\r
3612   NET "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_B | NETSKEW     |     4.833ns|     0.167ns|       0|           0\r\r
3613   UFGP" MAXSKEW = 5 ns                      |             |            |            |        |            \r\r
3614 ------------------------------------------------------------------------------------------------------\r\r
3615   TS_clock_generator_0_clock_generator_0_PL | MINPERIOD   |     4.900ns|     3.100ns|       0|           0\r\r
3616   L0_CLK_OUT_1_ = PERIOD TIMEGRP         "c |             |            |            |        |            \r\r
3617   lock_generator_0_clock_generator_0_PLL0_C |             |            |            |        |            \r\r
3618   LK_OUT_1_" TS_sys_clk_pin *         1.25  |             |            |            |        |            \r\r
3619   HIGH 50%                                  |             |            |            |        |            \r\r
3620 ------------------------------------------------------------------------------------------------------\r\r
3621   TSTXOUT_Ethernet_MAC = MAXDELAY FROM TIME | MAXDELAY    |     7.423ns|     2.577ns|       0|           0\r\r
3622   GRP "TXCLK_GRP_Ethernet_MAC" TO         T |             |            |            |        |            \r\r
3623   IMEGRP "PADS" 10 ns                       |             |            |            |        |            \r\r
3624 ------------------------------------------------------------------------------------------------------\r\r
3625   NET "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_B | SETUP       |     9.363ns|    13.248ns|       0|           0\r\r
3626   UFGP" PERIOD = 40 ns HIGH 14 ns           | HOLD        |     0.458ns|            |       0|           0\r\r
3627 ------------------------------------------------------------------------------------------------------\r\r
3628   TS_MC_PHY_INIT_DATA_SEL_0 = MAXDELAY FROM | SETUP       |    13.905ns|     6.095ns|       0|           0\r\r
3629    TIMEGRP "TNM_PHY_INIT_DATA_SEL" TO       | HOLD        |     0.812ns|            |       0|           0\r\r
3630      TIMEGRP "TNM_CLK0" TS_MC_CLK * 4       |             |            |            |        |            \r\r
3631 ------------------------------------------------------------------------------------------------------\r\r
3632   TS_MC_PHY_INIT_DATA_SEL_90 = MAXDELAY FRO | SETUP       |    14.527ns|     5.473ns|       0|           0\r\r
3633   M TIMEGRP "TNM_PHY_INIT_DATA_SEL" TO      | HOLD        |     0.262ns|            |       0|           0\r\r
3634       TIMEGRP "TNM_CLK90" TS_MC_CLK * 4     |             |            |            |        |            \r\r
3635 ------------------------------------------------------------------------------------------------------\r\r
3636   TS_MC_GATE_DLY = MAXDELAY FROM TIMEGRP "T | SETUP       |    17.706ns|     2.294ns|       0|           0\r\r
3637   NM_GATE_DLY" TO TIMEGRP "TNM_CLK0"        | HOLD        |     0.056ns|            |       0|           0\r\r
3638     TS_MC_CLK * 4                           |             |            |            |        |            \r\r
3639 ------------------------------------------------------------------------------------------------------\r\r
3640   TS_MC_CAL_RDEN_DLY = MAXDELAY FROM TIMEGR | SETUP       |    18.115ns|     1.885ns|       0|           0\r\r
3641   P "TNM_CAL_RDEN_DLY" TO TIMEGRP         " | HOLD        |     0.231ns|            |       0|           0\r\r
3642   TNM_CLK0" TS_MC_CLK * 4                   |             |            |            |        |            \r\r
3643 ------------------------------------------------------------------------------------------------------\r\r
3644   TS_MC_RDEN_DLY = MAXDELAY FROM TIMEGRP "T | SETUP       |    18.117ns|     1.883ns|       0|           0\r\r
3645   NM_RDEN_DLY" TO TIMEGRP "TNM_CLK0"        | HOLD        |     0.020ns|            |       0|           0\r\r
3646     TS_MC_CLK * 4                           |             |            |            |        |            \r\r
3647 ------------------------------------------------------------------------------------------------------\r\r
3648   NET "fpga_0_SysACE_CompactFlash_SysACE_CL | SETUP       |    26.887ns|     3.113ns|       0|           0\r\r
3649   K_pin_BUFGP/IBUFG" PERIOD = 30 ns         | HOLD        |     0.468ns|            |       0|           0\r\r
3650    HIGH 50%                                 |             |            |            |        |            \r\r
3651 ------------------------------------------------------------------------------------------------------\r\r
3652   NET "fpga_0_Ethernet_MAC_PHY_tx_clk_pin_B | SETUP       |    32.341ns|     7.659ns|       0|           0\r\r
3653   UFGP" PERIOD = 40 ns HIGH 14 ns           | HOLD        |     0.314ns|            |       0|           0\r\r
3654 ------------------------------------------------------------------------------------------------------\r\r
3655   Pin to Pin Skew Constraint                | MAXDELAY    | 2106523.523ns| 2106523.837ns|       0|           0\r\r
3656 ------------------------------------------------------------------------------------------------------\r\r
3657   TS_MC_RDEN_SEL_MUX = MAXDELAY FROM TIMEGR | N/A         |         N/A|         N/A|     N/A|         N/A\r\r
3658   P "TNM_RDEN_SEL_MUX" TO TIMEGRP         " |             |            |            |        |            \r\r
3659   TNM_CLK0" TS_MC_CLK * 4                   |             |            |            |        |            \r\r
3660 ------------------------------------------------------------------------------------------------------\r\r
3661   NET "PCIe_Bridge/Bridge_Clk" PERIOD = 8 n | N/A         |         N/A|         N/A|     N/A|         N/A\r\r
3662   s HIGH 50%                                |             |            |            |        |            \r\r
3663 ------------------------------------------------------------------------------------------------------\r\r
3664 \r\r
3665 \r\r
3666 Derived Constraint Report\r\r
3667 Derived Constraints for TS_MC_CLK\r\r
3668 +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+\r\r
3669 |                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |\r\r
3670 |           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|\r\r
3671 |                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |\r\r
3672 +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+\r\r
3673 |TS_MC_CLK                      |      5.000ns|      3.990ns|      1.524ns|            0|            0|            0|          345|\r\r
3674 | TS_MC_PHY_INIT_DATA_SEL_0     |     20.000ns|      6.095ns|          N/A|            0|            0|           21|            0|\r\r
3675 | TS_MC_PHY_INIT_DATA_SEL_90    |     20.000ns|      5.473ns|          N/A|            0|            0|          274|            0|\r\r
3676 | TS_MC_GATE_DLY                |     20.000ns|      2.294ns|          N/A|            0|            0|           40|            0|\r\r
3677 | TS_MC_RDEN_DLY                |     20.000ns|      1.883ns|          N/A|            0|            0|            5|            0|\r\r
3678 | TS_MC_CAL_RDEN_DLY            |     20.000ns|      1.885ns|          N/A|            0|            0|            5|            0|\r\r
3679 | TS_MC_RDEN_SEL_MUX            |     20.000ns|          N/A|          N/A|            0|            0|            0|            0|\r\r
3680 +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+\r\r
3681 \r\r
3682 Derived Constraints for TS_sys_clk_pin\r\r
3683 +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+\r\r
3684 |                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |\r\r
3685 |           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|\r\r
3686 |                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |\r\r
3687 +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+\r\r
3688 |TS_sys_clk_pin                 |     10.000ns|      4.000ns|      9.965ns|            0|            0|            0|      1090426|\r\r
3689 | TS_clock_generator_0_clock_gen|      8.000ns|      4.917ns|          N/A|            0|            0|          626|            0|\r\r
3690 | erator_0_PLL0_CLK_OUT_0_      |             |             |             |             |             |             |             |\r\r
3691 | TS_clock_generator_0_clock_gen|      8.000ns|      3.100ns|          N/A|            0|            0|            0|            0|\r\r
3692 | erator_0_PLL0_CLK_OUT_1_      |             |             |             |             |             |             |             |\r\r
3693 | TS_clock_generator_0_clock_gen|      8.000ns|      7.972ns|          N/A|            0|            0|      1078756|            0|\r\r
3694 | erator_0_PLL0_CLK_OUT_2_      |             |             |             |             |             |             |             |\r\r
3695 | TS_clock_generator_0_clock_gen|      5.000ns|      1.336ns|          N/A|            0|            0|            2|            0|\r\r
3696 | erator_0_PLL0_CLK_OUT_3_      |             |             |             |             |             |             |             |\r\r
3697 | TS_clock_generator_0_clock_gen|     16.000ns|      8.316ns|          N/A|            0|            0|        11042|            0|\r\r
3698 | erator_0_PLL0_CLK_OUT_4_      |             |             |             |             |             |             |             |\r\r
3699 +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+\r\r
3700 \r\r
3701 All constraints were met.\r\r
3702 INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the \r\r
3703    constraint does not cover any paths or that it has no requested value.\r\r
3704 \r\r
3705 \r\r
3706 Generating Pad Report.\r\r
3707 \r\r
3708 All signals are completely routed.\r\r
3709 \r\r
3710 WARNING:Par:283 - There are 5 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.\r\r
3711 \r\r
3712 Loading device for application Rf_Device from file '5vlx50t.nph' in environment\r\r
3713 c:\devtools\Xilinx\11.1\ISE;C:\devtools\Xilinx\11.1\EDK.\r\r
3714 INFO:ParHelpers:197 - Number of "Exact" mode Directed Routing Constraints: 128\r\r
3715 INFO:ParHelpers:199 - All "EXACT" mode Directed Routing constrained nets successfully routed. The number of constraints\r\r
3716    found: 128, number successful: 128\r\r
3717 Total REAL time to PAR completion: 7 mins 33 secs \r\r
3718 Total CPU time to PAR completion: 7 mins 9 secs \r\r
3719 \r\r
3720 Peak Memory Usage:  705 MB\r\r
3721 \r\r
3722 Placer: Placement generated during map.\r\r
3723 Routing: Completed - No errors found.\r\r
3724 Timing: Completed - No errors found.\r\r
3725 \r\r
3726 Number of error messages: 0\r\r
3727 Number of warning messages: 9\r\r
3728 Number of info messages: 4\r\r
3729 \r\r
3730 Writing design to file system.ncd\r\r
3731 \r\r
3732 \r\r
3733 \r\r
3734 PAR done!\r\r
3735 \r\r
3736 \r\r
3737 \r\r
3738 #----------------------------------------------#\r\r
3739 # Starting program post_par_trce\r\r
3740 # trce -ise ../__xps/ise/system.ise -e 3 -xml system.twx system.ncd system.pcf \r\r
3741 #----------------------------------------------#\r\r
3742 Release 11.2 - Trace  (nt)\r\r
3743 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
3744 \r\r
3745 \r\r
3746 PMSPEC -- Overriding Xilinx file\r\r
3747 <C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
3748 <c:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
3749 Loading device for application Rf_Device from file '5vfx70t.nph' in environment\r\r
3750 c:\devtools\Xilinx\11.1\ISE;C:\devtools\Xilinx\11.1\EDK.\r\r
3751    "system" is an NCD, version 3.2, device xc5vfx70t, package ff1136, speed -1\r\r
3752 WARNING:ConstraintSystem:65 - Constraint <NET "PCIe_Bridge/Bridge_Clk" PERIOD =\r\r
3753    8 ns HIGH 50%;> [system.pcf(78662)] overrides constraint <NET\r\r
3754    "PCIe_Bridge/Bridge_Clk" PERIOD = 8 ns HIGH 50%;> [system.pcf(78661)].\r\r
3755 \r\r
3756 WARNING:Timing:3223 - Timing constraint TS_MC_RDEN_SEL_MUX = MAXDELAY FROM\r\r
3757    TIMEGRP "TNM_RDEN_SEL_MUX" TO TIMEGRP        "TNM_CLK0" TS_MC_CLK * 4;\r\r
3758    ignored during timing analysis.\r\r
3759 INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more\r\r
3760    information, see the TSI report.  Please consult the Xilinx Command Line\r\r
3761    Tools User Guide for information on generating a TSI report.\r\r
3762 --------------------------------------------------------------------------------\r\r
3763 Release 11.2 Trace  (nt)\r\r
3764 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
3765 \r\r
3766 trce -ise ../__xps/ise/system.ise -e 3 -xml system.twx system.ncd system.pcf\r\r
3767 \r\r
3768 \r\r
3769 Design file:              system.ncd\r\r
3770 Physical constraint file: system.pcf\r\r
3771 Device,speed:             xc5vfx70t,-1 (PRODUCTION 1.65 2009-06-01, STEPPING\r\r
3772 level 0)\r\r
3773 Report level:             error report\r\r
3774 --------------------------------------------------------------------------------\r\r
3775 \r\r
3776 INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths\r\r
3777    option. All paths that are not constrained will be reported in the\r\r
3778    unconstrained paths section(s) of the report.\r\r
3779 INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a\r\r
3780    50 Ohm transmission line loading model.  For the details of this model, and\r\r
3781    for more information on accounting for different loading conditions, please\r\r
3782    see the device datasheet.\r\r
3783 \r\r
3784 \r\r
3785 Timing summary:\r\r
3786 ---------------\r\r
3787 \r\r
3788 Timing errors: 0  Score: 0 (Setup/Max: 0, Hold: 0)\r\r
3789 \r\r
3790 Constraints cover 1280410 paths, 18 nets, and 87141 connections\r\r
3791 \r\r
3792 Design statistics:\r\r
3793    Minimum period:  13.248ns (Maximum frequency:  75.483MHz)\r\r
3794    Maximum path delay from/to any node:   7.813ns\r\r
3795    Maximum net delay:   0.805ns\r\r
3796    Maximum net skew:   0.545ns\r\r
3797 \r\r
3798 \r\r
3799 Analysis completed Fri Jul 03 22:25:44 2009\r\r
3800 --------------------------------------------------------------------------------\r\r
3801 \r\r
3802 Generating Report ...\r\r
3803 \r\r
3804 Number of warnings: 2\r\r
3805 Number of info messages: 3\r\r
3806 Total time: 1 mins 34 secs \r\r
3807 \r\r
3808 \r\r
3809 xflow done!\r\r
3810 touch __xps/system_routed\r
3811 xilperl C:/devtools/Xilinx/11.1/EDK/data/fpga_impl/observe_par.pl -error yes implementation/system.par\r
3812 Analyzing implementation/system.par\r\r
3813 *********************************************\r
3814 Running Bitgen..\r
3815 *********************************************\r
3816 cd implementation; bitgen -w -f bitgen.ut system; cd ..\r
3817 Release 11.2 - Bitgen L.46 (nt)\r\r
3818 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
3819 PMSPEC -- Overriding Xilinx file\r\r
3820 <C:/devtools/Xilinx/11.1/EDK/virtex5/data/virtex5.acd> with local file\r\r
3821 <c:/devtools/Xilinx/11.1/ISE/virtex5/data/virtex5.acd>\r\r
3822 Loading device for application Rf_Device from file '5vfx70t.nph' in environment\r\r
3823 c:\devtools\Xilinx\11.1\ISE;C:\devtools\Xilinx\11.1\EDK.\r\r
3824    "system" is an NCD, version 3.2, device xc5vfx70t, package ff1136, speed -1\r\r
3825 Opened constraints file system.pcf.\r\r
3826 \r\r
3827 Fri Jul 03 22:26:27 2009\r\r
3828 \r\r
3829 Running DRC.\r\r
3830 WARNING:PhysDesignRules:1842 - One or more GTXs are being used in this design.\r\r
3831    Evaluate the SelectIO-To-GTX Crosstalk section of the Virtex-5 RocketIO GTX\r\r
3832    Transceiver User Guide to ensure that the design SelectIO usage meets the\r\r
3833    guidelines to minimize the impact on GTX performance. \r\r
3834 WARNING:PhysDesignRules:372 - Gated clock. Clock net\r\r
3835    PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_w\r\r
3836    rapper_i/icdrreset<0> is sourced by a combinatorial pin. This is not good\r\r
3837    design practice. Use the CE pin to control the loading of data into the\r\r
3838    flip-flop.\r\r
3839 WARNING:PhysDesignRules:372 - Gated clock. Clock net\r\r
3840    Ethernet_MAC/Ethernet_MAC/phy_tx_clk_i is sourced by a combinatorial pin.\r\r
3841    This is not good design practice. Use the CE pin to control the loading of\r\r
3842    data into the flip-flop.\r\r
3843 WARNING:PhysDesignRules:367 - The signal\r\r
3844    <PCIe_Bridge/PCIe_Bridge/sig_sb_txrem_n<0>> is incomplete. The signal does\r\r
3845    not drive any load pins in the design.\r\r
3846 WARNING:PhysDesignRules:367 - The signal\r\r
3847    <PCIe_Bridge/PCIe_Bridge/sig_MB_TxREMn<0>> is incomplete. The signal does not\r\r
3848    drive any load pins in the design.\r\r
3849 WARNING:PhysDesignRules:367 - The signal\r\r
3850    <xps_bram_if_cntlr_1_port_BRAM_Addr<31>> is incomplete. The signal does not\r\r
3851    drive any load pins in the design.\r\r
3852 WARNING:PhysDesignRules:367 - The signal\r\r
3853    <xps_bram_if_cntlr_1_port_BRAM_Addr<30>> is incomplete. The signal does not\r\r
3854    drive any load pins in the design.\r\r
3855 WARNING:PhysDesignRules:367 - The signal <PCIe_Bridge/PCIe_Bridge/sig_MB_RxFull>\r\r
3856    is incomplete. The signal does not drive any load pins in the design.\r\r
3857 WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
3858    block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
3859    qs[1].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The Q1 output pin of IFF is not\r\r
3860    used.\r\r
3861 WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
3862    block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
3863    qs[1].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The SR pin is used for the IFF\r\r
3864    Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
3865 WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
3866    block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
3867    qs[4].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The Q1 output pin of IFF is not\r\r
3868    used.\r\r
3869 WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
3870    block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
3871    qs[4].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The SR pin is used for the IFF\r\r
3872    Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
3873 WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
3874    block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
3875    qs[7].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The Q1 output pin of IFF is not\r\r
3876    used.\r\r
3877 WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
3878    block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
3879    qs[7].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The SR pin is used for the IFF\r\r
3880    Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
3881 WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
3882    block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
3883    qs[2].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The Q1 output pin of IFF is not\r\r
3884    used.\r\r
3885 WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
3886    block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
3887    qs[2].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The SR pin is used for the IFF\r\r
3888    Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
3889 WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
3890    block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
3891    qs[5].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The Q1 output pin of IFF is not\r\r
3892    used.\r\r
3893 WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
3894    block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
3895    qs[5].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The SR pin is used for the IFF\r\r
3896    Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
3897 WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
3898    block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
3899    qs[0].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The Q1 output pin of IFF is not\r\r
3900    used.\r\r
3901 WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
3902    block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
3903    qs[0].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The SR pin is used for the IFF\r\r
3904    Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
3905 WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
3906    block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
3907    qs[3].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The Q1 output pin of IFF is not\r\r
3908    used.\r\r
3909 WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
3910    block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
3911    qs[3].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The SR pin is used for the IFF\r\r
3912    Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
3913 WARNING:PhysDesignRules:1269 - Dangling pins on\r\r
3914    block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
3915    qs[6].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The Q1 output pin of IFF is not\r\r
3916    used.\r\r
3917 WARNING:PhysDesignRules:1273 - Dangling pins on\r\r
3918    block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_d\r\r
3919    qs[6].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>.  The SR pin is used for the IFF\r\r
3920    Flip-flop but the SRVAL_Q1 set/reset value is not configured.\r\r
3921 DRC detected 0 errors and 24 warnings.  Please see the previously displayed\r\r
3922 individual error or warning messages for more details.\r\r
3923 Creating bit map...\r\r
3924 Saving bit stream in "system.bit".\r\r
3925 Bitstream generation is complete.\r\r
3926 \r
3927 \r
3928 Done!
3929 \r
3930 At Local date and time: Sat Jul 04 08:21:51 2009
3931  make -f system.make download started...
3932 \r
3933 cp -f /cygdrive/c/devtools/Xilinx/11.1/EDK/sw/lib/ppc440/ppc440_bootloop.elf bootloops/ppc440_0.elf\r
3934 *********************************************\r
3935 Initializing BRAM contents of the bitstream\r
3936 *********************************************\r
3937 bitinit -p xc5vfx70tff1136-1 system.mhs  -pe ppc440_0  bootloops/ppc440_0.elf  \\r
3938 -bt implementation/system.bit -o implementation/download.bit\r
3939 \r\r
3940 bitinit version Xilinx EDK 11.2 Build EDK_LS3.47\r\r
3941 Copyright (c) Xilinx Inc. 2002.\r\r
3942 \r\r
3943 Parsing MHS File system.mhs...\r\r
3944 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
3945    C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
3946    hs line 253 - deprecated core for architecture 'virtex5fx'!\r\r
3947 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
3948    C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
3949    hs line 298 - deprecated core for architecture 'virtex5fx'!\r\r
3950 \r\r
3951 Overriding IP level properties ...\r\r
3952 \r\r
3953 Performing IP level DRCs on properties...\r\r
3954 \r\r
3955 Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...\r\r
3956 Address Map for Processor ppc440_0\r\r
3957   (0b0000000000-0b0011111111) ppc440_0  \r\r
3958   (0000000000-0x0fffffff) DDR2_SDRAM    ppc440_0_PPC440MC\r\r
3959   (0x81000000-0x8100ffff) Ethernet_MAC  plb_v46_0\r\r
3960   (0x81400000-0x8140ffff) Push_Buttons_5Bit     plb_v46_0\r\r
3961   (0x81420000-0x8142ffff) LEDs_Positions        plb_v46_0\r\r
3962   (0x81440000-0x8144ffff) LEDs_8Bit     plb_v46_0\r\r
3963   (0x81460000-0x8146ffff) DIP_Switches_8Bit     plb_v46_0\r\r
3964   (0x81600000-0x8160ffff) IIC_EEPROM    plb_v46_0\r\r
3965   (0x81800000-0x8180ffff) xps_intc_0    plb_v46_0\r\r
3966   (0x83600000-0x8360ffff) SysACE_CompactFlash   plb_v46_0\r\r
3967   (0x84000000-0x8400ffff) RS232_Uart_1  plb_v46_0\r\r
3968   (0x85c00000-0x85c0ffff) PCIe_Bridge   plb_v46_0\r\r
3969   (0xc0000000-0xdfffffff) PCIe_Bridge   plb_v46_0\r\r
3970   (0xe0000000-0xefffffff) PCIe_Bridge   plb_v46_0\r\r
3971   (0xf8000000-0xf80fffff) SRAM  plb_v46_0\r\r
3972   (0xffffe000-0xffffffff) xps_bram_if_cntlr_1   plb_v46_0\r\r
3973 INFO:EDK:1560 - IPNAME:ppc440_virtex5 INSTANCE:ppc440_0 -\r\r
3974    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_\r\r
3975    01_a\data\ppc440_virtex5_v2_1_0.mpd line 175 - tool is overriding PARAMETER\r\r
3976    C_SPLB0_P2P value to 0\r\r
3977 \r\r
3978 Computing clock values...\r\r
3979 INFO:EDK:1432 - Frequency for Top-Level Input Clock\r\r
3980    'fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin' is not specified. Clock DRCs will not be\r\r
3981    performed for IPs connected to that clock port, unless they are connected\r\r
3982    through the clock generator IP. \r\r
3983 \r\r
3984 INFO:EDK:1432 - Frequency for Top-Level Input Clock\r\r
3985    'fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin' is not specified. Clock DRCs will not be\r\r
3986    performed for IPs connected to that clock port, unless they are connected\r\r
3987    through the clock generator IP. \r\r
3988 \r\r
3989 INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
3990    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
3991    ta\plb_v46_v2_1_0.mpd line 70 - tool is overriding PARAMETER\r\r
3992    C_PLBV46_NUM_MASTERS value to 1\r\r
3993 INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
3994    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
3995    ta\plb_v46_v2_1_0.mpd line 71 - tool is overriding PARAMETER\r\r
3996    C_PLBV46_NUM_SLAVES value to 12\r\r
3997 INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
3998    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
3999    ta\plb_v46_v2_1_0.mpd line 72 - tool is overriding PARAMETER\r\r
4000    C_PLBV46_MID_WIDTH value to 1\r\r
4001 INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
4002    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
4003    ta\plb_v46_v2_1_0.mpd line 74 - tool is overriding PARAMETER C_PLBV46_DWIDTH\r\r
4004    value to 128\r\r
4005 INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -\r\r
4006    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_\r\r
4007    v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 75 - tool is overriding\r\r
4008    PARAMETER C_SPLB_DWIDTH value to 128\r\r
4009 INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -\r\r
4010    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_\r\r
4011    v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 76 - tool is overriding\r\r
4012    PARAMETER C_SPLB_NUM_MASTERS value to 1\r\r
4013 INFO:EDK:1560 - IPNAME:xps_bram_if_cntlr INSTANCE:xps_bram_if_cntlr_1 -\r\r
4014    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_\r\r
4015    v1_00_b\data\xps_bram_if_cntlr_v2_1_0.mpd line 80 - tool is overriding\r\r
4016    PARAMETER C_SPLB_SMALLEST_MASTER value to 128\r\r
4017 INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
4018    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\r\r
4019    \data\bram_block_v2_1_0.mpd line 69 - tool is overriding PARAMETER C_MEMSIZE\r\r
4020    value to 0x2000\r\r
4021 INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
4022    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\r\r
4023    \data\bram_block_v2_1_0.mpd line 70 - tool is overriding PARAMETER\r\r
4024    C_PORT_DWIDTH value to 64\r\r
4025 INFO:EDK:1560 - IPNAME:bram_block INSTANCE:xps_bram_if_cntlr_1_bram -\r\r
4026    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\r\r
4027    \data\bram_block_v2_1_0.mpd line 72 - tool is overriding PARAMETER C_NUM_WE\r\r
4028    value to 8\r\r
4029 INFO:EDK:1560 - IPNAME:xps_uartlite INSTANCE:RS232_Uart_1 -\r\r
4030    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_uartlite_v1_01\r\r
4031    _a\data\xps_uartlite_v2_1_0.mpd line 73 - tool is overriding PARAMETER\r\r
4032    C_SPLB_DWIDTH value to 128\r\r
4033 INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:LEDs_8Bit -\r\r
4034    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
4035    ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
4036    value to 128\r\r
4037 INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:LEDs_Positions -\r\r
4038    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
4039    ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
4040    value to 128\r\r
4041 INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:Push_Buttons_5Bit -\r\r
4042    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
4043    ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
4044    value to 128\r\r
4045 INFO:EDK:1560 - IPNAME:xps_gpio INSTANCE:DIP_Switches_8Bit -\r\r
4046    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d\r\r
4047    ata\xps_gpio_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
4048    value to 128\r\r
4049 INFO:EDK:1560 - IPNAME:xps_iic INSTANCE:IIC_EEPROM -\r\r
4050    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_iic_v2_01_a\da\r\r
4051    ta\xps_iic_v2_1_0.mpd line 79 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
4052    value to 128\r\r
4053 INFO:EDK:1560 - IPNAME:xps_mch_emc INSTANCE:SRAM -\r\r
4054    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_\r\r
4055    a\data\xps_mch_emc_v2_1_0.mpd line 82 - tool is overriding PARAMETER\r\r
4056    C_SPLB_DWIDTH value to 128\r\r
4057 INFO:EDK:1560 - IPNAME:xps_mch_emc INSTANCE:SRAM -\r\r
4058    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_\r\r
4059    a\data\xps_mch_emc_v2_1_0.mpd line 84 - tool is overriding PARAMETER\r\r
4060    C_SPLB_SMALLEST_MASTER value to 128\r\r
4061 INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
4062    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
4063    b\data\plbv46_pcie_v2_1_0.mpd line 86 - tool is overriding PARAMETER\r\r
4064    C_MPLB_DWIDTH value to 128\r\r
4065 INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
4066    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
4067    b\data\plbv46_pcie_v2_1_0.mpd line 87 - tool is overriding PARAMETER\r\r
4068    C_MPLB_SMALLEST_SLAVE value to 128\r\r
4069 INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
4070    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
4071    b\data\plbv46_pcie_v2_1_0.mpd line 89 - tool is overriding PARAMETER\r\r
4072    C_SPLB_MID_WIDTH value to 1\r\r
4073 INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
4074    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
4075    b\data\plbv46_pcie_v2_1_0.mpd line 90 - tool is overriding PARAMETER\r\r
4076    C_SPLB_NUM_MASTERS value to 1\r\r
4077 INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
4078    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
4079    b\data\plbv46_pcie_v2_1_0.mpd line 91 - tool is overriding PARAMETER\r\r
4080    C_SPLB_SMALLEST_MASTER value to 128\r\r
4081 INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
4082    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_\r\r
4083    b\data\plbv46_pcie_v2_1_0.mpd line 95 - tool is overriding PARAMETER\r\r
4084    C_SPLB_DWIDTH value to 128\r\r
4085 INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
4086    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
4087    ta\plb_v46_v2_1_0.mpd line 70 - tool is overriding PARAMETER\r\r
4088    C_PLBV46_NUM_MASTERS value to 1\r\r
4089 INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
4090    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
4091    ta\plb_v46_v2_1_0.mpd line 71 - tool is overriding PARAMETER\r\r
4092    C_PLBV46_NUM_SLAVES value to 1\r\r
4093 INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
4094    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
4095    ta\plb_v46_v2_1_0.mpd line 72 - tool is overriding PARAMETER\r\r
4096    C_PLBV46_MID_WIDTH value to 1\r\r
4097 INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
4098    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da\r\r
4099    ta\plb_v46_v2_1_0.mpd line 74 - tool is overriding PARAMETER C_PLBV46_DWIDTH\r\r
4100    value to 128\r\r
4101 INFO:EDK:1560 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
4102    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_ethernetlite_v\r\r
4103    2_01_a\data\xps_ethernetlite_v2_1_0.mpd line 75 - tool is overriding\r\r
4104    PARAMETER C_SPLB_DWIDTH value to 128\r\r
4105 INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -\r\r
4106    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a\r\r
4107    \data\xps_sysace_v2_1_0.mpd line 72 - tool is overriding PARAMETER\r\r
4108    C_SPLB_DWIDTH value to 128\r\r
4109 INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -\r\r
4110    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a\r\r
4111    \data\xps_sysace_v2_1_0.mpd line 74 - tool is overriding PARAMETER\r\r
4112    C_SPLB_MID_WIDTH value to 1\r\r
4113 INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -\r\r
4114    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a\r\r
4115    \data\xps_sysace_v2_1_0.mpd line 75 - tool is overriding PARAMETER\r\r
4116    C_SPLB_NUM_MASTERS value to 1\r\r
4117 INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -\r\r
4118    C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d\r\r
4119    ata\xps_intc_v2_1_0.mpd line 72 - tool is overriding PARAMETER C_SPLB_DWIDTH\r\r
4120    value to 128\r\r
4121 \r\r
4122 Checking platform address map ...\r\r
4123 \r\r
4124 Initializing Memory...\r\r
4125 Running Data2Mem with the following command:\r\r
4126 data2mem -bm "implementation/system_bd" -bt "implementation/system.bit"  -bd\r\r
4127 "bootloops/ppc440_0.elf" tag ppc440_0  -o b implementation/download.bit \r\r
4128 Memory Initialization completed successfully.\r\r
4129 \r\r
4130 *********************************************\r
4131 Downloading Bitstream onto the target board\r
4132 *********************************************\r
4133 impact -batch etc/download.cmd\r
4134 Release 11.2 - iMPACT L.46 (nt)\r\r
4135 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
4136 Preference Table\r\r
4137 Name                 Setting             \r\r
4138 StartupClock         Auto_Correction     \r\r
4139 AutoSignature        False               \r\r
4140 KeepSVF              False               \r\r
4141 ConcurrentMode       False               \r\r
4142 UseHighz             False               \r\r
4143 ConfigOnFailure      Stop                \r\r
4144 UserLevel            Novice              \r\r
4145 MessageLevel         Detailed            \r\r
4146 svfUseTime           false               \r\r
4147 SpiByteSwap          Auto_Correction     \r\r
4148 AutoDetecting cable. Please wait.\r\r
4149 Connecting to cable (Usb Port - USB21).\r\r
4150 Checking cable driver.\r\r
4151  Driver file xusb_xp2.sys found.\r\r
4152  Driver version: src=2301, dest=2301.\r\r
4153  Driver windrvr6.sys version = 9.0.0.0. WinDriver v9.00 Jungo (c) 1997 - 2007 Build Date: Mar 27 2007 X86 32bit SYS\r\r
4154 13:58:07, version = 900.\r\r
4155  Cable PID = 0008.\r\r
4156  Max current requested during enumeration is 300 mA.\r\r
4157 Type = 0x0005.\r\r
4158 write (count, cmdBuffer, dataBuffer) failed C0000004.\r\r
4159  Cable Type = 3, Revision = 0.\r\r
4160  Setting cable speed to 6 MHz.\r\r
4161 Cable connection established.\r\r
4162 Firmware version = 2301.\r\r
4163 File version of c:/devtools/Xilinx/11.1/ISE/data/xusb_xp2.hex = 2401.\r\r
4164 Firmware hex file version = 2401.\r\r
4165 Downloading c:/devtools/Xilinx/11.1/ISE/data/xusb_xp2.hex.\r\r
4166 Downloaded firmware version = 2401.\r\r
4167 PLD file version = 200Dh.\r\r
4168  PLD version = 200Dh.\r\r
4169 Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc5vfx70t, Version : 6\r\r
4170 INFO:iMPACT:1777 - \r
4171    Reading c:/devtools/Xilinx/11.1/ISE/virtex5/data/xc5vfx70t.bsd...\r
4172 \r
4173 ----------------------------------------------------------------------\r\r
4174 ----------------------------------------------------------------------\r\r
4175 '1': : Manufacturer's ID = Xilinx xccace, Version : 0\r\r
4176 INFO:iMPACT:501 - '1': Added Device xc5vfx70t successfully.\r
4177 \r
4178 ----------------------------------------------------------------------\r\r
4179 ----------------------------------------------------------------------\r\r
4180 '2': : Manufacturer's ID = Xilinx xc95144xl, Version : 5\r\r
4181 INFO:iMPACT:1777 - \r
4182    Reading c:/devtools/Xilinx/11.1/ISE/acecf/data/xccace.bsd...\r
4183 INFO:iMPACT:501 - '1': Added Device xccace successfully.\r
4184 \r
4185 ----------------------------------------------------------------------\r\r
4186 ----------------------------------------------------------------------\r\r
4187 '3': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
4188 INFO:iMPACT:1777 - \r
4189    Reading c:/devtools/Xilinx/11.1/ISE/xc9500xl/data/xc95144xl.bsd...\r
4190 INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.\r
4191 \r
4192 ----------------------------------------------------------------------\r\r
4193 ----------------------------------------------------------------------\r\r
4194 '4': : Manufacturer's ID = Xilinx xcf32p, Version : 15\r\r
4195 ----------------------------------------------------------------------\r\r
4196 ----------------------------------------------------------------------\r\r
4197 INFO:iMPACT:1777 - \r
4198    Reading c:/devtools/Xilinx/11.1/ISE/xcfp/data/xcf32p.bsd...\r
4199 INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
4200 INFO:iMPACT:501 - '1': Added Device xcf32p successfully.\r
4201 \r
4202 done.\r\r
4203 Elapsed time =      2 sec.\r\r
4204 Elapsed time =      0 sec.\r\r
4205 '5': Loading file 'implementation/download.bit' ...\r\r
4206 done.\r\r
4207 UserID read from the bitstream file = 0xFFFFFFFF.\r\r
4208 ----------------------------------------------------------------------\r\r
4209 ----------------------------------------------------------------------\r\r
4210 ----------------------------------------------------------------------\r\r
4211 Maximum TCK operating frequency for this device chain: 10000000.\r\r
4212 Validating chain...\r\r
4213 Boundary-scan chain validated successfully.\r\r
4214 5: Device Temperature: Current Reading:   30.69 C, Min. Reading:   27.24 C, Max.\r\r
4215 Reading:   30.69 C\r\r
4216 5: VCCINT Supply: Current Reading:   0.999 V, Min. Reading:   0.999 V, Max.\r\r
4217 Reading:   1.002 V\r\r
4218 5: VCCAUX Supply: Current Reading:   2.505 V, Min. Reading:   2.505 V, Max.\r\r
4219 Reading:   2.508 V\r\r
4220 INFO:iMPACT:501 - '5': Added Device xc5vfx70t successfully.\r
4221 \r
4222 '5': Programming device...\r\r
4223  Match_cycle = 2.\r\r
4224 done.\r\r
4225 '5': Reading status register contents...\r\r
4226 CRC error                                         :         0\r\r
4227 Decryptor security set                            :         0\r\r
4228 DCM locked                                        :         1\r\r
4229 DCI matched                                       :         1\r\r
4230 End of startup signal from Startup block          :         1\r\r
4231 status of GTS_CFG_B                               :         1\r\r
4232 status of GWE                                     :         1\r\r
4233 status of GHIGH                                   :         1\r\r
4234 value of MODE pin M0                              :         1\r\r
4235 value of MODE pin M1                              :         0\r\r
4236 Value of MODE pin M2                              :         1\r\r
4237 Internal signal indicates when housecleaning is completed:         1\r\r
4238 Value driver in from INIT pad                     :         1\r\r
4239 Internal signal indicates that chip is configured :         1\r\r
4240 Value of DONE pin                                 :         1\r\r
4241 Indicates when ID value written does not match chip ID:         0\r\r
4242 Decryptor error Signal                            :         0\r\r
4243 System Monitor Over-Temperature Alarm             :         0\r\r
4244 startup_state[18] CFG startup state machine       :         0\r\r
4245 startup_state[19] CFG startup state machine       :         0\r\r
4246 startup_state[20] CFG startup state machine       :         1\r\r
4247 E-fuse program voltage available                  :         0\r\r
4248 SPI Flash Type[22] Select                         :         1\r\r
4249 SPI Flash Type[23] Select                         :         1\r\r
4250 SPI Flash Type[24] Select                         :         1\r\r
4251 CFG bus width auto detection result               :         0\r\r
4252 CFG bus width auto detection result               :         0\r\r
4253 Reserved                                          :         0\r\r
4254 BPI address wrap around error                     :         0\r\r
4255 IPROG pulsed                                      :         0\r\r
4256 read back crc error                               :         0\r\r
4257 Indicates that efuse logic is busy                :         0\r\r
4258  Match_cycle = 2.\r\r
4259 '5': Programmed successfully.\r\r
4260 Elapsed time =     10 sec.\r\r
4261 ----------------------------------------------------------------------\r\r
4262 ----------------------------------------------------------------------\r\r
4263 ----------------------------------------------------------------------\r\r
4264 ----------------------------------------------------------------------\r\r
4265 ----------------------------------------------------------------------\r\r
4266 ----------------------------------------------------------------------\r\r
4267 ----------------------------------------------------------------------\r\r
4268 ----------------------------------------------------------------------\r\r
4269 INFO:iMPACT:2219 - Status register values:\r
4270 INFO:iMPACT - 0011 1111 1011 1110 0000 1011 1000 0000 \r
4271 INFO:iMPACT:579 - '5': Completed downloading bit file to device.\r
4272 INFO:iMPACT - '5': Programing completed successfully.\r
4273 INFO:iMPACT - '5': Checking done pin....done.\r
4274 \r
4275 \r
4276 \r
4277 Done!
4278 \r
4279 At Local date and time: Sat Jul 04 08:22:29 2009
4280  make -f system.make program started...
4281 \r
4282 *********************************************\r
4283 Creating software libraries...\r
4284 *********************************************\r
4285 libgen -mhs system.mhs -p xc5vfx70tff1136-1  -msg __xps/ise/xmsgprops.lst system.mss\r
4286 libgen\r\r
4287 Xilinx EDK 11.2 Build EDK_LS3.47\r\r
4288 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
4289 \r\r
4290 Command Line: libgen -mhs system.mhs -p xc5vfx70tff1136-1 -msg\r\r
4291 __xps/ise/xmsgprops.lst system.mss \r\r
4292 \r\r
4293 Release 11.2 - psf2Edward EDK_LS3.47 (nt)\r\r
4294 Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.\r\r
4295 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
4296    C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
4297    hs line 253 - deprecated core for architecture 'virtex5fx'!\r\r
4298 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
4299    C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
4300    hs line 298 - deprecated core for architecture 'virtex5fx'!\r\r
4301 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -\r\r
4302    C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
4303    hs line 253 - deprecated core for architecture 'virtex5fx'!\r\r
4304 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -\r\r
4305    C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
4306    hs line 298 - deprecated core for architecture 'virtex5fx'!\r\r
4307 \r\r
4308 Checking platform configuration ...\r\r
4309 IPNAME:plb_v46 INSTANCE:plb_v46_0 -\r\r
4310 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
4311 line 109 - 1 master(s) : 12 slave(s)\r\r
4312 IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -\r\r
4313 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
4314 line 290 - 1 master(s) : 1 slave(s)\r\r
4315 IPNAME:fcb_v20 INSTANCE:ppc440_0_fcb_v20 -\r\r
4316 C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs\r\r
4317 line 394 - 1 master(s) : 1 slave(s)\r\r
4318 \r\r
4319 Checking port drivers...\r\r
4320 WARNING:EDK:2099 - PORT:Peripheral_Reset CONNECTOR:sys_periph_reset -\r\r
4321    C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
4322    hs line 462 - floating connection!\r\r
4323 \r\r
4324 Performing Clock DRCs...\r\r
4325 \r\r
4326 Performing Reset DRCs...\r\r
4327 \r\r
4328 Overriding system level properties...\r\r
4329 \r\r
4330 Running system level update procedures...\r\r
4331 \r\r
4332 Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...\r\r
4333 \r\r
4334 Running system level DRCs...\r\r
4335 \r\r
4336 Performing System level DRCs on properties...\r\r
4337 \r\r
4338 Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...\r\r
4339 WARNING:EDK:411 - pcie -\r\r
4340    C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
4341    ss line 77 - deprecated driver!\r\r
4342 WARNING:EDK:411 - emaclite -\r\r
4343    C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.m\r\r
4344    ss line 83 - deprecated driver!\r\r
4345 INFO:EDK:1740 - List of peripherals connected to processor instance ppc440_0: \r\r
4346   - DDR2_SDRAM\r\r
4347   - DIP_Switches_8Bit\r\r
4348   - Ethernet_MAC\r\r
4349   - IIC_EEPROM\r\r
4350   - LEDs_8Bit\r\r
4351   - LEDs_Positions\r\r
4352   - PCIe_Bridge\r\r
4353   - Push_Buttons_5Bit\r\r
4354   - RS232_Uart_1\r\r
4355   - SRAM\r\r
4356   - SysACE_CompactFlash\r\r
4357   - ppc440_0_apu_fpu_virtex5\r\r
4358   - xps_bram_if_cntlr_1\r\r
4359   - xps_intc_0\r\r
4360 \r\r
4361 -- Generating libraries for processor: ppc440_0 --\r\r
4362 \r\r
4363 \r\r
4364 Staging source files.\r\r
4365 Running DRCs.\r\r
4366 Running generate.\r\r
4367 Running post_generate.\r\r
4368 Running include - 'make -s include "COMPILER=powerpc-eabi-gcc"\r\r
4369 "ARCHIVER=powerpc-eabi-ar" "COMPILER_FLAGS=-mfpu=sp_full -mcpu=440  -O2 -c"\r\r
4370 "EXTRA_COMPILER_FLAGS=-g"'.\r\r
4371 \r\r
4372 Running libs - 'make -s libs "COMPILER=powerpc-eabi-gcc"\r\r
4373 "ARCHIVER=powerpc-eabi-ar" "COMPILER_FLAGS=-mfpu=sp_full -mcpu=440  -O2 -c"\r\r
4374 "EXTRA_COMPILER_FLAGS=-g"'.\r\r
4375 Compiling common\r
4376 powerpc-eabi-ar: creating ../../../lib/libxil.a
4377 \r
4378 Compiling lldma\r
4379 Compiling standalone\r
4380 Compiling gpio\r
4381 Compiling emaclite\r
4382 Compiling iic\r
4383 Compiling pci\r
4384 Compiling uartlite\r
4385 Compiling sysace\r
4386 Compiling intc\r
4387 Compiling cpu_ppc440\r
4388 Running execs_generate.\r\r
4389 powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \\r
4390     -mfpu=sp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \\r
4391 -D GCC_PPC440 -mregnames  \r
4392 powerpc-eabi-size RTOSDemo/executable.elf \r
4393    text    data     bss     dec     hex filename\r
4394   50674     372   86528  137574   21966 RTOSDemo/executable.elf\r
4395 \r
4396 \r
4397 Done!
4398 \r
4399 start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/; exit;"
4400 \r
4401 Writing filter settings....
4402 \r
4403 Done writing filter settings to:
4404         C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
4405 \r
4406 Done writing Tab View settings to:
4407         C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\__xps\system.gui
4408 \r
4409 WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
4410 \r
4411 WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
4412 \r
4413 Generating Block Diagram to Buffer
4414 \r
4415 Generated Block Diagram SVG
4416 \r
4417 At Local date and time: Sun Jul 05 09:36:10 2009
4418  make -f system.make hwclean started...
4419 \r
4420 rm -f implementation/system.ngc\r
4421 rm -f platgen.log\r
4422 rm -f __xps/ise/_xmsgs/platgen.xmsgs\r
4423 rm -f implementation/system.bmm\r
4424 rm -f implementation/system.bit\r
4425 rm -f implementation/system.ncd\r
4426 rm -f implementation/system_bd.bmm \r
4427 rm -f implementation/system_map.ncd \r
4428 rm -f __xps/system_routed\r
4429 rm -rf implementation synthesis xst hdl\r
4430 rm -rf xst.srp system.srp\r
4431 rm -f __xps/ise/_xmsgs/bitinit.xmsgs\r
4432 \r
4433 \r
4434 Done!
4435 \r
4436 At Local date and time: Sun Jul 05 09:36:23 2009
4437  make -f system.make swclean started...
4438 \r
4439 rm -rf ppc440_0/\r
4440 rm -f libgen.log\r
4441 rm -f __xps/ise/_xmsgs/libgen.xmsgs\r
4442 rm -f RTOSDemo/executable.elf \r
4443 \r
4444 \r
4445 Done!
4446 \r
4447 Writing filter settings....
4448 \r
4449 Done writing filter settings to:
4450         C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
4451 \r
4452 Done writing Tab View settings to:
4453         C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\__xps\system.gui
4454 \r