git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/RISC-V-Qemu-sifive_e-Eclipse-GCC/fe310-xsvd.json

   1 {\r
   2   "schemaVersion": "0.2.4",\r
   3   "contentVersion": "0.2.0",\r
   4   "headerVersion": "0.2.0",\r
   5   "device": {\r
   6     "fe310": {\r
   7       "displayName": "Freedom E310-G000",\r
   8       "description": "The FE310-G000 is the first Freedom E300 SoC, and is the industry's first commercially available RISC-V SoC. The FE310-G000 is built around the E31 Core Complex instantiated in the Freedom E300 platform.",\r
   9       "supplier": {\r
  10         "name": "sifive",\r
  11         "id": "1",\r
  12         "displayName": "SiFive",\r
  13         "fullName": "SiFive, Inc.",\r
  14         "contact": "info@sifive.com"\r
  15       },\r
  16       "busWidth": "32",\r
  17       "resetMask": "all",\r
  18       "resetValue": "0x00000000",\r
  19       "access": "rw",\r
  20       "headerGuardPrefix": "SIFIVE_DEVICES_FE310_",\r
  21       "headerTypePrefix": "sifive_fe310_",\r
  22       "headerInterruptPrefix": "sifive_fe310_interrupt_global_",\r
  23       "headerInterruptEnumPrefix": "riscv_interrupts_global_",\r
  24       "revision": "r0p0",\r
  25       "numInterrupts": "51",\r
  26       "priorityBits": "3",\r
  27       "regWidth": "32",\r
  28       "cores": {\r
  29         "e31": {\r
  30           "harts": "1",\r
  31           "isa": "RV32IMAC",\r
  32           "isaVersion": "2.2",\r
  33           "mpu": "pmp",\r
  34           "mmu": "none",\r
  35           "localInterrupts": {\r
  36             "machine_software": {\r
  37               "description": "Machine Software Interrupt",\r
  38               "value": "3"\r
  39             },\r
  40             "machine_timer": {\r
  41               "description": "Machine Timer Interrupt",\r
  42               "value": "7"\r
  43             },\r
  44             "machine_ext": {\r
  45               "description": "Machine External Interrupt",\r
  46               "value": "11"\r
  47             }\r
  48           },\r
  49           "numLocalInterrupts": "0"\r
  50         }\r
  51       },\r
  52       "peripherals": {\r
  53         "clint": {\r
  54           "description": "Core Complex Local Interruptor (CLINT) Peripheral",\r
  55           "baseAddress": "0x02000000",\r
  56           "size": "0x10000",\r
  57           "registers": {\r
  58             "msip": {\r
  59               "description": "MSIP (Machine-mode Software Interrupts) Register per Hart",\r
  60               "addressOffset": "0x0000",\r
  61               "arraySize": "1"\r
  62             }\r
  63           },\r
  64           "clusters": {\r
  65             "mtimecmp": {\r
  66               "description": "Machine Time Compare Registers per Hart",\r
  67               "addressOffset": "0x4000",\r
  68               "arraySize": "1",\r
  69               "registers": {\r
  70                 "low": {\r
  71                   "description": "Machine Compare Register Low",\r
  72                   "addressOffset": "0x0000"\r
  73                 },\r
  74                 "high": {\r
  75                   "description": "Machine Compare Register High",\r
  76                   "addressOffset": "0x0004"\r
  77                 }\r
  78               }\r
  79             },\r
  80             "mtime": {\r
  81               "description": "Machine Time Register",\r
  82               "addressOffset": "0xBFF8",\r
  83               "access": "r",\r
  84               "registers": {\r
  85                 "low": {\r
  86                   "description": "Machine Time Register Low",\r
  87                   "addressOffset": "0x0000"\r
  88                 },\r
  89                 "high": {\r
  90                   "description": "Machine Time Register High",\r
  91                   "addressOffset": "0x0004"\r
  92                 }\r
  93               }\r
  94             }\r
  95           }\r
  96         },\r
  97         "plic": {\r
  98           "description": "Platform-Level Interrupt Controller (PLIC) Peripheral",\r
  99           "baseAddress": "0x0C000000",\r
 100           "size": "0x4000000",\r
 101           "registers": {\r
 102             "priorities": {\r
 103               "arraySize": "52",\r
 104               "description": "Interrupt Priorities Registers; 0 is reserved.",\r
 105               "addressOffset": "0x0000",\r
 106               "fields": {\r
 107                 "value": {\r
 108                   "description": "The priority for a given global interrupt",\r
 109                   "bitOffset": "0",\r
 110                   "bitWidth": "3",\r
 111                   "resetMask": "all",\r
 112                   "resetValue": "0x0"\r
 113                 }\r
 114               }\r
 115             },\r
 116             "pendings": {\r
 117               "arraySize": "2",\r
 118               "description": "Interrupt Pending Bits Registers",\r
 119               "addressOffset": "0x1000",\r
 120               "access": "r"\r
 121             }\r
 122           },\r
 123           "clusters": {\r
 124             "enablestarget0": {\r
 125               "description": "Hart 0 Interrupt Enable Bits",\r
 126               "addressOffset": "0x00002000",\r
 127               "clusters": {\r
 128                 "m": {\r
 129                   "addressOffset": "0x0000",\r
 130                   "description": "Hart 0 M-mode Interrupt Enable Bits",\r
 131                   "registers": {\r
 132                     "enables": {\r
 133                       "arraySize": "2",\r
 134                       "description": "Interrupt Enable Bits Registers",\r
 135                       "addressOffset": "0x0000"\r
 136                     }\r
 137                   }\r
 138                 }\r
 139               }\r
 140             },\r
 141             "target0": {\r
 142               "description": "Hart 0 Interrupt Thresholds",\r
 143               "addressOffset": "0x00200000",\r
 144               "clusters": {\r
 145                 "m": {\r
 146                   "addressOffset": "0x0000",\r
 147                   "description": "Hart 0 M-Mode Interrupt Threshold",\r
 148                   "registers": {\r
 149                     "threshold": {\r
 150                       "description": "The Priority Threshold Register",\r
 151                       "addressOffset": "0x0000",\r
 152                       "fields": {\r
 153                         "value": {\r
 154                           "description": "The priority threshold value",\r
 155                           "bitOffset": "0",\r
 156                           "bitWidth": "3",\r
 157                           "resetMask": "all",\r
 158                           "resetValue": "0x0"\r
 159                         }\r
 160                       }\r
 161                     },\r
 162                     "claimcomplete": {\r
 163                       "description": "The Interrupt Claim/Completion Register",\r
 164                       "addressOffset": "0x0004"\r
 165                     }\r
 166                   }\r
 167                 }\r
 168               }\r
 169             }\r
 170           }\r
 171         },\r
 172         "wdog": {\r
 173           "description": "Watchdog Timer (WDT), part of Always-On Domain",\r
 174           "baseAddress": "0x10000000",\r
 175           "size": "0x0040",\r
 176           "resetMask": "none",\r
 177           "registers": {\r
 178             "cfg": {\r
 179               "description": "Watchdog Configuration Register",\r
 180               "addressOffset": "0x0000",\r
 181               "fields": {\r
 182                 "scale": {\r
 183                   "description": "Watchdog counter scale",\r
 184                   "bitOffset": "0",\r
 185                   "bitWidth": "4"\r
 186                 },\r
 187                 "rsten": {\r
 188                   "description": "Watchdog full reset enable",\r
 189                   "bitOffset": "8",\r
 190                   "bitWidth": "1",\r
 191                   "resetMask": "all",\r
 192                   "resetValue": "0x0"\r
 193                 },\r
 194                 "zerocmp": {\r
 195                   "description": "Watchdog zero on comparator",\r
 196                   "bitOffset": "9",\r
 197                   "bitWidth": "1"\r
 198                 },\r
 199                 "enalways": {\r
 200                   "description": "Watchdog enable counter always",\r
 201                   "bitOffset": "12",\r
 202                   "bitWidth": "1",\r
 203                   "resetMask": "all",\r
 204                   "resetValue": "0x0"\r
 205                 },\r
 206                 "encoreawake": {\r
 207                   "description": "Watchdog counter only when awake",\r
 208                   "bitOffset": "13",\r
 209                   "bitWidth": "1",\r
 210                   "resetMask": "all",\r
 211                   "resetValue": "0x0"\r
 212                 },\r
 213                 "cmpip": {\r
 214                   "description": "Watchdog interrupt pending",\r
 215                   "bitOffset": "28",\r
 216                   "bitWidth": "1"\r
 217                 }\r
 218               }\r
 219             },\r
 220             "count": {\r
 221               "description": "Watchdog Count Register",\r
 222               "addressOffset": "0x0008"\r
 223             },\r
 224             "scale": {\r
 225               "description": "Watchdog Scale Register",\r
 226               "addressOffset": "0x0010",\r
 227               "fields": {\r
 228                 "value": {\r
 229                   "description": "Watchdog scale value",\r
 230                   "bitOffset": "0",\r
 231                   "bitWidth": "16"\r
 232                 }\r
 233               }\r
 234             },\r
 235             "feed": {\r
 236               "description": "Watchdog Feed Address Register",\r
 237               "addressOffset": "0x0018"\r
 238             },\r
 239             "key": {\r
 240               "description": "Watchdog Key Register",\r
 241               "addressOffset": "0x001C"\r
 242             },\r
 243             "cmp": {\r
 244               "description": "Watchdog Compare Register",\r
 245               "addressOffset": "0x0020",\r
 246               "fields": {\r
 247                 "value": {\r
 248                   "description": "Watchdog compare value",\r
 249                   "bitOffset": "0",\r
 250                   "bitWidth": "16"\r
 251                 }\r
 252               }\r
 253             }\r
 254           },\r
 255           "interrupts": {\r
 256             "wdogcmp": {\r
 257               "description": "Watchdog Compare Interrupt",\r
 258               "value": "1"\r
 259             }\r
 260           }\r
 261         },\r
 262         "rtc": {\r
 263           "description": "Real-Time Clock (RTC), part of Always-On Domain",\r
 264           "baseAddress": "0x10000040",\r
 265           "size": "0x0030",\r
 266           "resetMask": "none",\r
 267           "registers": {\r
 268             "cfg": {\r
 269               "description": "RTC Configuration Register",\r
 270               "addressOffset": "0x0000",\r
 271               "fields": {\r
 272                 "scale": {\r
 273                   "description": "RTC clock rate scale",\r
 274                   "bitOffset": "0",\r
 275                   "bitWidth": "4"\r
 276                 },\r
 277                 "enalways": {\r
 278                   "description": "RTC counter enable",\r
 279                   "bitOffset": "12",\r
 280                   "bitWidth": "1",\r
 281                   "resetMask": "all",\r
 282                   "resetValue": "0x0"\r
 283                 },\r
 284                 "cmpip": {\r
 285                   "description": "RTC comparator interrupt pending",\r
 286                   "bitOffset": "28",\r
 287                   "bitWidth": "1",\r
 288                   "access": "r"\r
 289                 }\r
 290               }\r
 291             },\r
 292             "low": {\r
 293               "description": "RTC Counter Register Low",\r
 294               "addressOffset": "0x0008"\r
 295             },\r
 296             "high": {\r
 297               "description": "RTC Counter Register High",\r
 298               "addressOffset": "0x000C",\r
 299               "fields": {\r
 300                 "value": {\r
 301                   "description": "RTC counter register, high bits",\r
 302                   "bitOffset": "0",\r
 303                   "bitWidth": "16"\r
 304                 }\r
 305               }\r
 306             },\r
 307             "scale": {\r
 308               "description": "RTC Scale Register",\r
 309               "addressOffset": "0x0010"\r
 310             },\r
 311             "cmp": {\r
 312               "description": "RTC Compare Register",\r
 313               "addressOffset": "0x0020"\r
 314             }\r
 315           },\r
 316           "interrupts": {\r
 317             "rtccmp": {\r
 318               "description": "RTC Compare Interrupt",\r
 319               "value": "2"\r
 320             }\r
 321           }\r
 322         },\r
 323         "pmu": {\r
 324           "description": "Power-Management Unit (PMU), part of Always-On Domain",\r
 325           "baseAddress": "0x10000100",\r
 326           "size": "0x0050",\r
 327           "resetMask": "none",\r
 328           "registers": {\r
 329             "wakeupi": {\r
 330               "description": "Wakeup program instruction Registers",\r
 331               "addressOffset": "0x0000",\r
 332               "arraySize": "8"\r
 333             },\r
 334             "sleepi": {\r
 335               "description": "Sleep Program Instruction Registers",\r
 336               "addressOffset": "0x0020",\r
 337               "arraySize": "8"\r
 338             },\r
 339             "ie": {\r
 340               "description": "PMU Interrupt Enables Register",\r
 341               "addressOffset": "0x0040",\r
 342               "fields": {\r
 343                 "rtc": {\r
 344                   "description": "RTC Comparator active",\r
 345                   "bitOffset": "1",\r
 346                   "bitWidth": "1"\r
 347                 },\r
 348                 "dwakeup": {\r
 349                   "description": "dwakeup_n pin active",\r
 350                   "bitOffset": "2",\r
 351                   "bitWidth": "1"\r
 352                 }\r
 353               }\r
 354             },\r
 355             "cause": {\r
 356               "description": "PMU Wakeup Cause Register",\r
 357               "addressOffset": "0x0044",\r
 358               "fields": {\r
 359                 "wakeupcause": {\r
 360                   "description": "Wakeup cause",\r
 361                   "bitOffset": "0",\r
 362                   "bitWidth": "2",\r
 363                   "access": "r",\r
 364                   "enumerations": {\r
 365                     "wakeupcause-enum": {\r
 366                       "description": "Wakeup Cause Values Enumeration",\r
 367                       "values": {\r
 368                         "0": {\r
 369                           "displayName": "reset",\r
 370                           "description": "Reset Wakeup"\r
 371                         },\r
 372                         "1": {\r
 373                           "displayName": "rtc",\r
 374                           "description": "RTC Wakeup"\r
 375                         },\r
 376                         "2": {\r
 377                           "displayName": "dwakeup",\r
 378                           "description": "Digital input Wakeup"\r
 379                         },\r
 380                         "*": {\r
 381                           "displayName": "undefined"\r
 382                         }\r
 383                       }\r
 384                     }\r
 385                   }\r
 386                 },\r
 387                 "resetcause": {\r
 388                   "description": "Reset cause",\r
 389                   "bitOffset": "8",\r
 390                   "bitWidth": "2",\r
 391                   "access": "r",\r
 392                   "enumerations": {\r
 393                     "resetcause-enum": {\r
 394                       "description": "Reset Cause Values Enumeration",\r
 395                       "values": {\r
 396                         "1": {\r
 397                           "displayName": "external",\r
 398                           "description": "External reset"\r
 399                         },\r
 400                         "2": {\r
 401                           "displayName": "watchdog",\r
 402                           "description": "Watchdog timer reset"\r
 403                         },\r
 404                         "*": {\r
 405                           "displayName": "undefined"\r
 406                         }\r
 407                       }\r
 408                     }\r
 409                   }\r
 410                 }\r
 411               }\r
 412             },\r
 413             "sleep": {\r
 414               "description": "PMU Initiate Sleep Sequence Register",\r
 415               "addressOffset": "0x0048"\r
 416             },\r
 417             "key": {\r
 418               "description": "PMU Key Register",\r
 419               "addressOffset": "0x004C"\r
 420             }\r
 421           }\r
 422         },\r
 423         "aon": {\r
 424           "description": "Always-On (AON) Domain",\r
 425           "baseAddress": "0x10000070",\r
 426           "size": "0x0090",\r
 427           "resetMask": "none",\r
 428           "registers": {\r
 429             "lfrosccfg": {\r
 430               "description": "Internal Programmable Low-Frequency Ring Oscillator Register",\r
 431               "addressOffset": "0x0000",\r
 432               "fields": {\r
 433                 "div": {\r
 434                   "description": "LFROSC divider",\r
 435                   "bitOffset": "0",\r
 436                   "bitWidth": "6",\r
 437                   "resetMask": "all",\r
 438                   "resetValue": "0x04"\r
 439                 },\r
 440                 "trim": {\r
 441                   "description": "LFROSC trim value",\r
 442                   "bitOffset": "16",\r
 443                   "bitWidth": "5",\r
 444                   "resetMask": "all",\r
 445                   "resetValue": "0x10"\r
 446                 },\r
 447                 "en": {\r
 448                   "description": "LFROSC enable",\r
 449                   "bitOffset": "30",\r
 450                   "bitWidth": "1",\r
 451                   "resetMask": "all",\r
 452                   "resetValue": "0x1"\r
 453                 },\r
 454                 "rdy": {\r
 455                   "description": "LFROSC ready",\r
 456                   "bitOffset": "31",\r
 457                   "bitWidth": "1",\r
 458                   "access": "r"\r
 459                 }\r
 460               }\r
 461             },\r
 462             "backup": {\r
 463               "description": "Backup Registers",\r
 464               "addressOffset": "0x0010",\r
 465               "arraySize": "32"\r
 466             }\r
 467           }\r
 468         },\r
 469         "prci": {\r
 470           "description": "Power, Reset, Clock, Interrupt (PRCI) Peripheral",\r
 471           "baseAddress": "0x10008000",\r
 472           "size": "0x8000",\r
 473           "registers": {\r
 474             "hfrosccfg": {\r
 475               "description": "Internal Trimmable Programmable 72 MHz Oscillator Register",\r
 476               "addressOffset": "0x0000",\r
 477               "fields": {\r
 478                 "div": {\r
 479                   "description": "HFROSC divider",\r
 480                   "bitOffset": "0",\r
 481                   "bitWidth": "6",\r
 482                   "resetMask": "all",\r
 483                   "resetValue": "0x04"\r
 484                 },\r
 485                 "trim": {\r
 486                   "description": "HFROSC trim value",\r
 487                   "bitOffset": "16",\r
 488                   "bitWidth": "5",\r
 489                   "resetMask": "all",\r
 490                   "resetValue": "0x10"\r
 491                 },\r
 492                 "en": {\r
 493                   "description": "HFROSC enable",\r
 494                   "bitOffset": "30",\r
 495                   "bitWidth": "1",\r
 496                   "resetMask": "all",\r
 497                   "resetValue": "0x1"\r
 498                 },\r
 499                 "rdy": {\r
 500                   "description": "HFROSC ready",\r
 501                   "bitOffset": "31",\r
 502                   "bitWidth": "1",\r
 503                   "access": "r"\r
 504                 }\r
 505               }\r
 506             },\r
 507             "hfxosccfg": {\r
 508               "description": "External 16 MHz Crystal Oscillator Register",\r
 509               "addressOffset": "0x0004",\r
 510               "fields": {\r
 511                 "en": {\r
 512                   "description": "HFXOSC enable",\r
 513                   "bitOffset": "30",\r
 514                   "bitWidth": "1",\r
 515                   "resetMask": "all",\r
 516                   "resetValue": "0x1"\r
 517                 },\r
 518                 "rdy": {\r
 519                   "description": "HFXOSC ready",\r
 520                   "bitOffset": "31",\r
 521                   "bitWidth": "1",\r
 522                   "access": "r"\r
 523                 }\r
 524               }\r
 525             },\r
 526             "pllcfg": {\r
 527               "description": "Internal High-Frequency PLL (HFPLL) Register",\r
 528               "addressOffset": "0x0008",\r
 529               "fields": {\r
 530                 "r": {\r
 531                   "description": "PLL R input divider value",\r
 532                   "bitOffset": "0",\r
 533                   "bitWidth": "3",\r
 534                   "resetMask": "all",\r
 535                   "resetValue": "0x1",\r
 536                   "enumerations": {\r
 537                     "pllr-enum": {\r
 538                       "description": "Reference Clock R Divide Ratio Enumeration",\r
 539                       "values": {\r
 540                         "0": {\r
 541                           "displayName": "/1",\r
 542                           "headerName": "div1",\r
 543                           "description": "Unchanged"\r
 544                         },\r
 545                         "1": {\r
 546                           "displayName": "/2",\r
 547                           "headerName": "div2",\r
 548                           "description": "Divided by 2"\r
 549                         },\r
 550                         "2": {\r
 551                           "displayName": "/3",\r
 552                           "headerName": "div3",\r
 553                           "description": "Divided by 3"\r
 554                         },\r
 555                         "3": {\r
 556                           "displayName": "/4",\r
 557                           "headerName": "div4",\r
 558                           "description": "Divided by 4"\r
 559                         }\r
 560                       }\r
 561                     }\r
 562                   }\r
 563                 },\r
 564                 "f": {\r
 565                   "description": "PLL F multiplier value",\r
 566                   "bitOffset": "4",\r
 567                   "bitWidth": "6",\r
 568                   "resetMask": "all",\r
 569                   "resetValue": "0x1F",\r
 570                   "enumerations": {\r
 571                     "pllf-enum": {\r
 572                       "description": "Reference Clock F Multiplier Ratio Enumeration",\r
 573                       "values": {\r
 574                         "0": {\r
 575                           "displayName": "*2",\r
 576                           "headerName": "mul2",\r
 577                           "description": "Multiplied by 2"\r
 578                         },\r
 579                         "1": {\r
 580                           "displayName": "*4",\r
 581                           "headerName": "mul4",\r
 582                           "description": "Multiplied by 4"\r
 583                         },\r
 584                         "2": {\r
 585                           "displayName": "*6",\r
 586                           "headerName": "mul6",\r
 587                           "description": "Multiplied by 6"\r
 588                         },\r
 589                         "3": {\r
 590                           "displayName": "*8",\r
 591                           "headerName": "mul8",\r
 592                           "description": "Multiplied by 8"\r
 593                         },\r
 594                         "4": {\r
 595                           "displayName": "*10",\r
 596                           "headerName": "mul10",\r
 597                           "description": "Multiplied by 10"\r
 598                         },\r
 599                         "5": {\r
 600                           "displayName": "*12",\r
 601                           "headerName": "mul12",\r
 602                           "description": "Multiplied by 12"\r
 603                         },\r
 604                         "6": {\r
 605                           "displayName": "*14",\r
 606                           "headerName": "mul14",\r
 607                           "description": "Multiplied by 14"\r
 608                         },\r
 609                         "7": {\r
 610                           "displayName": "*16",\r
 611                           "headerName": "mul16",\r
 612                           "description": "Multiplied by 16"\r
 613                         },\r
 614                         "8": {\r
 615                           "displayName": "*18",\r
 616                           "headerName": "mul18",\r
 617                           "description": "Multiplied by 18"\r
 618                         },\r
 619                         "9": {\r
 620                           "displayName": "*20",\r
 621                           "headerName": "mul20",\r
 622                           "description": "Multiplied by 20"\r
 623                         },\r
 624                         "10": {\r
 625                           "displayName": "*22",\r
 626                           "headerName": "mul22",\r
 627                           "description": "Multiplied by 22"\r
 628                         },\r
 629                         "11": {\r
 630                           "displayName": "*24",\r
 631                           "headerName": "mul24",\r
 632                           "description": "Multiplied by 24"\r
 633                         },\r
 634                         "12": {\r
 635                           "displayName": "*26",\r
 636                           "headerName": "mul26",\r
 637                           "description": "Multiplied by 26"\r
 638                         },\r
 639                         "13": {\r
 640                           "displayName": "*28",\r
 641                           "headerName": "mul28",\r
 642                           "description": "Multiplied by 28"\r
 643                         },\r
 644                         "14": {\r
 645                           "displayName": "*30",\r
 646                           "headerName": "mul30",\r
 647                           "description": "Multiplied by 30"\r
 648                         },\r
 649                         "15": {\r
 650                           "displayName": "*32",\r
 651                           "headerName": "mul32",\r
 652                           "description": "Multiplied by 32"\r
 653                         },\r
 654                         "16": {\r
 655                           "displayName": "*34",\r
 656                           "headerName": "mul34",\r
 657                           "description": "Multiplied by 34"\r
 658                         },\r
 659                         "17": {\r
 660                           "displayName": "*36",\r
 661                           "headerName": "mul36",\r
 662                           "description": "Multiplied by 36"\r
 663                         },\r
 664                         "18": {\r
 665                           "displayName": "*38",\r
 666                           "headerName": "mul38",\r
 667                           "description": "Multiplied by 38"\r
 668                         },\r
 669                         "19": {\r
 670                           "displayName": "*40",\r
 671                           "headerName": "mul40",\r
 672                           "description": "Multiplied by 40"\r
 673                         },\r
 674                         "20": {\r
 675                           "displayName": "*42",\r
 676                           "headerName": "mul42",\r
 677                           "description": "Multiplied by 42"\r
 678                         },\r
 679                         "21": {\r
 680                           "displayName": "*44",\r
 681                           "headerName": "mul44",\r
 682                           "description": "Multiplied by 44"\r
 683                         },\r
 684                         "22": {\r
 685                           "displayName": "*46",\r
 686                           "headerName": "mul46",\r
 687                           "description": "Multiplied by 46"\r
 688                         },\r
 689                         "23": {\r
 690                           "displayName": "*48",\r
 691                           "headerName": "mul48",\r
 692                           "description": "Multiplied by 48"\r
 693                         },\r
 694                         "24": {\r
 695                           "displayName": "*50",\r
 696                           "headerName": "mul50",\r
 697                           "description": "Multiplied by 50"\r
 698                         },\r
 699                         "25": {\r
 700                           "displayName": "*52",\r
 701                           "headerName": "mul52",\r
 702                           "description": "Multiplied by 52"\r
 703                         },\r
 704                         "26": {\r
 705                           "displayName": "*54",\r
 706                           "headerName": "mul54",\r
 707                           "description": "Multiplied by 54"\r
 708                         },\r
 709                         "27": {\r
 710                           "displayName": "*56",\r
 711                           "headerName": "mul56",\r
 712                           "description": "Multiplied by 56"\r
 713                         },\r
 714                         "28": {\r
 715                           "displayName": "*58",\r
 716                           "headerName": "mul58",\r
 717                           "description": "Multiplied by 58"\r
 718                         },\r
 719                         "29": {\r
 720                           "displayName": "*60",\r
 721                           "headerName": "mul60",\r
 722                           "description": "Multiplied by 60"\r
 723                         },\r
 724                         "30": {\r
 725                           "displayName": "*62",\r
 726                           "headerName": "mul62",\r
 727                           "description": "Multiplied by 62"\r
 728                         },\r
 729                         "31": {\r
 730                           "displayName": "*64",\r
 731                           "headerName": "mul64",\r
 732                           "description": "Multiplied by 64"\r
 733                         },\r
 734                         "32": {\r
 735                           "displayName": "*66",\r
 736                           "headerName": "mul66",\r
 737                           "description": "Multiplied by 66"\r
 738                         },\r
 739                         "33": {\r
 740                           "displayName": "*68",\r
 741                           "headerName": "mul68",\r
 742                           "description": "Multiplied by 68"\r
 743                         },\r
 744                         "34": {\r
 745                           "displayName": "*70",\r
 746                           "headerName": "mul70",\r
 747                           "description": "Multiplied by 70"\r
 748                         },\r
 749                         "35": {\r
 750                           "displayName": "*72",\r
 751                           "headerName": "mul72",\r
 752                           "description": "Multiplied by 72"\r
 753                         },\r
 754                         "36": {\r
 755                           "displayName": "*74",\r
 756                           "headerName": "mul74",\r
 757                           "description": "Multiplied by 74"\r
 758                         },\r
 759                         "37": {\r
 760                           "displayName": "*76",\r
 761                           "headerName": "mul76",\r
 762                           "description": "Multiplied by 76"\r
 763                         },\r
 764                         "38": {\r
 765                           "displayName": "*78",\r
 766                           "headerName": "mul78",\r
 767                           "description": "Multiplied by 78"\r
 768                         },\r
 769                         "39": {\r
 770                           "displayName": "*80",\r
 771                           "headerName": "mul80",\r
 772                           "description": "Multiplied by 80"\r
 773                         },\r
 774                         "40": {\r
 775                           "displayName": "*82",\r
 776                           "headerName": "mul82",\r
 777                           "description": "Multiplied by 82"\r
 778                         },\r
 779                         "41": {\r
 780                           "displayName": "*84",\r
 781                           "headerName": "mul84",\r
 782                           "description": "Multiplied by 84"\r
 783                         },\r
 784                         "42": {\r
 785                           "displayName": "*86",\r
 786                           "headerName": "mul86",\r
 787                           "description": "Multiplied by 86"\r
 788                         },\r
 789                         "43": {\r
 790                           "displayName": "*88",\r
 791                           "headerName": "mul88",\r
 792                           "description": "Multiplied by 88"\r
 793                         },\r
 794                         "44": {\r
 795                           "displayName": "*90",\r
 796                           "headerName": "mul90",\r
 797                           "description": "Multiplied by 90"\r
 798                         },\r
 799                         "45": {\r
 800                           "displayName": "*92",\r
 801                           "headerName": "mul92",\r
 802                           "description": "Multiplied by 92"\r
 803                         },\r
 804                         "46": {\r
 805                           "displayName": "*94",\r
 806                           "headerName": "mul94",\r
 807                           "description": "Multiplied by 94"\r
 808                         },\r
 809                         "47": {\r
 810                           "displayName": "*96",\r
 811                           "headerName": "mul96",\r
 812                           "description": "Multiplied by 96"\r
 813                         },\r
 814                         "48": {\r
 815                           "displayName": "*98",\r
 816                           "headerName": "mul98",\r
 817                           "description": "Multiplied by 98"\r
 818                         },\r
 819                         "49": {\r
 820                           "displayName": "*100",\r
 821                           "headerName": "mul100",\r
 822                           "description": "Multiplied by 100"\r
 823                         },\r
 824                         "50": {\r
 825                           "displayName": "*102",\r
 826                           "headerName": "mul102",\r
 827                           "description": "Multiplied by 102"\r
 828                         },\r
 829                         "51": {\r
 830                           "displayName": "*104",\r
 831                           "headerName": "mul104",\r
 832                           "description": "Multiplied by 104"\r
 833                         },\r
 834                         "52": {\r
 835                           "displayName": "*106",\r
 836                           "headerName": "mul106",\r
 837                           "description": "Multiplied by 106"\r
 838                         },\r
 839                         "53": {\r
 840                           "displayName": "*108",\r
 841                           "headerName": "mul108",\r
 842                           "description": "Multiplied by 108"\r
 843                         },\r
 844                         "54": {\r
 845                           "displayName": "*110",\r
 846                           "headerName": "mul110",\r
 847                           "description": "Multiplied by 110"\r
 848                         },\r
 849                         "55": {\r
 850                           "displayName": "*112",\r
 851                           "headerName": "mul112",\r
 852                           "description": "Multiplied by 112"\r
 853                         },\r
 854                         "56": {\r
 855                           "displayName": "*114",\r
 856                           "headerName": "mul114",\r
 857                           "description": "Multiplied by 114"\r
 858                         },\r
 859                         "57": {\r
 860                           "displayName": "*116",\r
 861                           "headerName": "mul116",\r
 862                           "description": "Multiplied by 116"\r
 863                         },\r
 864                         "58": {\r
 865                           "displayName": "*118",\r
 866                           "headerName": "mul118",\r
 867                           "description": "Multiplied by 118"\r
 868                         },\r
 869                         "59": {\r
 870                           "displayName": "*120",\r
 871                           "headerName": "mul120",\r
 872                           "description": "Multiplied by 120"\r
 873                         },\r
 874                         "60": {\r
 875                           "displayName": "*122",\r
 876                           "headerName": "mul122",\r
 877                           "description": "Multiplied by 122"\r
 878                         },\r
 879                         "61": {\r
 880                           "displayName": "*124",\r
 881                           "headerName": "mul124",\r
 882                           "description": "Multiplied by 124"\r
 883                         },\r
 884                         "62": {\r
 885                           "displayName": "*126",\r
 886                           "headerName": "mul126",\r
 887                           "description": "Multiplied by 126"\r
 888                         },\r
 889                         "63": {\r
 890                           "displayName": "*128",\r
 891                           "headerName": "mul128",\r
 892                           "description": "Multiplied by 128"\r
 893                         }\r
 894                       }\r
 895                     }\r
 896                   }\r
 897                 },\r
 898                 "q": {\r
 899                   "description": "PLL Q output divider value",\r
 900                   "bitOffset": "10",\r
 901                   "bitWidth": "2",\r
 902                   "resetMask": "all",\r
 903                   "resetValue": "0x3",\r
 904                   "enumerations": {\r
 905                     "pllq-enum": {\r
 906                       "description": "Reference Clock Q Divide Ratio Enumeration",\r
 907                       "values": {\r
 908                         "*": {\r
 909                           "displayName": "n/a",\r
 910                           "description": "Not supported"\r
 911                         },\r
 912                         "1": {\r
 913                           "displayName": "/2",\r
 914                           "headerName": "div2",\r
 915                           "description": "Divided by 2"\r
 916                         },\r
 917                         "2": {\r
 918                           "displayName": "/4",\r
 919                           "headerName": "div4",\r
 920                           "description": "Divided by 4"\r
 921                         },\r
 922                         "3": {\r
 923                           "displayName": "/8",\r
 924                           "headerName": "div8",\r
 925                           "description": "Divided by 8"\r
 926                         }\r
 927                       }\r
 928                     }\r
 929                   }\r
 930                 },\r
 931                 "sel": {\r
 932                   "description": "PLL select",\r
 933                   "bitOffset": "16",\r
 934                   "bitWidth": "1",\r
 935                   "resetMask": "all",\r
 936                   "resetValue": "0x0"\r
 937                 },\r
 938                 "refsel": {\r
 939                   "description": "PLL reference select",\r
 940                   "bitOffset": "17",\r
 941                   "bitWidth": "1",\r
 942                   "resetMask": "all",\r
 943                   "resetValue": "0x1"\r
 944                 },\r
 945                 "bypass": {\r
 946                   "description": "PLL bypass",\r
 947                   "bitOffset": "18",\r
 948                   "bitWidth": "1",\r
 949                   "resetMask": "all",\r
 950                   "resetValue": "0x1"\r
 951                 },\r
 952                 "lock": {\r
 953                   "description": "PLL lock indicator",\r
 954                   "bitOffset": "31",\r
 955                   "bitWidth": "1",\r
 956                   "access": "r"\r
 957                 }\r
 958               }\r
 959             },\r
 960             "plloutdiv": {\r
 961               "description": "PLL Output Divider",\r
 962               "addressOffset": "0x000C"\r
 963             }\r
 964           }\r
 965         },\r
 966         "otp": {\r
 967           "description": "One-Time Programmable Memory (OTP) Peripheral",\r
 968           "baseAddress": "0x10010000",\r
 969           "size": "0x1000",\r
 970           "registers": {\r
 971             "lock": {\r
 972               "description": "Programmed-I/O Lock Register",\r
 973               "addressOffset": "0x0000"\r
 974             },\r
 975             "ck": {\r
 976               "description": "Device Clock Signal Register",\r
 977               "addressOffset": "0x0004"\r
 978             },\r
 979             "oe": {\r
 980               "description": "Device Output-Enable Signal Register",\r
 981               "addressOffset": "0x0008"\r
 982             },\r
 983             "sel": {\r
 984               "description": "Device Chip-Select Signal Register",\r
 985               "addressOffset": "0x000C"\r
 986             },\r
 987             "we": {\r
 988               "description": "Device Write-Enable Signal Register",\r
 989               "addressOffset": "0x0010"\r
 990             },\r
 991             "mr": {\r
 992               "description": "Device Mode Register",\r
 993               "addressOffset": "0x0014"\r
 994             },\r
 995             "mrr": {\r
 996               "description": "Read-Voltage Regulator Control Register",\r
 997               "addressOffset": "0x0018"\r
 998             },\r
 999             "mpp": {\r
1000               "description": "Write-Voltage Charge Pump Control Register",\r
1001               "addressOffset": "0x001C"\r
1002             },\r
1003             "vrren": {\r
1004               "description": "Read-Voltage Enable Register",\r
1005               "addressOffset": "0x0020"\r
1006             },\r
1007             "vppen": {\r
1008               "description": "Write-Voltage Enable Register",\r
1009               "addressOffset": "0x0024"\r
1010             },\r
1011             "a": {\r
1012               "description": "Device Address Register",\r
1013               "addressOffset": "0x0028"\r
1014             },\r
1015             "d": {\r
1016               "description": "Device Data Input Register",\r
1017               "addressOffset": "0x002C"\r
1018             },\r
1019             "q": {\r
1020               "description": "Device Data Output Register",\r
1021               "addressOffset": "0x0030"\r
1022             },\r
1023             "rsctrl": {\r
1024               "description": "Read Sequencer Control Register",\r
1025               "addressOffset": "0x0034",\r
1026               "fields": {\r
1027                 "scale": {\r
1028                   "description": "OTP timescale",\r
1029                   "bitOffset": "0",\r
1030                   "bitWidth": "2",\r
1031                   "resetMask": "all",\r
1032                   "resetValue": "0x1"\r
1033                 },\r
1034                 "tas": {\r
1035                   "description": "Address setup time",\r
1036                   "bitOffset": "3",\r
1037                   "bitWidth": "1",\r
1038                   "resetMask": "all",\r
1039                   "resetValue": "0x0"\r
1040                 },\r
1041                 "trp": {\r
1042                   "description": "Read pulse time",\r
1043                   "bitOffset": "4",\r
1044                   "bitWidth": "1"\r
1045                 },\r
1046                 "tracc": {\r
1047                   "description": "Read access time",\r
1048                   "bitOffset": "5",\r
1049                   "bitWidth": "1"\r
1050                 }\r
1051               }\r
1052             }\r
1053           }\r
1054         },\r
1055         "gpio": {\r
1056           "description": "General Purpose Input/Output Controller (GPIO) Peripheral",\r
1057           "baseAddress": "0x10012000",\r
1058           "size": "0x1000",\r
1059           "registers": {\r
1060             "value": {\r
1061               "description": "Pin Value Register",\r
1062               "addressOffset": "0x000",\r
1063               "fields": {\r
1064                 "bit": {\r
1065                   "repeatGenerator": "0-31",\r
1066                   "description": "Value Bit Field",\r
1067                   "bitOffset": "0",\r
1068                   "bitWidth": "1",\r
1069                   "headerName": ""\r
1070                 }\r
1071               }\r
1072             },\r
1073             "inputen": {\r
1074               "description": "Pin Input Enable Register",\r
1075               "addressOffset": "0x004",\r
1076               "fields": {\r
1077                 "bit": {\r
1078                   "repeatGenerator": "0-31",\r
1079                   "description": "Pin Input Enable Bit Field",\r
1080                   "bitOffset": "0",\r
1081                   "bitWidth": "1",\r
1082                   "headerName": ""\r
1083                 }\r
1084               }\r
1085             },\r
1086             "outputen": {\r
1087               "description": "Pin Output Enable Register",\r
1088               "addressOffset": "0x008",\r
1089               "fields": {\r
1090                 "bit": {\r
1091                   "repeatGenerator": "0-31",\r
1092                   "description": "Pin Output Enable Bit Field",\r
1093                   "bitOffset": "0",\r
1094                   "bitWidth": "1",\r
1095                   "headerName": ""\r
1096                 }\r
1097               }\r
1098             },\r
1099             "port": {\r
1100               "description": "Output Port Value Register",\r
1101               "addressOffset": "0x00C",\r
1102               "fields": {\r
1103                 "bit": {\r
1104                   "repeatGenerator": "0-31",\r
1105                   "description": "Output Port Value Bit Field",\r
1106                   "bitOffset": "0",\r
1107                   "bitWidth": "1",\r
1108                   "headerName": ""\r
1109                 }\r
1110               }\r
1111             },\r
1112             "pue": {\r
1113               "description": "Internal Pull-up Enable Register",\r
1114               "addressOffset": "0x010",\r
1115               "fields": {\r
1116                 "bit": {\r
1117                   "repeatGenerator": "0-31",\r
1118                   "description": "Internal Pull-up Enable Bit Field",\r
1119                   "bitOffset": "0",\r
1120                   "bitWidth": "1",\r
1121                   "headerName": ""\r
1122                 }\r
1123               }\r
1124             },\r
1125             "ds": {\r
1126               "description": "Pin Drive Strength Register",\r
1127               "addressOffset": "0x014",\r
1128               "fields": {\r
1129                 "bit": {\r
1130                   "repeatGenerator": "0-31",\r
1131                   "description": "Pin Drive Strength Bit Field",\r
1132                   "bitOffset": "0",\r
1133                   "bitWidth": "1",\r
1134                   "headerName": ""\r
1135                 }\r
1136               }\r
1137             },\r
1138             "riseie": {\r
1139               "description": "Rise Interrupt Enable Register",\r
1140               "addressOffset": "0x018",\r
1141               "fields": {\r
1142                 "bit": {\r
1143                   "repeatGenerator": "0-31",\r
1144                   "description": "Rise Interrupt Enable Bit Field",\r
1145                   "bitOffset": "0",\r
1146                   "bitWidth": "1",\r
1147                   "headerName": ""\r
1148                 }\r
1149               }\r
1150             },\r
1151             "riseip": {\r
1152               "description": "Rise Interrupt Pending Register",\r
1153               "addressOffset": "0x01C",\r
1154               "fields": {\r
1155                 "bit": {\r
1156                   "repeatGenerator": "0-31",\r
1157                   "description": "Rise Interrupt Pending Bit Field",\r
1158                   "bitOffset": "0",\r
1159                   "bitWidth": "1",\r
1160                   "headerName": ""\r
1161                 }\r
1162               }\r
1163             },\r
1164             "fallie": {\r
1165               "description": "Fall Interrupt Enable Register",\r
1166               "addressOffset": "0x020",\r
1167               "fields": {\r
1168                 "bit": {\r
1169                   "repeatGenerator": "0-31",\r
1170                   "description": "Fall Interrupt Enable Bit Field",\r
1171                   "bitOffset": "0",\r
1172                   "bitWidth": "1",\r
1173                   "headerName": ""\r
1174                 }\r
1175               }\r
1176             },\r
1177             "fallip": {\r
1178               "description": "Fall Interrupt Pending Register",\r
1179               "addressOffset": "0x024",\r
1180               "fields": {\r
1181                 "bit": {\r
1182                   "repeatGenerator": "0-31",\r
1183                   "description": "Fall Interrupt Pending Bit Field",\r
1184                   "bitOffset": "0",\r
1185                   "bitWidth": "1",\r
1186                   "headerName": ""\r
1187                 }\r
1188               }\r
1189             },\r
1190             "highie": {\r
1191               "description": "High Interrupt Enable Register",\r
1192               "addressOffset": "0x028",\r
1193               "fields": {\r
1194                 "bit": {\r
1195                   "repeatGenerator": "0-31",\r
1196                   "description": "High Interrupt Enable Bit Field",\r
1197                   "bitOffset": "0",\r
1198                   "bitWidth": "1",\r
1199                   "headerName": ""\r
1200                 }\r
1201               }\r
1202             },\r
1203             "highip": {\r
1204               "description": "High Interrupt Pending Register",\r
1205               "addressOffset": "0x02C",\r
1206               "fields": {\r
1207                 "bit": {\r
1208                   "repeatGenerator": "0-31",\r
1209                   "description": "High Interrupt Pending Bit Field",\r
1210                   "bitOffset": "0",\r
1211                   "bitWidth": "1",\r
1212                   "headerName": ""\r
1213                 }\r
1214               }\r
1215             },\r
1216             "lowie": {\r
1217               "description": "Low Interrupt Enable Register",\r
1218               "addressOffset": "0x030",\r
1219               "fields": {\r
1220                 "bit": {\r
1221                   "repeatGenerator": "0-31",\r
1222                   "description": "Low Interrupt Enable Bit Field",\r
1223                   "bitOffset": "0",\r
1224                   "bitWidth": "1",\r
1225                   "headerName": ""\r
1226                 }\r
1227               }\r
1228             },\r
1229             "lowip": {\r
1230               "description": "Low Interrupt Pending Register",\r
1231               "addressOffset": "0x034",\r
1232               "fields": {\r
1233                 "bit": {\r
1234                   "repeatGenerator": "0-31",\r
1235                   "description": "Low Interrupt Pending Bit Field",\r
1236                   "bitOffset": "0",\r
1237                   "bitWidth": "1",\r
1238                   "headerName": ""\r
1239                 }\r
1240               }\r
1241             },\r
1242             "iofen": {\r
1243               "description": "HW I/O Function Enable Register",\r
1244               "addressOffset": "0x038",\r
1245               "fields": {\r
1246                 "bit": {\r
1247                   "repeatGenerator": "0-31",\r
1248                   "description": "HW I/O Function Enable Bit Field",\r
1249                   "bitOffset": "0",\r
1250                   "bitWidth": "1",\r
1251                   "headerName": ""\r
1252                 }\r
1253               }\r
1254             },\r
1255             "iofsel": {\r
1256               "description": "HW I/O Function Select Register",\r
1257               "addressOffset": "0x03C",\r
1258               "fields": {\r
1259                 "bit": {\r
1260                   "repeatGenerator": "0-31",\r
1261                   "description": "HW I/O Function Select Bit Field",\r
1262                   "bitOffset": "0",\r
1263                   "bitWidth": "1",\r
1264                   "headerName": ""\r
1265                 }\r
1266               }\r
1267             },\r
1268             "outxor": {\r
1269               "description": "Output XOR (invert) Register",\r
1270               "addressOffset": "0x040",\r
1271               "fields": {\r
1272                 "bit": {\r
1273                   "repeatGenerator": "0-31",\r
1274                   "description": "Output XOR Bit Field",\r
1275                   "bitOffset": "0",\r
1276                   "bitWidth": "1",\r
1277                   "headerName": ""\r
1278                 }\r
1279               }\r
1280             }\r
1281           },\r
1282           "interrupts": {\r
1283             "gpio0": {\r
1284               "description": "GPIO0 Interrupt",\r
1285               "value": "8"\r
1286             },\r
1287             "gpio1": {\r
1288               "description": "GPIO1 Interrupt",\r
1289               "value": "9"\r
1290             },\r
1291             "gpio2": {\r
1292               "description": "GPIO2 Interrupt",\r
1293               "value": "10"\r
1294             },\r
1295             "gpio3": {\r
1296               "description": "GPIO3 Interrupt",\r
1297               "value": "11"\r
1298             },\r
1299             "gpio4": {\r
1300               "description": "GPIO4 Interrupt",\r
1301               "value": "12"\r
1302             },\r
1303             "gpio5": {\r
1304               "description": "GPIO5 Interrupt",\r
1305               "value": "13"\r
1306             },\r
1307             "gpio6": {\r
1308               "description": "GPIO6 Interrupt",\r
1309               "value": "14"\r
1310             },\r
1311             "gpio7": {\r
1312               "description": "GPIO7 Interrupt",\r
1313               "value": "15"\r
1314             },\r
1315             "gpio8": {\r
1316               "description": "GPIO8 Interrupt",\r
1317               "value": "16"\r
1318             },\r
1319             "gpio9": {\r
1320               "description": "GPIO9 Interrupt",\r
1321               "value": "17"\r
1322             },\r
1323             "gpio10": {\r
1324               "description": "GPIO10 Interrupt",\r
1325               "value": "18"\r
1326             },\r
1327             "gpio11": {\r
1328               "description": "GPIO11 Interrupt",\r
1329               "value": "19"\r
1330             },\r
1331             "gpio12": {\r
1332               "description": "GPIO12 Interrupt",\r
1333               "value": "20"\r
1334             },\r
1335             "gpio13": {\r
1336               "description": "GPIO13 Interrupt",\r
1337               "value": "21"\r
1338             },\r
1339             "gpio14": {\r
1340               "description": "GPIO14 Interrupt",\r
1341               "value": "22"\r
1342             },\r
1343             "gpio15": {\r
1344               "description": "GPIO15 Interrupt",\r
1345               "value": "23"\r
1346             },\r
1347             "gpio16": {\r
1348               "description": "GPIO16 Interrupt",\r
1349               "value": "24"\r
1350             },\r
1351             "gpio17": {\r
1352               "description": "GPIO17 Interrupt",\r
1353               "value": "25"\r
1354             },\r
1355             "gpio18": {\r
1356               "description": "GPIO18 Interrupt",\r
1357               "value": "26"\r
1358             },\r
1359             "gpio19": {\r
1360               "description": "GPIO19 Interrupt",\r
1361               "value": "27"\r
1362             },\r
1363             "gpio20": {\r
1364               "description": "GPIO20 Interrupt",\r
1365               "value": "28"\r
1366             },\r
1367             "gpio21": {\r
1368               "description": "GPIO21 Interrupt",\r
1369               "value": "29"\r
1370             },\r
1371             "gpio22": {\r
1372               "description": "GPIO22 Interrupt",\r
1373               "value": "30"\r
1374             },\r
1375             "gpio23": {\r
1376               "description": "GPIO23 Interrupt",\r
1377               "value": "31"\r
1378             },\r
1379             "gpio24": {\r
1380               "description": "GPIO24 Interrupt",\r
1381               "value": "32"\r
1382             },\r
1383             "gpio25": {\r
1384               "description": "GPIO25 Interrupt",\r
1385               "value": "33"\r
1386             },\r
1387             "gpio26": {\r
1388               "description": "GPIO26 Interrupt",\r
1389               "value": "34"\r
1390             },\r
1391             "gpio27": {\r
1392               "description": "GPIO27 Interrupt",\r
1393               "value": "35"\r
1394             },\r
1395             "gpio28": {\r
1396               "description": "GPIO28 Interrupt",\r
1397               "value": "36"\r
1398             },\r
1399             "gpio29": {\r
1400               "description": "GPIO29 Interrupt",\r
1401               "value": "37"\r
1402             },\r
1403             "gpio30": {\r
1404               "description": "GPIO30 Interrupt",\r
1405               "value": "38"\r
1406             },\r
1407             "gpio31": {\r
1408               "description": "GPIO31 Interrupt",\r
1409               "value": "39"\r
1410             }\r
1411           }\r
1412         },\r
1413         "uart0": {\r
1414           "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral",\r
1415           "baseAddress": "0x10013000",\r
1416           "size": "0x1000",\r
1417           "resetMask": "none",\r
1418           "groupName": "uart",\r
1419           "registers": {\r
1420             "txdata": {\r
1421               "description": "Transmit Data Register",\r
1422               "addressOffset": "0x000",\r
1423               "fields": {\r
1424                 "data": {\r
1425                   "description": "Transmit data",\r
1426                   "bitOffset": "0",\r
1427                   "bitWidth": "8"\r
1428                 },\r
1429                 "full": {\r
1430                   "description": "Transmit FIFO full",\r
1431                   "bitOffset": "31",\r
1432                   "bitWidth": "1"\r
1433                 }\r
1434               }\r
1435             },\r
1436             "rxdata": {\r
1437               "description": "Receive Data Register",\r
1438               "addressOffset": "0x004",\r
1439               "resetMask": "none",\r
1440               "fields": {\r
1441                 "data": {\r
1442                   "description": "Received data",\r
1443                   "bitOffset": "0",\r
1444                   "bitWidth": "8",\r
1445                   "access": "r"\r
1446                 },\r
1447                 "empty": {\r
1448                   "description": "Receive FIFO empty",\r
1449                   "bitOffset": "31",\r
1450                   "bitWidth": "1"\r
1451                 }\r
1452               }\r
1453             },\r
1454             "txctrl": {\r
1455               "description": "Transmit Control Register ",\r
1456               "addressOffset": "0x008",\r
1457               "fields": {\r
1458                 "txen": {\r
1459                   "description": "Transmit enable",\r
1460                   "bitOffset": "0",\r
1461                   "bitWidth": "1",\r
1462                   "resetMask": "all",\r
1463                   "resetValue": "0x0"\r
1464                 },\r
1465                 "nstop": {\r
1466                   "description": "Number of stop bits",\r
1467                   "bitOffset": "1",\r
1468                   "bitWidth": "1",\r
1469                   "resetMask": "all",\r
1470                   "resetValue": "0x0"\r
1471                 },\r
1472                 "txcnt": {\r
1473                   "description": "Transmit watermark level",\r
1474                   "bitOffset": "16",\r
1475                   "bitWidth": "3",\r
1476                   "resetMask": "all",\r
1477                   "resetValue": "0x0"\r
1478                 }\r
1479               }\r
1480             },\r
1481             "rxctrl": {\r
1482               "description": "Receive Control Register",\r
1483               "addressOffset": "0x00C",\r
1484               "fields": {\r
1485                 "rxen": {\r
1486                   "description": "Receive enable",\r
1487                   "bitOffset": "0",\r
1488                   "bitWidth": "1",\r
1489                   "resetMask": "all",\r
1490                   "resetValue": "0x0"\r
1491                 },\r
1492                 "rxcnt": {\r
1493                   "description": "Receive watermark level",\r
1494                   "bitOffset": "16",\r
1495                   "bitWidth": "3",\r
1496                   "resetMask": "all",\r
1497                   "resetValue": "0x0"\r
1498                 }\r
1499               }\r
1500             },\r
1501             "ie": {\r
1502               "description": "Interrupt Enable Register",\r
1503               "addressOffset": "0x010",\r
1504               "fields": {\r
1505                 "txwm": {\r
1506                   "description": "Transmit watermark interrupt enable",\r
1507                   "bitOffset": "0",\r
1508                   "bitWidth": "1",\r
1509                   "resetMask": "all",\r
1510                   "resetValue": "0x0"\r
1511                 },\r
1512                 "rxwm": {\r
1513                   "description": "Receive watermark interrupt enable",\r
1514                   "bitOffset": "1",\r
1515                   "bitWidth": "1",\r
1516                   "resetMask": "all",\r
1517                   "resetValue": "0x0"\r
1518                 }\r
1519               }\r
1520             },\r
1521             "ip": {\r
1522               "description": "Interrupt Pending Register",\r
1523               "addressOffset": "0x014",\r
1524               "access": "r",\r
1525               "fields": {\r
1526                 "txwm": {\r
1527                   "description": "Transmit watermark interrupt pending",\r
1528                   "bitOffset": "0",\r
1529                   "bitWidth": "1"\r
1530                 },\r
1531                 "rxwm": {\r
1532                   "description": "Receive watermark interrupt pending",\r
1533                   "bitOffset": "1",\r
1534                   "bitWidth": "1"\r
1535                 }\r
1536               }\r
1537             },\r
1538             "div": {\r
1539               "description": "Baud Rate Divisor Register",\r
1540               "addressOffset": "0x018",\r
1541               "fields": {\r
1542                 "value": {\r
1543                   "description": "Baud rate divisor",\r
1544                   "bitOffset": "0",\r
1545                   "bitWidth": "16",\r
1546                   "resetMask": "all",\r
1547                   "resetValue": "0x0000FFFF"\r
1548                 }\r
1549               }\r
1550             }\r
1551           },\r
1552           "interrupts": {\r
1553             "uart0": {\r
1554               "description": "UART0 Interrupt",\r
1555               "value": "3"\r
1556             }\r
1557           }\r
1558         },\r
1559         "spi0": {\r
1560           "description": "Serial Peripheral Interface (SPI) Peripheral",\r
1561           "baseAddress": "0x10014000",\r
1562           "size": "0x1000",\r
1563           "resetMask": "none",\r
1564           "groupName": "spi",\r
1565           "registers": {\r
1566             "sckdiv": {\r
1567               "description": "Serial clock divisor Register",\r
1568               "addressOffset": "0x000",\r
1569               "fields": {\r
1570                 "scale": {\r
1571                   "description": "Divisor for serial clock",\r
1572                   "bitOffset": "0",\r
1573                   "bitWidth": "12",\r
1574                   "resetMask": "all",\r
1575                   "resetValue": "0x003"\r
1576                 }\r
1577               }\r
1578             },\r
1579             "sckmode": {\r
1580               "description": "Serial Clock Mode Register",\r
1581               "addressOffset": "0x004",\r
1582               "fields": {\r
1583                 "pha": {\r
1584                   "description": "Serial clock phase",\r
1585                   "bitOffset": "0",\r
1586                   "bitWidth": "1",\r
1587                   "resetMask": "all",\r
1588                   "resetValue": "0x0"\r
1589                 },\r
1590                 "pol": {\r
1591                   "description": "Serial clock polarity",\r
1592                   "bitOffset": "1",\r
1593                   "bitWidth": "1",\r
1594                   "resetMask": "all",\r
1595                   "resetValue": "0x0"\r
1596                 }\r
1597               }\r
1598             },\r
1599             "csid": {\r
1600               "description": "Chip Select ID Register",\r
1601               "addressOffset": "0x010",\r
1602               "resetMask": "all",\r
1603               "resetValue": "0x00000000"\r
1604             },\r
1605             "csdef": {\r
1606               "description": "Chip Select Default Register",\r
1607               "addressOffset": "0x014",\r
1608               "resetMask": "all",\r
1609               "resetValue": "0x00000001"\r
1610             },\r
1611             "csmode": {\r
1612               "description": "Chip Select Mode Register",\r
1613               "addressOffset": "0x018",\r
1614               "fields": {\r
1615                 "mode": {\r
1616                   "description": "Chip select mode",\r
1617                   "bitOffset": "0",\r
1618                   "bitWidth": "2",\r
1619                   "resetMask": "all",\r
1620                   "resetValue": "0x0",\r
1621                   "enumerations": {\r
1622                     "csmode-enum": {\r
1623                       "description": "Chip Select Modes Enumeration",\r
1624                       "values": {\r
1625                         "0": {\r
1626                           "displayName": "auto",\r
1627                           "description": "Assert/de-assert CS at the beginning/end of each frame"\r
1628                         },\r
1629                         "*": {\r
1630                           "displayName": "reserved"\r
1631                         },\r
1632                         "2": {\r
1633                           "displayName": "hold",\r
1634                           "description": "Keep CS continuously asserted after the initial frame"\r
1635                         },\r
1636                         "3": {\r
1637                           "displayName": "off",\r
1638                           "description": "Disable hardware control of the CS pin"\r
1639                         }\r
1640                       }\r
1641                     }\r
1642                   }\r
1643                 }\r
1644               }\r
1645             },\r
1646             "delay0": {\r
1647               "description": "Delay Control 0 Register",\r
1648               "addressOffset": "0x028",\r
1649               "fields": {\r
1650                 "cssck": {\r
1651                   "description": "CS to SCK Delay",\r
1652                   "bitOffset": "0",\r
1653                   "bitWidth": "8",\r
1654                   "resetMask": "all",\r
1655                   "resetValue": "0x01"\r
1656                 },\r
1657                 "sckcs": {\r
1658                   "description": "SCK to CS Delay",\r
1659                   "bitOffset": "16",\r
1660                   "bitWidth": "8",\r
1661                   "resetMask": "all",\r
1662                   "resetValue": "0x01"\r
1663                 }\r
1664               }\r
1665             },\r
1666             "delay1": {\r
1667               "description": "Delay Control 1 Register",\r
1668               "addressOffset": "0x02C",\r
1669               "fields": {\r
1670                 "intercs": {\r
1671                   "description": "Minimum CS inactive time",\r
1672                   "bitOffset": "0",\r
1673                   "bitWidth": "8",\r
1674                   "resetMask": "all",\r
1675                   "resetValue": "0x01"\r
1676                 },\r
1677                 "interxfr": {\r
1678                   "description": "Maximum interframe delay",\r
1679                   "bitOffset": "16",\r
1680                   "bitWidth": "8",\r
1681                   "resetMask": "all",\r
1682                   "resetValue": "0x01"\r
1683                 }\r
1684               }\r
1685             },\r
1686             "fmt": {\r
1687               "description": "Frame Format Register",\r
1688               "addressOffset": "0x040",\r
1689               "fields": {\r
1690                 "proto": {\r
1691                   "description": "SPI Protocol",\r
1692                   "bitOffset": "0",\r
1693                   "bitWidth": "2",\r
1694                   "resetMask": "all",\r
1695                   "resetValue": "0x0",\r
1696                   "enumerations": {\r
1697                     "proto-enum": {\r
1698                       "description": "SPI Protocol Enumeration",\r
1699                       "values": {\r
1700                         "0": {\r
1701                           "displayName": "single",\r
1702                           "description": "DQ0 (MOSI), DQ1 (MISO)"\r
1703                         },\r
1704                         "1": {\r
1705                           "displayName": "dual",\r
1706                           "description": "DQ0, DQ1"\r
1707                         },\r
1708                         "2": {\r
1709                           "displayName": "quad",\r
1710                           "description": "DQ0, DQ1, DQ2, DQ3"\r
1711                         },\r
1712                         "*": {\r
1713                           "displayName": "reserved"\r
1714                         }\r
1715                       }\r
1716                     }\r
1717                   }\r
1718                 },\r
1719                 "endian": {\r
1720                   "description": "SPI endianness",\r
1721                   "bitOffset": "2",\r
1722                   "bitWidth": "1",\r
1723                   "resetMask": "all",\r
1724                   "resetValue": "0x0",\r
1725                   "enumerations": {\r
1726                     "endian-enum": {\r
1727                       "description": "SPI Endianness Enumeration",\r
1728                       "values": {\r
1729                         "0": {\r
1730                           "displayName": "msb",\r
1731                           "description": "Transmit most-significant bit (MSB) first"\r
1732                         },\r
1733                         "1": {\r
1734                           "displayName": "lsb",\r
1735                           "description": "Transmit least-significant bit (LSB) first"\r
1736                         }\r
1737                       }\r
1738                     }\r
1739                   }\r
1740                 },\r
1741                 "dir": {\r
1742                   "description": "SPI I/O Direction",\r
1743                   "bitOffset": "3",\r
1744                   "bitWidth": "1",\r
1745                   "resetMask": "all",\r
1746                   "resetValue": "0x1",\r
1747                   "enumerations": {\r
1748                     "dir-enum": {\r
1749                       "description": "SPI I/O Direction Enumeration",\r
1750                       "values": {\r
1751                         "0": {\r
1752                           "displayName": "rx",\r
1753                           "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal."\r
1754                         },\r
1755                         "1": {\r
1756                           "displayName": "tx",\r
1757                           "description": "The receive FIFO is not populated."\r
1758                         }\r
1759                       }\r
1760                     }\r
1761                   }\r
1762                 },\r
1763                 "len": {\r
1764                   "description": "Number of bits per frame",\r
1765                   "bitOffset": "16",\r
1766                   "bitWidth": "4",\r
1767                   "resetMask": "all",\r
1768                   "resetValue": "0x8"\r
1769                 }\r
1770               }\r
1771             },\r
1772             "txdata": {\r
1773               "description": "Tx FIFO Data Register",\r
1774               "addressOffset": "0x048",\r
1775               "fields": {\r
1776                 "data": {\r
1777                   "description": "Transmit data",\r
1778                   "bitOffset": "0",\r
1779                   "bitWidth": "8",\r
1780                   "resetMask": "all",\r
1781                   "resetValue": "0x00"\r
1782                 },\r
1783                 "full": {\r
1784                   "description": "FIFO full flag",\r
1785                   "bitOffset": "31",\r
1786                   "bitWidth": "1",\r
1787                   "access": "r"\r
1788                 }\r
1789               }\r
1790             },\r
1791             "rxdata": {\r
1792               "description": "Rx FIFO Data Register",\r
1793               "addressOffset": "0x04C",\r
1794               "resetMask": "none",\r
1795               "access": "r",\r
1796               "fields": {\r
1797                 "data": {\r
1798                   "description": "Received data",\r
1799                   "bitOffset": "0",\r
1800                   "bitWidth": "8"\r
1801                 },\r
1802                 "empty": {\r
1803                   "description": "FIFO empty flag",\r
1804                   "bitOffset": "31",\r
1805                   "bitWidth": "1"\r
1806                 }\r
1807               }\r
1808             },\r
1809             "txmark": {\r
1810               "description": "Tx FIFO Watermark Register",\r
1811               "addressOffset": "0x050",\r
1812               "fields": {\r
1813                 "value": {\r
1814                   "description": "Transmit watermark",\r
1815                   "bitOffset": "0",\r
1816                   "bitWidth": "3",\r
1817                   "resetMask": "all",\r
1818                   "resetValue": "0x1"\r
1819                 }\r
1820               }\r
1821             },\r
1822             "rxmark": {\r
1823               "description": "Rx FIFO Watermark Register",\r
1824               "addressOffset": "0x054",\r
1825               "fields": {\r
1826                 "value": {\r
1827                   "description": "Receive watermark",\r
1828                   "bitOffset": "0",\r
1829                   "bitWidth": "3",\r
1830                   "resetMask": "all",\r
1831                   "resetValue": "0x0"\r
1832                 }\r
1833               }\r
1834             },\r
1835             "fctrl": {\r
1836               "description": "Flash Interface Control Register",\r
1837               "addressOffset": "0x060",\r
1838               "fields": {\r
1839                 "en": {\r
1840                   "description": "SPI Flash Mode Select",\r
1841                   "bitOffset": "0",\r
1842                   "bitWidth": "1",\r
1843                   "resetMask": "all",\r
1844                   "resetValue": "0x1"\r
1845                 }\r
1846               }\r
1847             },\r
1848             "ffmt": {\r
1849               "description": "Flash Instruction Format Register",\r
1850               "addressOffset": "0x064",\r
1851               "fields": {\r
1852                 "cmden": {\r
1853                   "description": "Enable sending of command",\r
1854                   "bitOffset": "0",\r
1855                   "bitWidth": "1",\r
1856                   "resetMask": "all",\r
1857                   "resetValue": "0x1"\r
1858                 },\r
1859                 "addrlen": {\r
1860                   "description": "Number of address bytes(0 to 4)",\r
1861                   "bitOffset": "1",\r
1862                   "bitWidth": "3",\r
1863                   "resetMask": "all",\r
1864                   "resetValue": "0x3"\r
1865                 },\r
1866                 "padcnt": {\r
1867                   "description": "Number of dummy cycles",\r
1868                   "bitOffset": "4",\r
1869                   "bitWidth": "4",\r
1870                   "resetMask": "all",\r
1871                   "resetValue": "0x0"\r
1872                 },\r
1873                 "cmdproto": {\r
1874                   "description": "Protocol for transmitting command",\r
1875                   "bitOffset": "8",\r
1876                   "bitWidth": "2",\r
1877                   "resetMask": "all",\r
1878                   "resetValue": "0x0"\r
1879                 },\r
1880                 "addrproto": {\r
1881                   "description": "Protocol for transmitting address and padding",\r
1882                   "bitOffset": "10",\r
1883                   "bitWidth": "2",\r
1884                   "resetMask": "all",\r
1885                   "resetValue": "0x0"\r
1886                 },\r
1887                 "dataproto": {\r
1888                   "description": "Protocol for receiving data bytes",\r
1889                   "bitOffset": "12",\r
1890                   "bitWidth": "2",\r
1891                   "resetMask": "all",\r
1892                   "resetValue": "0x0"\r
1893                 },\r
1894                 "cmdcode": {\r
1895                   "description": "Value of command byte",\r
1896                   "bitOffset": "16",\r
1897                   "bitWidth": "8",\r
1898                   "resetMask": "all",\r
1899                   "resetValue": "0x03"\r
1900                 },\r
1901                 "padcode": {\r
1902                   "description": "First 8 bits to transmit during dummy cycles",\r
1903                   "bitOffset": "24",\r
1904                   "bitWidth": "8",\r
1905                   "resetMask": "all",\r
1906                   "resetValue": "0x0"\r
1907                 }\r
1908               }\r
1909             },\r
1910             "ie": {\r
1911               "description": "Interrupt Enable Register",\r
1912               "addressOffset": "0x070",\r
1913               "fields": {\r
1914                 "txwm": {\r
1915                   "description": "Transmit watermark enable",\r
1916                   "bitOffset": "0",\r
1917                   "bitWidth": "1",\r
1918                   "access": "r",\r
1919                   "resetMask": "all",\r
1920                   "resetValue": "0x0"\r
1921                 },\r
1922                 "rxwm": {\r
1923                   "description": "Receive watermark enable",\r
1924                   "bitOffset": "1",\r
1925                   "bitWidth": "1",\r
1926                   "access": "r",\r
1927                   "resetMask": "all",\r
1928                   "resetValue": "0x0"\r
1929                 }\r
1930               }\r
1931             },\r
1932             "ip": {\r
1933               "description": "Interrupt Pending Register",\r
1934               "addressOffset": "0x074",\r
1935               "fields": {\r
1936                 "txwm": {\r
1937                   "description": "Transmit watermark pending",\r
1938                   "bitOffset": "0",\r
1939                   "bitWidth": "1",\r
1940                   "access": "r"\r
1941                 },\r
1942                 "rxwm": {\r
1943                   "description": "Receive watermark pending",\r
1944                   "bitOffset": "1",\r
1945                   "bitWidth": "1",\r
1946                   "access": "r"\r
1947                 }\r
1948               }\r
1949             }\r
1950           },\r
1951           "interrupts": {\r
1952             "spi0": {\r
1953               "description": "SPI0 Interrupt",\r
1954               "value": "5"\r
1955             }\r
1956           }\r
1957         },\r
1958         "pwm0": {\r
1959           "description": "Pulse-Width Modulation (PWM) Peripheral",\r
1960           "baseAddress": "0x10015000",\r
1961           "size": "0x1000",\r
1962           "resetMask": "none",\r
1963           "registers": {\r
1964             "cfg": {\r
1965               "description": "Configuration Register",\r
1966               "addressOffset": "0x000",\r
1967               "fields": {\r
1968                 "scale": {\r
1969                   "description": "Counter scale",\r
1970                   "bitOffset": "0",\r
1971                   "bitWidth": "4"\r
1972                 },\r
1973                 "sticky": {\r
1974                   "description": "Sticky - disallow clearing pwmcmpXip bits",\r
1975                   "bitOffset": "8",\r
1976                   "bitWidth": "1"\r
1977                 },\r
1978                 "zerocmp": {\r
1979                   "description": "Zero - counter resets to zero after match",\r
1980                   "bitOffset": "9",\r
1981                   "bitWidth": "1"\r
1982                 },\r
1983                 "deglitch": {\r
1984                   "description": "Deglitch - latch pwmcmpXip within same cycle",\r
1985                   "bitOffset": "10",\r
1986                   "bitWidth": "1"\r
1987                 },\r
1988                 "enalways": {\r
1989                   "description": "Enable always - run continuously",\r
1990                   "bitOffset": "12",\r
1991                   "bitWidth": "1",\r
1992                   "resetMask": "all",\r
1993                   "resetValue": "0x0"\r
1994                 },\r
1995                 "enoneshot": {\r
1996                   "description": "enable one shot - run one cycle",\r
1997                   "bitOffset": "13",\r
1998                   "bitWidth": "1",\r
1999                   "resetMask": "all",\r
2000                   "resetValue": "0x0"\r
2001                 },\r
2002                 "cmp0center": {\r
2003                   "description": "PWM0 Compare Center",\r
2004                   "bitOffset": "16",\r
2005                   "bitWidth": "1"\r
2006                 },\r
2007                 "cmp1center": {\r
2008                   "description": "PWM1 Compare Center",\r
2009                   "bitOffset": "17",\r
2010                   "bitWidth": "1"\r
2011                 },\r
2012                 "cmp2center": {\r
2013                   "description": "PWM2 Compare Center",\r
2014                   "bitOffset": "18",\r
2015                   "bitWidth": "1"\r
2016                 },\r
2017                 "cmp3center": {\r
2018                   "description": "PWM3 Compare Center",\r
2019                   "bitOffset": "19",\r
2020                   "bitWidth": "1"\r
2021                 },\r
2022                 "cmp0gang": {\r
2023                   "description": "PWM0/PWM1 Compare Gang",\r
2024                   "bitOffset": "24",\r
2025                   "bitWidth": "1"\r
2026                 },\r
2027                 "cmp1gang": {\r
2028                   "description": "PWM1/PWM2 Compare Gang",\r
2029                   "bitOffset": "25",\r
2030                   "bitWidth": "1"\r
2031                 },\r
2032                 "cmp2gang": {\r
2033                   "description": "PWM2/PWM3 Compare Gang",\r
2034                   "bitOffset": "26",\r
2035                   "bitWidth": "1"\r
2036                 },\r
2037                 "cmp3gang": {\r
2038                   "description": "PWM3/PWM0 Compare Gang",\r
2039                   "bitOffset": "27",\r
2040                   "bitWidth": "1"\r
2041                 },\r
2042                 "cmp0ip": {\r
2043                   "description": "PWM0 Interrupt Pending",\r
2044                   "bitOffset": "28",\r
2045                   "bitWidth": "1"\r
2046                 },\r
2047                 "cmp1ip": {\r
2048                   "description": "PWM1 Interrupt Pending",\r
2049                   "bitOffset": "29",\r
2050                   "bitWidth": "1"\r
2051                 },\r
2052                 "cmp2ip": {\r
2053                   "description": "PWM2 Interrupt Pending",\r
2054                   "bitOffset": "30",\r
2055                   "bitWidth": "1"\r
2056                 },\r
2057                 "cmp3ip": {\r
2058                   "description": "PWM3 Interrupt Pending",\r
2059                   "bitOffset": "31",\r
2060                   "bitWidth": "1"\r
2061                 }\r
2062               }\r
2063             },\r
2064             "count": {\r
2065               "description": "Configuration Register",\r
2066               "addressOffset": "0x008"\r
2067             },\r
2068             "scale": {\r
2069               "description": "Scale Register",\r
2070               "addressOffset": "0x010",\r
2071               "fields": {\r
2072                 "value": {\r
2073                   "description": "Compare value",\r
2074                   "bitOffset": "0",\r
2075                   "bitWidth": "8"\r
2076                 }\r
2077               }\r
2078             },\r
2079             "cmp": {\r
2080               "arraySize": "4",\r
2081               "description": "Compare Registers",\r
2082               "addressOffset": "0x020",\r
2083               "fields": {\r
2084                 "value": {\r
2085                   "description": "Compare value",\r
2086                   "bitOffset": "0",\r
2087                   "bitWidth": "8"\r
2088                 }\r
2089               }\r
2090             }\r
2091           },\r
2092           "interrupts": {\r
2093             "pwm0cmp0": {\r
2094               "description": "PWM0 Compare 0 Interrupt",\r
2095               "value": "40"\r
2096             },\r
2097             "pwm0cmp1": {\r
2098               "description": "PWM0 Compare 1 Interrupt",\r
2099               "value": "41"\r
2100             },\r
2101             "pwm0cmp2": {\r
2102               "description": "PWM0 Compare 2 Interrupt",\r
2103               "value": "42"\r
2104             },\r
2105             "pwm0cmp3": {\r
2106               "description": "PWM0 Compare 3 Interrupt",\r
2107               "value": "43"\r
2108             }\r
2109           }\r
2110         },\r
2111         "uart1": {\r
2112           "baseAddress": "0x10023000",\r
2113           "derivedFrom": "uart0",\r
2114           "groupName": "uart",\r
2115           "interrupts": {\r
2116             "uart1": {\r
2117               "description": "UART1 Interrupt",\r
2118               "value": "4"\r
2119             }\r
2120           }\r
2121         },\r
2122         "spi1": {\r
2123           "baseAddress": "0x10024000",\r
2124           "derivedFrom": "spi0",\r
2125           "groupName": "spi",\r
2126           "interrupts": {\r
2127             "spi1": {\r
2128               "description": "SPI1 Interrupt",\r
2129               "value": "6"\r
2130             }\r
2131           }\r
2132         },\r
2133         "pwm1": {\r
2134           "description": "Pulse-Width Modulation (PWM) Peripheral",\r
2135           "baseAddress": "0x10025000",\r
2136           "groupName": "pwm",\r
2137           "size": "0x1000",\r
2138           "resetMask": "none",\r
2139           "groupName": "pwm",\r
2140           "registers": {\r
2141             "cfg": {\r
2142               "description": "Configuration Register",\r
2143               "addressOffset": "0x000",\r
2144               "fields": {\r
2145                 "scale": {\r
2146                   "description": "Counter scale",\r
2147                   "bitOffset": "0",\r
2148                   "bitWidth": "4"\r
2149                 },\r
2150                 "sticky": {\r
2151                   "description": "Sticky - disallow clearing pwmcmpXip bits",\r
2152                   "bitOffset": "8",\r
2153                   "bitWidth": "1"\r
2154                 },\r
2155                 "zerocmp": {\r
2156                   "description": "Zero - counter resets to zero after match",\r
2157                   "bitOffset": "9",\r
2158                   "bitWidth": "1"\r
2159                 },\r
2160                 "deglitch": {\r
2161                   "description": "Deglitch - latch pwmcmpXip within same cycle",\r
2162                   "bitOffset": "10",\r
2163                   "bitWidth": "1"\r
2164                 },\r
2165                 "enalways": {\r
2166                   "description": "Enable always - run continuously",\r
2167                   "bitOffset": "12",\r
2168                   "bitWidth": "1",\r
2169                   "resetMask": "all",\r
2170                   "resetValue": "0x0"\r
2171                 },\r
2172                 "enoneshot": {\r
2173                   "description": "enable one shot - run one cycle",\r
2174                   "bitOffset": "13",\r
2175                   "bitWidth": "1",\r
2176                   "resetMask": "all",\r
2177                   "resetValue": "0x0"\r
2178                 },\r
2179                 "cmp0center": {\r
2180                   "description": "PWM0 Compare Center",\r
2181                   "bitOffset": "16",\r
2182                   "bitWidth": "1"\r
2183                 },\r
2184                 "cmp1center": {\r
2185                   "description": "PWM1 Compare Center",\r
2186                   "bitOffset": "17",\r
2187                   "bitWidth": "1"\r
2188                 },\r
2189                 "cmp2center": {\r
2190                   "description": "PWM2 Compare Center",\r
2191                   "bitOffset": "18",\r
2192                   "bitWidth": "1"\r
2193                 },\r
2194                 "cmp3center": {\r
2195                   "description": "PWM3 Compare Center",\r
2196                   "bitOffset": "19",\r
2197                   "bitWidth": "1"\r
2198                 },\r
2199                 "cmp0gang": {\r
2200                   "description": "PWM0/PWM1 Compare Gang",\r
2201                   "bitOffset": "24",\r
2202                   "bitWidth": "1"\r
2203                 },\r
2204                 "cmp1gang": {\r
2205                   "description": "PWM1/PWM2 Compare Gang",\r
2206                   "bitOffset": "25",\r
2207                   "bitWidth": "1"\r
2208                 },\r
2209                 "cmp2gang": {\r
2210                   "description": "PWM2/PWM3 Compare Gang",\r
2211                   "bitOffset": "26",\r
2212                   "bitWidth": "1"\r
2213                 },\r
2214                 "cmp3gang": {\r
2215                   "description": "PWM3/PWM0 Compare Gang",\r
2216                   "bitOffset": "27",\r
2217                   "bitWidth": "1"\r
2218                 },\r
2219                 "cmp0ip": {\r
2220                   "description": "PWM0 Interrupt Pending",\r
2221                   "bitOffset": "28",\r
2222                   "bitWidth": "1"\r
2223                 },\r
2224                 "cmp1ip": {\r
2225                   "description": "PWM1 Interrupt Pending",\r
2226                   "bitOffset": "29",\r
2227                   "bitWidth": "1"\r
2228                 },\r
2229                 "cmp2ip": {\r
2230                   "description": "PWM2 Interrupt Pending",\r
2231                   "bitOffset": "30",\r
2232                   "bitWidth": "1"\r
2233                 },\r
2234                 "cmp3ip": {\r
2235                   "description": "PWM3 Interrupt Pending",\r
2236                   "bitOffset": "31",\r
2237                   "bitWidth": "1"\r
2238                 }\r
2239               }\r
2240             },\r
2241             "count": {\r
2242               "description": "Configuration Register",\r
2243               "addressOffset": "0x008"\r
2244             },\r
2245             "scale": {\r
2246               "description": "Scale Register",\r
2247               "addressOffset": "0x010",\r
2248               "fields": {\r
2249                 "value": {\r
2250                   "description": "Compare value",\r
2251                   "bitOffset": "0",\r
2252                   "bitWidth": "16"\r
2253                 }\r
2254               }\r
2255             },\r
2256             "cmp": {\r
2257               "arraySize": "4",\r
2258               "description": "Compare Registers",\r
2259               "addressOffset": "0x020",\r
2260               "fields": {\r
2261                 "value": {\r
2262                   "description": "Compare value",\r
2263                   "bitOffset": "0",\r
2264                   "bitWidth": "16"\r
2265                 }\r
2266               }\r
2267             }\r
2268           },\r
2269           "interrupts": {\r
2270             "pwm1cmp0": {\r
2271               "description": "PWM1 Compare 0 Interrupt",\r
2272               "value": "44"\r
2273             },\r
2274             "pwm1cmp1": {\r
2275               "description": "PWM1 Compare 1 Interrupt",\r
2276               "value": "45"\r
2277             },\r
2278             "pwm1cmp2": {\r
2279               "description": "PWM1 Compare 2 Interrupt",\r
2280               "value": "46"\r
2281             },\r
2282             "pwm1cmp3": {\r
2283               "description": "PWM1 Compare 3 Interrupt",\r
2284               "value": "47"\r
2285             }\r
2286           }\r
2287         },\r
2288         "spi2": {\r
2289           "baseAddress": "0x10034000",\r
2290           "derivedFrom": "spi0",\r
2291           "groupName": "spi",\r
2292           "interrupts": {\r
2293             "spi2": {\r
2294               "description": "SPI2 Interrupt",\r
2295               "value": "7"\r
2296             }\r
2297           }\r
2298         },\r
2299         "pwm2": {\r
2300           "baseAddress": "0x10035000",\r
2301           "derivedFrom": "pwm1",\r
2302           "groupName": "pwm",\r
2303           "interrupts": {\r
2304             "pwm2cmp0": {\r
2305               "description": "PWM2 Compare 0 Interrupt",\r
2306               "value": "48"\r
2307             },\r
2308             "pwm2cmp1": {\r
2309               "description": "PWM2 Compare 1 Interrupt",\r
2310               "value": "49"\r
2311             },\r
2312             "pwm2cmp2": {\r
2313               "description": "PWM2 Compare 2 Interrupt",\r
2314               "value": "50"\r
2315             },\r
2316             "pwm2cmp3": {\r
2317               "description": "PWM2 Compare 3 Interrupt",\r
2318               "value": "51"\r
2319             }\r
2320           }\r
2321         }\r
2322       }\r
2323     }\r
2324   }\r
2325 }