1 /*******************************************************************************
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2 * (c) Copyright 2008-2015 Microsemi SoC Products Group. All rights reserved.
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4 * CoreGPIO bare metal driver implementation.
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6 * SVN $Revision: 7964 $
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7 * SVN $Date: 2015-10-09 18:26:53 +0530 (Fri, 09 Oct 2015) $
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9 #include "core_gpio.h"
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11 #include "hal_assert.h"
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12 #include "coregpio_regs.h"
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14 /*-------------------------------------------------------------------------*//**
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17 #define GPIO_INT_ENABLE_MASK (uint32_t)0x00000008UL
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18 #define OUTPUT_BUFFER_ENABLE_MASK 0x00000004UL
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21 #define NB_OF_GPIO 32
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23 #define CLEAR_ALL_IRQ32 (uint32_t)0xFFFFFFFF
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24 #define CLEAR_ALL_IRQ16 (uint16_t)0xFFFF
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25 #define CLEAR_ALL_IRQ8 (uint8_t)0xFF
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27 /*-------------------------------------------------------------------------*//**
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29 * See "core_gpio.h" for details of how to use this function.
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33 gpio_instance_t * this_gpio,
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35 gpio_apb_width_t bus_width
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39 addr_t cfg_reg_addr = base_addr;
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41 this_gpio->base_addr = base_addr;
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42 this_gpio->apb_bus_width = bus_width;
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44 /* Clear configuration. */
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45 for( i = 0, cfg_reg_addr = base_addr; i < NB_OF_GPIO; ++i )
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47 HW_set_8bit_reg( cfg_reg_addr, 0 );
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50 /* Clear any pending interrupts */
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51 switch( this_gpio->apb_bus_width )
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53 case GPIO_APB_32_BITS_BUS:
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54 HAL_set_32bit_reg( this_gpio->base_addr, IRQ, CLEAR_ALL_IRQ32 );
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57 case GPIO_APB_16_BITS_BUS:
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58 HAL_set_16bit_reg( this_gpio->base_addr, IRQ0, (uint16_t)CLEAR_ALL_IRQ16 );
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59 HAL_set_16bit_reg( this_gpio->base_addr, IRQ1, (uint16_t)CLEAR_ALL_IRQ16 );
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62 case GPIO_APB_8_BITS_BUS:
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63 HAL_set_8bit_reg( this_gpio->base_addr, IRQ0, (uint8_t)CLEAR_ALL_IRQ8 );
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64 HAL_set_8bit_reg( this_gpio->base_addr, IRQ1, (uint8_t)CLEAR_ALL_IRQ8 );
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65 HAL_set_8bit_reg( this_gpio->base_addr, IRQ2, (uint8_t)CLEAR_ALL_IRQ8 );
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66 HAL_set_8bit_reg( this_gpio->base_addr, IRQ3, (uint8_t)CLEAR_ALL_IRQ8 );
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75 /*-------------------------------------------------------------------------*//**
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77 * See "core_gpio.h" for details of how to use this function.
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81 gpio_instance_t * this_gpio,
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86 HAL_ASSERT( port_id < NB_OF_GPIO );
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88 if ( port_id < NB_OF_GPIO )
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90 uint32_t cfg_reg_addr = this_gpio->base_addr;
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91 cfg_reg_addr += (port_id * 4);
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92 HW_set_32bit_reg( cfg_reg_addr, config );
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95 * Verify that the configuration was correctly written. Failure to read
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96 * back the expected value may indicate that the GPIO port was configured
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97 * as part of the hardware flow and cannot be modified through software.
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98 * It may also indicate that the base address passed as parameter to
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99 * GPIO_init() was incorrect.
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101 HAL_ASSERT( HW_get_32bit_reg( cfg_reg_addr ) == config );
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105 /*-------------------------------------------------------------------------*//**
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107 * See "core_gpio.h" for details of how to use this function.
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109 void GPIO_set_outputs
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111 gpio_instance_t * this_gpio,
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115 switch( this_gpio->apb_bus_width )
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117 case GPIO_APB_32_BITS_BUS:
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118 HAL_set_32bit_reg( this_gpio->base_addr, GPIO_OUT, value );
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121 case GPIO_APB_16_BITS_BUS:
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122 HAL_set_16bit_reg( this_gpio->base_addr, GPIO_OUT0, (uint16_t)value );
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123 HAL_set_16bit_reg( this_gpio->base_addr, GPIO_OUT1, (uint16_t)(value >> 16) );
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126 case GPIO_APB_8_BITS_BUS:
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127 HAL_set_8bit_reg( this_gpio->base_addr, GPIO_OUT0, (uint8_t)value );
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128 HAL_set_8bit_reg( this_gpio->base_addr, GPIO_OUT1, (uint8_t)(value >> 8) );
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129 HAL_set_8bit_reg( this_gpio->base_addr, GPIO_OUT2, (uint8_t)(value >> 16) );
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130 HAL_set_8bit_reg( this_gpio->base_addr, GPIO_OUT3, (uint8_t)(value >> 24) );
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139 * Verify that the output register was correctly written. Failure to read back
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140 * the expected value may indicate that some of the GPIOs may not exist due to
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141 * the number of GPIOs selected in the CoreGPIO hardware flow configuration.
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142 * It may also indicate that the base address or APB bus width passed as
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143 * parameter to the GPIO_init() function do not match the hardware design.
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145 HAL_ASSERT( GPIO_get_outputs( this_gpio ) == value );
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148 /*-------------------------------------------------------------------------*//**
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150 * See "core_gpio.h" for details of how to use this function.
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152 uint32_t GPIO_get_inputs
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154 gpio_instance_t * this_gpio
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157 uint32_t gpio_in = 0;
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159 switch( this_gpio->apb_bus_width )
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161 case GPIO_APB_32_BITS_BUS:
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162 gpio_in = HAL_get_32bit_reg( this_gpio->base_addr, GPIO_IN );
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165 case GPIO_APB_16_BITS_BUS:
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166 gpio_in |= HAL_get_16bit_reg( this_gpio->base_addr, GPIO_IN0 );
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167 gpio_in |= (HAL_get_16bit_reg( this_gpio->base_addr, GPIO_IN1 ) << 16);
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170 case GPIO_APB_8_BITS_BUS:
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171 gpio_in |= HAL_get_8bit_reg( this_gpio->base_addr, GPIO_IN0 );
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172 gpio_in |= (HAL_get_8bit_reg( this_gpio->base_addr, GPIO_IN1 ) << 8);
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173 gpio_in |= (HAL_get_8bit_reg( this_gpio->base_addr, GPIO_IN2 ) << 16);
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174 gpio_in |= (HAL_get_8bit_reg( this_gpio->base_addr, GPIO_IN3 ) << 24);
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185 /*-------------------------------------------------------------------------*//**
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187 * See "core_gpio.h" for details of how to use this function.
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189 uint32_t GPIO_get_outputs
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191 gpio_instance_t * this_gpio
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194 uint32_t gpio_out = 0;
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196 switch( this_gpio->apb_bus_width )
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198 case GPIO_APB_32_BITS_BUS:
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199 gpio_out = HAL_get_32bit_reg( this_gpio->base_addr, GPIO_OUT );
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202 case GPIO_APB_16_BITS_BUS:
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203 gpio_out |= HAL_get_16bit_reg( this_gpio->base_addr, GPIO_OUT0 );
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204 gpio_out |= (HAL_get_16bit_reg( this_gpio->base_addr, GPIO_OUT1 ) << 16);
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207 case GPIO_APB_8_BITS_BUS:
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208 gpio_out |= HAL_get_16bit_reg( this_gpio->base_addr, GPIO_OUT0 );
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209 gpio_out |= (HAL_get_16bit_reg( this_gpio->base_addr, GPIO_OUT1 ) << 8);
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210 gpio_out |= (HAL_get_16bit_reg( this_gpio->base_addr, GPIO_OUT2 ) << 16);
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211 gpio_out |= (HAL_get_16bit_reg( this_gpio->base_addr, GPIO_OUT3 ) << 24);
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222 /*-------------------------------------------------------------------------*//**
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224 * See "core_gpio.h" for details of how to use this function.
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226 void GPIO_set_output
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228 gpio_instance_t * this_gpio,
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233 HAL_ASSERT( port_id < NB_OF_GPIO );
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236 switch( this_gpio->apb_bus_width )
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238 case GPIO_APB_32_BITS_BUS:
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240 uint32_t outputs_state;
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242 outputs_state = HAL_get_32bit_reg( this_gpio->base_addr, GPIO_OUT );
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245 outputs_state &= ~(1 << port_id);
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249 outputs_state |= 1 << port_id;
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251 HAL_set_32bit_reg( this_gpio->base_addr, GPIO_OUT, outputs_state );
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254 * Verify that the output register was correctly written. Failure to read back
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255 * the expected value may indicate that some of the GPIOs may not exist due to
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256 * the number of GPIOs selected in the CoreGPIO hardware flow configuration.
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257 * It may also indicate that the base address or APB bus width passed as
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258 * parameter to the GPIO_init() function do not match the hardware design.
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260 HAL_ASSERT( HAL_get_32bit_reg( this_gpio->base_addr, GPIO_OUT ) == outputs_state );
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264 case GPIO_APB_16_BITS_BUS:
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266 uint16_t outputs_state;
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267 uint32_t gpio_out_reg_addr = this_gpio->base_addr + GPIO_OUT_REG_OFFSET + ((port_id >> 4) * 4);
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269 outputs_state = HW_get_16bit_reg( gpio_out_reg_addr );
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272 outputs_state &= ~(1 << (port_id & 0x0F));
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276 outputs_state |= 1 << (port_id & 0x0F);
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278 HW_set_16bit_reg( gpio_out_reg_addr, outputs_state );
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281 * Verify that the output register was correctly written. Failure to read back
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282 * the expected value may indicate that some of the GPIOs may not exist due to
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283 * the number of GPIOs selected in the CoreGPIO hardware flow configuration.
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284 * It may also indicate that the base address or APB bus width passed as
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285 * parameter to the GPIO_init() function do not match the hardware design.
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287 HAL_ASSERT( HW_get_16bit_reg( gpio_out_reg_addr ) == outputs_state );
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291 case GPIO_APB_8_BITS_BUS:
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293 uint8_t outputs_state;
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294 uint32_t gpio_out_reg_addr = this_gpio->base_addr + GPIO_OUT_REG_OFFSET + ((port_id >> 3) * 4);
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296 outputs_state = HW_get_8bit_reg( gpio_out_reg_addr );
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299 outputs_state &= ~(1 << (port_id & 0x07));
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303 outputs_state |= 1 << (port_id & 0x07);
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305 HW_set_8bit_reg( gpio_out_reg_addr, outputs_state );
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308 * Verify that the output register was correctly written. Failure to read back
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309 * the expected value may indicate that some of the GPIOs may not exist due to
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310 * the number of GPIOs selected in the CoreGPIO hardware flow configuration.
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311 * It may also indicate that the base address or APB bus width passed as
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312 * parameter to the GPIO_init() function do not match the hardware design.
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314 HAL_ASSERT( HW_get_8bit_reg( gpio_out_reg_addr ) == outputs_state );
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324 /*-------------------------------------------------------------------------*//**
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326 * See "core_gpio.h" for details of how to use this function.
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328 void GPIO_drive_inout
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330 gpio_instance_t * this_gpio,
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332 gpio_inout_state_t inout_state
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336 uint32_t cfg_reg_addr = this_gpio->base_addr;
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338 HAL_ASSERT( port_id < NB_OF_GPIO );
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340 switch( inout_state )
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342 case GPIO_DRIVE_HIGH:
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343 /* Set output high */
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344 GPIO_set_output( this_gpio, port_id, 1 );
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346 /* Enable output buffer */
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347 cfg_reg_addr = this_gpio->base_addr + (port_id * 4);
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348 config = HW_get_8bit_reg( cfg_reg_addr );
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349 config |= OUTPUT_BUFFER_ENABLE_MASK;
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350 HW_set_8bit_reg( cfg_reg_addr, config );
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353 case GPIO_DRIVE_LOW:
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354 /* Set output low */
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355 GPIO_set_output( this_gpio, port_id, 0 );
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357 /* Enable output buffer */
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358 cfg_reg_addr = this_gpio->base_addr + (port_id * 4);
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359 config = HW_get_8bit_reg( cfg_reg_addr );
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360 config |= OUTPUT_BUFFER_ENABLE_MASK;
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361 HW_set_8bit_reg( cfg_reg_addr, config );
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365 /* Disable output buffer */
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366 cfg_reg_addr = this_gpio->base_addr + (port_id * 4);
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367 config = HW_get_8bit_reg( cfg_reg_addr );
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368 config &= ~OUTPUT_BUFFER_ENABLE_MASK;
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369 HW_set_8bit_reg( cfg_reg_addr, config );
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378 /*-------------------------------------------------------------------------*//**
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380 * See "core_gpio.h" for details of how to use this function.
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382 void GPIO_enable_irq
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384 gpio_instance_t * this_gpio,
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388 uint32_t cfg_value;
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389 uint32_t cfg_reg_addr = this_gpio->base_addr;
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391 HAL_ASSERT( port_id < NB_OF_GPIO );
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393 if ( port_id < NB_OF_GPIO )
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395 cfg_reg_addr += (port_id * 4);
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396 cfg_value = HW_get_8bit_reg( cfg_reg_addr );
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397 cfg_value |= GPIO_INT_ENABLE_MASK;
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398 HW_set_8bit_reg( cfg_reg_addr, cfg_value );
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402 /*-------------------------------------------------------------------------*//**
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404 * See "core_gpio.h" for details of how to use this function.
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406 void GPIO_disable_irq
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408 gpio_instance_t * this_gpio,
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412 uint32_t cfg_value;
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413 uint32_t cfg_reg_addr = this_gpio->base_addr;
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415 HAL_ASSERT( port_id < NB_OF_GPIO );
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417 if ( port_id < NB_OF_GPIO )
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419 cfg_reg_addr += (port_id * 4);
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420 cfg_value = HW_get_8bit_reg( cfg_reg_addr );
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421 cfg_value &= ~GPIO_INT_ENABLE_MASK;
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422 HW_set_8bit_reg( cfg_reg_addr, cfg_value );
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426 /*-------------------------------------------------------------------------*//**
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428 * See "core_gpio.h" for details of how to use this function.
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430 void GPIO_clear_irq
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432 gpio_instance_t * this_gpio,
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436 uint32_t irq_clr_value = ((uint32_t)1) << ((uint32_t)port_id);
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438 switch( this_gpio->apb_bus_width )
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440 case GPIO_APB_32_BITS_BUS:
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441 HAL_set_32bit_reg( this_gpio->base_addr, IRQ, irq_clr_value );
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444 case GPIO_APB_16_BITS_BUS:
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445 HAL_set_16bit_reg( this_gpio->base_addr, IRQ0, irq_clr_value );
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446 HAL_set_16bit_reg( this_gpio->base_addr, IRQ1, irq_clr_value >> 16 );
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449 case GPIO_APB_8_BITS_BUS:
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450 HAL_set_8bit_reg( this_gpio->base_addr, IRQ0, irq_clr_value );
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451 HAL_set_8bit_reg( this_gpio->base_addr, IRQ1, irq_clr_value >> 8 );
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452 HAL_set_8bit_reg( this_gpio->base_addr, IRQ2, irq_clr_value >> 16 );
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453 HAL_set_8bit_reg( this_gpio->base_addr, IRQ3, irq_clr_value >> 24 );
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