1 /*******************************************************************************
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2 * (c) Copyright 2009-2015 Microsemi SoC Products Group. All rights reserved.
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4 * CoreI2C software driver Application Programming Interface.
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5 * This file contains defines and function declarations allowing to interface
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6 * with the CoreI2C software driver.
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8 * SVN $Revision: 7984 $
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9 * SVN $Date: 2015-10-12 12:07:40 +0530 (Mon, 12 Oct 2015) $
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11 /*=========================================================================*//**
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12 @mainpage CoreI2C Bare Metal Driver.
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13 The CoreI2C bare metal software driver supports I2C master and slave
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16 @section intro_sec Introduction
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17 The CoreI2C driver provides a set of functions for controlling the Microsemi
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18 CoreI2C hardware IP. The driver supports up to 16 separate I2C channels per
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19 CoreI2C instance, with common slave address settings shared between channels
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22 Optional features of the CoreI2C allow it operate with I2C based protocols
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23 such as System Management Bus (SMBus), Power Management Bus (PMBus) and
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24 Intelligent Platform Management Interface (IPMI). This driver provides support
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25 for these features when enabled in the CoreI2C IP.
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27 The major features provided by CoreI2C driver are:
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28 - Support for configuring the I2C channels of each CoreI2C peripheral.
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29 - I2C master operations.
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30 - I2C slave operations.
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31 - SMBus related operations.
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33 This driver can be used as part of a bare metal system where no operating
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34 system is available. The driver can be adapted for use as part of an
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35 operating system, but the implementation of the adaptation layer between the
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36 driver and the operating system's driver model is outside the scope of this
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39 @section hw_dependencies Hardware Flow Dependencies
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40 Your application software should configure the CoreI2C driver through
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41 calls to the I2C_init() function for each CoreI2C instance in the
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42 hardware design. The configuration parameters include the CoreI2C hardware
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43 instance base address and other runtime parameters, such as the I2C serial
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44 clock frequency and I2C device address.
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46 Once channel 0 of a CoreI2C peripheral has been initialized via I2C_init(),
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47 any additional channels present should be configured by calling
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48 I2C_channel_init() for each of the remaining channels.
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50 No CoreI2C hardware configuration parameters are used by the driver, apart
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51 from the CoreI2C hardware instance base address. Hence, no additional
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52 configuration files are required to use the driver.
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55 The CoreI2C driver has to enable and disable the generation of interrupts by
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56 CoreI2C at various times when it is operating. This enabling and disabling of
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57 interrupts must be done through the system
\92s interrupt controller. For that
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58 reason, the method of controlling the CoreI2C interrupt is system specific
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59 and it is necessary to customize the I2C_enable_irq() and I2C_disable_irq()
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60 functions. These functions are found in the file i2c_interrupt.c. Their
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61 default implementation fires an assertion to attract attention to the fact
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62 that these functions must be modified.
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64 The implementation of the I2C_enable_irq() function should permit interrupts
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65 generated by a CoreI2C instance to interrupt the processor. The implementation
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66 of the I2C_disable_irq() function should prevent interrupts generated by a
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67 CoreI2C instance from interrupting the processor. Please refer to the provided
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68 example projects for a working implementation of these functions.
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70 The function I2C_register_write_handler() is used to register a write handler
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71 function with the CoreI2C driver that it calls on completion of an I2C write
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72 transaction by the CoreI2C slave. It is your responsibility to create and
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73 register the implementation of this handler function that processes or
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74 trigger the processing of the received data.
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76 The SMBSUS and SMBALERT interrupts are related to the SMBus interface and are
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77 enabled and disabled through I2C_enable_smbus_irq() and
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78 I2C_disable_smbus_irq() respectively. It is your responsibility to create
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79 interrupt handler functions in your application to get the desired response
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80 for the SMBus interrupts.
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82 Note: You must include the path to any application header files that are
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83 included in the i2c_interrupt.c file, as an include path in your
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84 project
\92s compiler settings. The details of how to do this will depend
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85 on your development software.
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88 SMBus related APIs will not have any effect if in CoreI2C hardware
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89 configuration "Generate SMBus Logic" is not enabled. The APIs which will not
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90 give desired results in case SMBus Logic is disabled are:
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94 I2C_enable_smbus_irq()
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95 I2C_disable_smbus_irq()
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96 I2C_suspend_smbus_slave()
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97 I2C_resume_smbus_slave()
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98 I2C_set_smsbus_alert()
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99 I2C_clear_smsbus_alert()
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100 I2C_get_irq_status()
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102 Fixed Baud Rate Values
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103 The serial clock frequency parameter passed to the I2C_init() and
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104 I2C_channel_init() functions may not have any effect if fixed values were
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105 selected for Baud rate in the hardware configuration of CoreI2C. When fixed
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106 values are selected for these baud rates, the driver cannot overwrite
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109 Fixed Slave Address Options Values
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110 The primary slave address parameter passed to the I2C_init() function, and
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111 secondary address value passed to the I2C_set_slave_second_addr() function,
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112 may not have the desired effect if fixed values were selected for the slave 0
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113 address and slave 1 address respectively. Proper operation of this version of
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114 the driver requires the slave addresses to be programmable.
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116 @section theory_op Theory of Operation
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117 The CoreI2C software driver is designed to allow the control of multiple
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118 instances of CoreI2C with one or more I2C channels. Each channel in an
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119 instance of CoreI2C in the hardware design is associated with a single
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120 instance of the i2c_instance_t structure in the software. You must allocate
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121 memory for one unique i2c_instance_t structure instance for each channel of
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122 each CoreI2C hardware instance. The contents of these data structures are
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123 initialised during calls to I2C_init() and if necessary I2C_channel_init().
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124 A pointer to the structure is passed to subsequent driver functions in order
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125 to identify the CoreI2C hardware instance and channel you wish to perform the
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126 requested operation.
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128 Note: Do not attempt to directly manipulate the contents of i2c_instance_t
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129 structures. These structures are only intended to be modified by the driver
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132 The CoreI2C driver functions are grouped into the following categories:
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133 - Initialization and configuration functions
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134 - Interrupt control
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135 - I2C slave addressing functions
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136 - I2C master operations functions to handle write, read and write-read
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138 - I2C slave operations functions to handle write, read and write-read
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140 - Mixed master-slave operations
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141 - SMBus interface configuration and control.
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143 Initialization and Configuration
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144 The CoreI2C device is first initialized through a call to the I2C_init()
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145 function. Since each CoreI2C peripheral supports up to 16 channels, an
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146 additional function, I2C_channel_init(), is required to initialize the
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147 remaining channels with their own data structures.
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149 I2C_init() initializes channel 0 of a CoreI2C and the i2c_instance_t for
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150 channel 0 acts as the basis for further channel initialization as the
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151 hardware base address and I2C serial address are same across all the
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152 channels. I2C_init() must be called before any other I2C driver function
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153 calls. The I2C_init() call for each CoreI2C takes the I2C serial address
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154 assigned to the I2C and the serial clock divider to be used to generate its
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155 I2C clock as configuration parameters.
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157 I2C_channel_init() takes as input parameters a pointer to the CoreI2C
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158 i2c_instance_t which has been initialized via I2C_init() and a pointer to a
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159 separate i2c_instance_t which represents this new channel. Another input
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160 parameter which is required by this function is serial clock divider which
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161 generates its I2C clock.
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164 The CoreI2C driver is interrupt driven and it uses each channels INT
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165 interrupt to drive the state machine which is at the heart of the driver.
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166 The application is responsible for providing the link between the interrupt
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167 generating hardware and the CoreI2C interrupt handler and must ensure that
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168 the I2C_isr() function is called with the correct i2c_instance_t structure
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169 pointer for the CoreI2C channel initiating the interrupt.
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171 The driver enables and disables the generation of INT interrupts by CoreI2C
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172 at various times when it is operating through the user supplied
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173 I2C_enable_irq() and I2C_disable_irq() functions.
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175 The function I2C_register_write_handler() is used to register a write
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176 handler function with the CoreI2C driver which is called on completion
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177 of an I2C write transaction by the CoreI2C slave. It is the user
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178 applications responsibility to create and register the implementation of
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179 this handler function that processes or triggers the processing of the
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182 The other two interrupt sources in the CoreI2C, are related to SMBus
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183 operation and are enabled and disabled through I2C_enable_smbus_irq() and
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184 I2C_disable_smbus_irq() respectively. Due to the application specific
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185 nature of the response to SMBus interrupts, you must design interrupt
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186 handler functions in the application to get the desired behaviour for
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187 SMBus related interrupts.
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189 If enabled, the SMBA_INT signal from the CoreI2C is asserted if an
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190 SMBALERT condition is signalled on the SMBALERT_NI input for the channel.
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192 If enabled, the SMBS_INT signal from the CoreI2C is asserted if an
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193 SMBSUSPEND condition is signalled on the SMBSUS_NI input for the channel.
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195 I2C slave addressing functions
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196 A CoreI2C peripheral can respond to three slave addresses:
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197 - Slave address 0 - This is the primary slave address which is used for
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198 accessing a CoreI2C channel when it acts as a slave in
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199 I2C transactions. You must configure the primary slave
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200 address via I2C_init().
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202 - Slave address 1 - This is the secondary slave address which might be
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203 required in certain application specific scenarios.
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204 The secondary slave address can be configured via
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205 I2C_set_slave_second_addr() and disabled via
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206 I2C_disable_slave_second_addr().
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208 - General call address - A CoreI2C slave can be configured to respond to
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209 a broadcast command by a master transmitting the
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210 general call address of 0x00. Use the I2C_set_gca()
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211 function to enable the slave to respond to the general
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212 call address. If the CoreI2C slave is not required to
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213 respond to the general call address, disable this
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214 address by calling I2C_clear_gca().
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216 Note: All channels on a CoreI2C instance share the same slave address logic.
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217 This means that they cannot have separate slave addresses and rely on
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218 the separate physical I2C bus connections to distinguish them.
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221 The I2C driver is designed to handle three types of I2C transaction:
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224 Write-read transactions
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227 The master I2C device initiates a write transaction by sending a START bit
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228 as soon as the bus becomes free. The START bit is followed by the 7-bit
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229 serial address of the target slave device followed by the read/write bit
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230 indicating the direction of the transaction. The slave acknowledges the
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231 receipt of it's address with an acknowledge bit. The master sends data one
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232 byte at a time to the slave, which must acknowledge receipt of each byte
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233 for the next byte to be sent. The master sends a STOP bit to complete the
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234 transaction. The slave can abort the transaction by replying with a
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235 non-acknowledge bit instead of an acknowledge.
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237 The application programmer can choose not to send a STOP bit at the end of
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238 the transaction causing the next transaction to begin with a repeated
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242 The master I2C device initiates a read transaction by sending a START bit
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243 as soon as the bus becomes free. The START bit is followed by the 7-bit
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244 serial address of the target slave device followed by the read/write bit
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245 indicating the direction of the transaction. The slave acknowledges
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246 receipt of it's slave address with an acknowledge bit. The slave sends
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247 data one byte at a time to the master, which must acknowledge receipt of
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248 each byte for the next byte to be sent. The master sends a non-acknowledge
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249 bit following the last byte it wishes to read followed by a STOP bit.
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251 The application programmer can choose not to send a STOP bit at the end of
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252 the transaction causing the next transaction to begin with a repeated
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255 Write-read transaction
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256 The write-read transaction is a combination of a write transaction
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257 immediately followed by a read transaction. There is no STOP bit between
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258 the write and read phases of a write-read transaction. A repeated START
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259 bit is sent between the write and read phases.
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261 Whilst the write handler is being executed, the slave holds the clock line
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262 low to stretch the clock until the response is ready.
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264 The write-read transaction is typically used to send a command or offset
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265 in the write transaction specifying the logical data to be transferred
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266 during the read phase.
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268 The application programmer can choose not to send a STOP bit at the end of
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269 the transaction causing the next transaction to begin with a repeated
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273 The application can use the I2C_write(), I2C_read() and I2C_write_read()
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274 functions to initiate an I2C bus transaction. The application can then wait
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275 for the transaction to complete using the I2C_wait_complete() function
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276 or poll the status of the I2C transaction using the I2C_get_status()
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277 function until it returns a value different from I2C_IN_PROGRESS. The
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278 I2C_system_tick() function can be used to set a time base for the
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279 I2C_wait_complete() function
\92s time out delay.
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282 The configuration of the I2C driver to operate as an I2C slave requires
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283 the use of the following functions:
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284 I2C_set_slave_tx_buffer()
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285 I2C_set_slave_rx_buffer()
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286 I2C_set_slave_mem_offset_length()
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287 I2C_register_write_handler()
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290 Use of all functions is not required if the slave I2C does not need to support
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291 all types of I2C read transactions. The subsequent sections list the functions
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292 that must be used to support each transaction type.
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294 Responding to read transactions
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295 The following functions are used to configure the CoreI2C driver to
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296 respond to I2C read transactions:
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297 I2C_set_slave_tx_buffer()
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300 The function I2C_set_slave_tx_buffer() specifies the data buffer that
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301 will be transmitted when the I2C slave is the target of an I2C read
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302 transaction. It is then up to the application to manage the content of
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303 that buffer to control the data that will be transmitted to the I2C
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304 master as a result of the read transaction.
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306 The function I2C_enable_slave() enables the I2C hardware instance
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307 to respond to I2C transactions. It must be called after the I2C driver
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308 has been configured to respond to the required transaction types.
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310 Responding to write transactions
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311 The following functions are used to configure the I2C driver to respond
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312 to I2C write transactions:
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313 I2C_set_slave_rx_buffer()
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314 I2C_register_write_handler()
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317 The function I2C_set_slave_rx_buffer() specifies the data buffer that
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318 will be used to store the data received by the I2C slave when it is the
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319 target an I2C write transaction.
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321 The function I2C_register_write_handler() specifies the handler function
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322 that must be called on completion of the I2C write transaction. It is this
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323 handler function that processes or triggers the processing of the received
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326 The function I2C_enable_slave() enables the I2C hardware instance
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327 to respond to I2C transactions. It must be called after the I2C driver
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328 has been configured to respond to the required transaction types.
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330 Responding to write-read transactions
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331 The following functions are used to configure the CoreI2C driver to
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332 respond to write-read transactions:
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333 I2C_set_slave_mem_offset_length()
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334 I2C_set_slave_tx_buffer()
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335 I2C_set_slave_rx_buffer()
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336 I2C_register_write_handler()
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339 The function I2C_set_slave_mem_offset_length() specifies the number of
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340 bytes expected by the I2C slave during the write phase of the write-read
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343 The function I2C_set_slave_tx_buffer() specifies the data that will be
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344 transmitted to the I2C master during the read phase of the write-read
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345 transaction. The value received by the I2C slave during the write phase of
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346 the transaction will be used as an index into the transmit buffer
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347 specified by this function to decide which part of the transmit buffer
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348 will be transmitted to the I2C master as part of the read phase of the
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349 write-read transaction.
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351 The function I2C_set_slave_rx_buffer() specifies the data buffer that
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352 will be used to store the data received by the I2C slave during the write
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353 phase of the write-read transaction. This buffer must be at least large
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354 enough to accommodate the number of bytes specified through the
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355 I2C_set_slave_mem_offset_length() function.
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357 The function I2C_register_write_handler() can optionally be used to
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358 specify a handler function that is called on completion of the write phase
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359 of the I2C write-read transaction. If a handler function is registered, it
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360 is responsible for processing the received data in the slave receive
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361 buffer and populating the slave transmit buffer with the data that will be
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362 transmitted to the I2C master as part of the read phase of the write-read
\r
365 The function I2C_enable_slave() enables the CoreI2C hardware instance to
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366 respond to I2C transactions. It must be called after the CoreI2C driver
\r
367 has been configured to respond to the required transaction types.
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369 Mixed Master-Slave Operations
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370 The CoreI2C device supports mixed master and slave operations. If the
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371 CoreI2C slave has a transaction in progress and your application attempts to
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372 begin a master mode transaction, the CoreI2C driver queu3es the master mode
\r
373 transaction until the bus is released and the CoreI2C can switch to master
\r
374 mode and acquire the bus. The CoreI2C master then starts the previously
\r
375 queued master transaction.
\r
378 The CoreI2C driver enables the CoreI2C peripheral
\92s SMBus functionality
\r
379 using the I2C_smbus_init() function.
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381 The I2C_suspend_smbus_slave() function is used, with a master mode CoreI2C,
\r
382 to force slave devices on the SMBus to enter their power-down/suspend mode.
\r
383 The I2C_resume_smbus_slave() function is used to end the suspend operation
\r
386 The I2C_reset_smbus() function is used, with a master mode CoreI2C, to force
\r
387 all devices on the SMBus to reset their SMBUs interface.
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389 The I2C_set_smsbus_alert() function is used, by a slave mode CoreI2C, to
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390 force communication with the SMBus master. Once communications with the
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391 master is initiated, the I2C_clear_smsbus_alert() function is used to clear
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392 the alert condition.
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394 The I2C_enable_smbus_irq() and I2C_disable_smbus_irq() functions are used to
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395 enable and disable the SMBSUS and SMBALERT SMBus interrupts.
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397 *//*=========================================================================*/
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399 #ifndef CORE_I2C_H_
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400 #define CORE_I2C_H_
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402 #include "cpu_types.h"
\r
407 /*-------------------------------------------------------------------------*//**
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408 The I2C_RELEASE_BUS constant is used to specify the options parameter to
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409 functions I2C_read(), I2C_write() and I2C_write_read() to indicate
\r
410 that a STOP bit must be generated at the end of the I2C transaction to release
\r
413 #define I2C_RELEASE_BUS 0x00u
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415 /*-------------------------------------------------------------------------*//**
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416 The I2C_HOLD_BUS constant is used to specify the options parameter to
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417 functions I2C_read(), I2C_write() and I2C_write_read() to indicate
\r
418 that a STOP bit must not be generated at the end of the I2C transaction in
\r
419 order to retain the bus ownership. This causes the next transaction to
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420 begin with a repeated START bit and no STOP bit between the transactions.
\r
422 #define I2C_HOLD_BUS 0x01u
\r
424 /*-------------------------------------------------------------------------*//**
\r
425 The following constants specify the interrupt identifier number which will be
\r
426 solely used by driver API. This has nothing to do with hardware interrupt line.
\r
427 I2C_INT_IRQ is the primary interrupt signal which drives the state machine
\r
428 of the CoreI2C driver. The I2C_SMBALERT_IRQ and I2C_SMBUS_IRQ are used by
\r
429 SMBus interrupt enable and disable functions. These IRQ numbers are also used
\r
430 by I2C_get_irq_status().
\r
432 #define I2C_NO_IRQ 0x00u
\r
433 #define I2C_SMBALERT_IRQ 0x01u
\r
434 #define I2C_SMBSUS_IRQ 0x02u
\r
435 #define I2C_INTR_IRQ 0x04u
\r
437 /*-------------------------------------------------------------------------*//**
\r
438 The I2C_NO_TIMEOUT constant is used as parameter to the I2C_wait_complete()
\r
439 function to indicate that the wait for completion of the transaction should
\r
442 #define I2C_NO_TIMEOUT 0u
\r
444 /*-------------------------------------------------------------------------*//**
\r
445 The i2c_channel_number_t type is used to specify the channel number of a
\r
448 typedef enum i2c_channel_number {
\r
449 I2C_CHANNEL_0 = 0u,
\r
465 I2C_MAX_CHANNELS = 16u
\r
466 } i2c_channel_number_t;
\r
468 /*-------------------------------------------------------------------------*//**
\r
469 The i2c_clock_divider_t type is used to specify the divider to be applied
\r
470 to the I2C PCLK or BCLK signal in order to generate the I2C clock.
\r
471 The I2C_BCLK_DIV_8 value selects a clock frequency based on division of BCLK,
\r
472 all other values select a clock frequency based on division of PCLK.
\r
474 typedef enum i2c_clock_divider {
\r
475 I2C_PCLK_DIV_256 = 0u,
\r
483 } i2c_clock_divider_t;
\r
485 /*-------------------------------------------------------------------------*//**
\r
486 The i2c_status_t type is used to report the status of I2C transactions.
\r
488 typedef enum i2c_status
\r
496 /*-------------------------------------------------------------------------*//**
\r
497 The i2c_slave_handler_ret_t type is used by slave write handler functions
\r
498 to indicate whether or not the received data buffer should be released.
\r
500 typedef enum i2c_slave_handler_ret {
\r
501 I2C_REENABLE_SLAVE_RX = 0u,
\r
502 I2C_PAUSE_SLAVE_RX = 1u
\r
503 } i2c_slave_handler_ret_t;
\r
505 typedef struct i2c_instance i2c_instance_t ;
\r
507 /*-------------------------------------------------------------------------*//**
\r
508 Slave write handler functions prototype.
\r
509 ------------------------------------------------------------------------------
\r
510 This defines the function prototype that must be followed by I2C slave write
\r
511 handler functions. These functions are registered with the CoreI2C driver
\r
512 through the I2C_register_write_handler() function.
\r
514 Declaring and Implementing Slave Write Handler Functions:
\r
515 Slave write handler functions should follow the following prototype:
\r
516 i2c_slave_handler_ret_t write_handler
\r
518 i2c_instance_t *instance, uint8_t * data, uint16_t size
\r
521 The instance parameter is a pointer to the i2c_instance_t for which this
\r
522 slave write handler has been declared.
\r
524 The data parameter is a pointer to a buffer (received data buffer) holding
\r
525 the data written to the I2C slave.
\r
527 Defining the macro INCLUDE_SLA_IN_RX_PAYLOAD causes the driver to insert the
\r
528 actual address used to access the slave as the first byte in the buffer.
\r
529 This allows applications tailor their response based on the actual address
\r
530 used to access the slave (primary address, secondary address or GCA).
\r
532 The size parameter is the number of bytes held in the received data buffer.
\r
533 Handler functions must return one of the following values:
\r
534 I2C_REENABLE_SLAVE_RX
\r
535 I2C_PAUSE_SLAVE_RX.
\r
537 If the handler function returns I2C_REENABLE_SLAVE_RX, the driver releases
\r
538 the received data buffer and allows further I2C write transactions to the
\r
539 I2C slave to take place.
\r
541 If the handler function returns I2C_PAUSE_SLAVE_RX, the I2C slave responds
\r
542 to subsequent write requests with a non-acknowledge bit (NACK), until the
\r
543 received data buffer content has been processed by some other part of the
\r
544 software application.
\r
546 A call to I2C_enable_slave() is required at some point after returning
\r
547 I2C_PAUSE_SLAVE_RX in order to release the received data buffer so it can
\r
548 be used to store data received by subsequent I2C write transactions.
\r
550 typedef i2c_slave_handler_ret_t (*i2c_slave_wr_handler_t)(i2c_instance_t *instance, uint8_t *, uint16_t );
\r
553 /*-------------------------------------------------------------------------*//**
\r
555 ------------------------------------------------------------------------------
\r
556 This structure is used to identify the various CoreI2C hardware instances in
\r
557 your system and the I2C channels within them. Your application software should
\r
558 declare one instance of this structure for each channel of each instance of
\r
559 CoreI2C in your system. The functions I2C_init() and I2C_channel_init()
\r
560 initialize this structure depending on whether it is channel 0 or one of the
\r
561 additional channels respectively. A pointer to an initialized instance of the
\r
562 structure should be passed as the first parameter to the CoreI2C driver
\r
563 functions, to identify which CoreI2C hardware instance and channel should
\r
564 perform the requested operation.
\r
566 The contents of this data structure should not be modified or used outside of
\r
567 the CoreI2C driver. Software using the CoreI2C driver should only need to
\r
568 create one single instance of this data structure for each channel of each
\r
569 CoreI2C hardware instance in the system then pass a pointer to these data
\r
570 structures with each call to the CoreI2C driver in order to identify the
\r
571 CoreI2C hardware instance it wishes to use.
\r
573 struct i2c_instance
\r
575 addr_t base_address;
\r
576 uint_fast8_t ser_address;
\r
578 /* Transmit related info:*/
\r
579 uint_fast8_t target_addr;
\r
581 /* Current transaction type (WRITE, READ, RANDOM_READ)*/
\r
582 uint8_t transaction;
\r
584 uint_fast16_t random_read_addr;
\r
588 /* Master TX INFO: */
\r
589 const uint8_t * master_tx_buffer;
\r
590 uint_fast16_t master_tx_size;
\r
591 uint_fast16_t master_tx_idx;
\r
594 /* Master RX INFO: */
\r
595 uint8_t * master_rx_buffer;
\r
596 uint_fast16_t master_rx_size;
\r
597 uint_fast16_t master_rx_idx;
\r
599 /* Master Status */
\r
600 volatile i2c_status_t master_status;
\r
601 uint32_t master_timeout_ms;
\r
603 /* Slave TX INFO */
\r
604 const uint8_t * slave_tx_buffer;
\r
605 uint_fast16_t slave_tx_size;
\r
606 uint_fast16_t slave_tx_idx;
\r
608 /* Slave RX INFO */
\r
609 uint8_t * slave_rx_buffer;
\r
610 uint_fast16_t slave_rx_size;
\r
611 uint_fast16_t slave_rx_idx;
\r
613 volatile i2c_status_t slave_status;
\r
616 uint_fast8_t slave_mem_offset_length;
\r
617 i2c_slave_wr_handler_t slave_write_handler;
\r
618 uint8_t is_slave_enabled;
\r
620 /* user specific data */
\r
621 void *p_user_data ;
\r
623 /* I2C bus status */
\r
624 uint8_t bus_status;
\r
626 /* Is transaction pending flag */
\r
627 uint8_t is_transaction_pending;
\r
629 /* I2C Pending transaction */
\r
630 uint8_t pending_transaction;
\r
633 /*-------------------------------------------------------------------------*//**
\r
634 I2C initialization routine.
\r
635 ------------------------------------------------------------------------------
\r
636 The I2C_init() function is used to configure channel 0 of a CoreI2C instance.
\r
637 It sets the base hardware address which is used to locate the CoreI2C instance
\r
638 in memory and also used internally by I2C_channel_init() to calculate the
\r
639 register addresses for any additional channels. The slave serial address set
\r
640 is shared by all channels on a CoreI2C instance.
\r
642 If only one channel is configured in a CoreI2C, the address of the
\r
643 i2c_instance_t used in I2C_Init() will also be used in subsequent calls to the
\r
644 CoreI2C driver functions. If more than one channel is configured in the
\r
645 CoreI2C, I2C_channel_init() will be called after I2C_init(), which initializes
\r
646 the i2c_instance_t data structure for a specific channel.
\r
647 ------------------------------------------------------------------------------
\r
649 Pointer to the i2c_instance_t data structure which will hold all data
\r
650 related to channel 0 of the CoreI2C instance being initialized. A pointer
\r
651 to this structure will be used in all subsequent calls to CoreI2C driver
\r
652 functions which are to operate on channel 0 of this CoreI2C instance.
\r
654 @param base_address:
\r
655 Base address in the processor's memory map of the registers of the CoreI2C
\r
656 instance being initialized.
\r
658 @param ser_address:
\r
659 This parameter sets the primary I2C serial address (SLAVE0 address) for the
\r
660 CoreI2C being initialized. It is the principal I2C bus address to which the
\r
661 CoreI2C instance will respond. CoreI2C can operate in master mode or slave
\r
662 mode and the serial address is significant only in the case of I2C slave
\r
663 mode. In master mode, CoreI2C does not require a serial address and the
\r
664 value of this parameter is not important. If you do not intend to use the
\r
665 CoreI2C device in slave mode, then any dummy slave address value can be
\r
666 provided to this parameter. However, in systems where the CoreI2C may be
\r
667 expected to switch from master mode to slave mode, it is advisable to
\r
668 initialize the CoreI2C device with a valid serial slave address.
\r
670 You need to call the I2C_init() function whenever it is required to change
\r
671 the primary slave address as there is no separate function to set the
\r
672 primary slave address of the I2C device. The serial address being
\r
673 initialized through this function is basically the primary slave address or
\r
674 slave address0. I2C_set_slave_second_addr() can be used to set the
\r
675 secondary slave address or slave address 1.
\r
676 Note : ser_address parameter does not have any affect if fixed slave
\r
677 address is enabled in CoreI2C hardware design. CoreI2C will
\r
678 be always addressed with the hardware configured fixed slave
\r
680 Note : ser_address parameter will not have any affect if the CoreI2C
\r
681 instance is only used in master mode.
\r
683 @param ser_clock_speed:
\r
684 This parameter sets the I2C serial clock frequency. It selects the divider
\r
685 that will be used to generate the serial clock from the APB PCLK or from
\r
686 the BCLK. It can be one of the following:
\r
695 Note: serial_clock_speed value will have no affect if Fixed baud rate is
\r
696 enabled in CoreI2C hardware instance configuration dialogue window.
\r
697 The fixed baud rate divider value will override the value
\r
698 passed as parameter in this function.
\r
699 Note: serial_clock_speed value is not critical for devices that only operate
\r
700 as slaves and can be set to any of the above values.
\r
706 #define COREI2C_BASE_ADDR 0xC0000000u
\r
707 #define COREI2C_SER_ADDR 0x10u
\r
709 i2c_instance_t g_i2c_inst;
\r
711 void system_init( void )
\r
713 I2C_init( &g_i2c_inst, COREI2C_BASE_ADDR, COREI2C_SER_ADDR,
\r
714 I2C_PCLK_DIV_256 );
\r
720 i2c_instance_t * this_i2c,
\r
721 addr_t base_address,
\r
722 uint8_t ser_address,
\r
723 i2c_clock_divider_t ser_clock_speed
\r
726 /*-------------------------------------------------------------------------*//**
\r
727 I2C channel initialization routine.
\r
728 ------------------------------------------------------------------------------
\r
729 The I2C_channel_init() function initializes and configures hardware and data
\r
730 structures of one of the additional channels of a CoreI2C instance.
\r
731 I2C_init() must be called before calling this function to set the CoreI2C
\r
732 instance hardware base address and I2C serial address. I2C_channel_init() also
\r
733 initializes I2C serial clock divider to set the serial clock baud rate.
\r
734 The pointer to data structure i2c_instance_t used for a particular channel
\r
735 will be used as an input parameter to subsequent CoreI2C driver functions
\r
736 which operate on this channel.
\r
737 ------------------------------------------------------------------------------
\r
738 @param this_i2c_channel
\r
739 Pointer to the i2c_instance_t data structure holding all data related to the
\r
740 CoreI2C channel being initialized. A pointer to the same data structure will
\r
741 be used in subsequent calls to the CoreI2C driver functions in order to
\r
742 identify the CoreI2C channel instance that should perform the operation
\r
743 implemented by the called driver function.
\r
746 This is a pointer to an i2c_instance_t structure previously initialized by
\r
747 I2C_init(). It holds information regarding the hardware base address and
\r
748 I2C serial address for the CoreI2C containing the channel to be
\r
749 initialized. This information is required by I2C_channel_init() to
\r
750 initialize the i2c_instance_t structure pointed to by this_i2c_channel as
\r
751 all channels in a CoreI2C instance share the same base address and serial
\r
752 address. It is very important that the i2c_instance_t structure pointed to
\r
753 by this_i2c has been previously initialized with a call to I2C_init().
\r
755 @param channel_number:
\r
756 This parameter of type i2c_channel_number_t identifies the channel to be
\r
759 @param ser_clock_speed:
\r
760 This parameter sets the I2C serial clock frequency. It selects the divider
\r
761 that will be used to generate the serial clock from the APB PCLK or from
\r
762 the BCLK. It can be one of the following:
\r
772 Note: serial_clock_speed value will have no affect if Fixed baud rate is
\r
773 enabled in CoreI2C hardware instance configuration dialogue window.
\r
774 The fixed baud rate divider value will supersede the value
\r
775 passed as parameter in this function.
\r
777 Note: ser_clock_speed value is not critical for devices that only operate
\r
778 as slaves and can be set to any of the above values.
\r
783 #define COREI2C_BASE_ADDR 0xC0000000u
\r
784 #define COREI2C_SER_ADDR 0x10u
\r
785 #define DATA_LENGTH 16u
\r
787 i2c_instance_t g_i2c_inst;
\r
788 i2c_instance_t g_i2c_channel_1_inst;
\r
790 uint8_t tx_buffer[DATA_LENGTH];
\r
791 uint8_t write_length = DATA_LENGTH;
\r
793 void system_init( void )
\r
795 uint8_t target_slave_addr = 0x12;
\r
797 // Initialize base CoreI2C instance
\r
798 I2C_init( &g_i2c_inst, COREI2C_BASE_ADDR, COREI2C_SER_ADDR,
\r
799 I2C_PCLK_DIV_256 );
\r
801 // Initialize CoreI2C channel 1 with different clock speed
\r
802 I2C_channel_init( &g_i2c_channel_1_inst, &g_i2c_inst, I2C_CHANNEL_1,
\r
803 I2C_PCLK_DIV_224 );
\r
805 // Write data to Channel 1 of CoreI2C instance.
\r
806 I2C_write( &g_i2c_channel_1_inst, target_slave_addr, tx_buffer,
\r
807 write_length, I2C_RELEASE_BUS );
\r
812 void I2C_channel_init
\r
814 i2c_instance_t * this_i2c_channel,
\r
815 i2c_instance_t * this_i2c,
\r
816 i2c_channel_number_t channel_number,
\r
817 i2c_clock_divider_t ser_clock_speed
\r
820 /*------------------------------------------------------------------------------
\r
821 CoreI2C interrupt service routine.
\r
822 ------------------------------------------------------------------------------
\r
823 The function I2C_isr is the CoreI2C interrupt service routine. User must
\r
824 call this function from their application level CoreI2C interrupt handler
\r
825 function. This function runs the I2C state machine based on previous and
\r
827 ------------------------------------------------------------------------------
\r
829 The this_i2c parameter is a pointer to the i2c_instance_t data structure
\r
830 holding all data related to a specific CoreI2C channel. For example, if only
\r
831 one channel is initialized, this data structure holds the information of
\r
832 channel 0 of the instantiated CoreI2C hardware.
\r
839 #define COREI2C_BASE_ADDR 0xC0000000u
\r
840 #define COREINTERRUPT_BASE_ADDR 0xCC000000u
\r
841 #define COREI2C_SER_ADDR 0x10u
\r
842 #define I2C_IRQ_NB 2u
\r
844 i2c_instance_t g_i2c_inst;
\r
846 void core_i2c_isr( void )
\r
848 I2C_isr( &g_i2c_inst );
\r
853 CIC_init( COREINTERRUPT_BASE_ADDR );
\r
855 CIC_set_irq_handler( I2C_IRQ_NB, core_i2c_isr );
\r
856 I2C_init( &g_i2c_inst, COREI2C_BASE_ADDR, COREI2C_SER_ADDR,
\r
857 I2C_PCLK_DIV_256 );
\r
858 NVIC_enable_interrupt( NVIC_IRQ_0 );
\r
864 i2c_instance_t * this_i2c
\r
867 /*******************************************************************************
\r
868 *******************************************************************************
\r
870 * Master specific functions
\r
872 * The following functions are only used within an I2C master's implementation.
\r
875 /*-------------------------------------------------------------------------*//**
\r
876 I2C master write function.
\r
877 ------------------------------------------------------------------------------
\r
878 This function initiates an I2C master write transaction. This function returns
\r
879 immediately after initiating the transaction. The content of the write buffer
\r
880 passed as parameter should not be modified until the write transaction
\r
881 completes. It also means that the memory allocated for the write buffer should
\r
882 not be freed or should not go out of scope before the write completes. You can
\r
883 check for the write transaction completion using the I2C_status() function.
\r
884 ------------------------------------------------------------------------------
\r
886 The this_i2c parameter is a pointer to the i2c_instance_t data structure
\r
887 holding all data related to a specific CoreI2C channel. For example, if only
\r
888 one channel is initialized, this data structure holds the information of
\r
889 channel 0 of the instantiated CoreI2C hardware.
\r
891 @param serial_addr:
\r
892 This parameter specifies the serial address of the target I2C device.
\r
894 @param write_buffer:
\r
895 This parameter is a pointer to a buffer holding the data to be written to
\r
896 the target I2C device.
\r
897 Care must be taken not to release the memory used by this buffer before the
\r
898 write transaction completes. For example, it is not appropriate to return
\r
899 from a function allocating this buffer as an auto array variable before the
\r
900 write transaction completes as this would result in the buffer's memory
\r
901 being de-allocated from the stack when the function returns. This memory
\r
902 could then be subsequently reused and modified causing unexpected data to
\r
903 be written to the target I2C device.
\r
906 Number of bytes held in the write_buffer to be written to the target I2C
\r
910 The options parameter is used to indicate if the I2C bus should be released
\r
911 on completion of the write transaction. Using the I2C_RELEASE_BUS
\r
912 constant for the options parameter causes a STOP bit to be generated at the
\r
913 end of the write transaction causing the bus to be released for other I2C
\r
914 devices to use. Using the I2C_HOLD_BUS constant as options parameter
\r
915 prevents a STOP bit from being generated at the end of the write
\r
916 transaction, preventing other I2C devices from initiating a bus transaction.
\r
922 #define COREI2C_BASE_ADDR 0xC0000000u
\r
923 #define COREI2C_DUMMY_ADDR 0x10u
\r
924 #define DATA_LENGTH 16u
\r
926 i2c_instance_t g_i2c_inst;
\r
928 uint8_t tx_buffer[DATA_LENGTH];
\r
929 uint8_t write_length = DATA_LENGTH;
\r
933 uint8_t target_slave_addr = 0x12;
\r
934 i2c_status_t status;
\r
936 // Initialize base CoreI2C instance
\r
937 I2C_init( &g_i2c_inst, COREI2C_BASE_ADDR, COREI2C_DUMMY_ADDR,
\r
938 I2C_PCLK_DIV_256 );
\r
940 // Write data to Channel 0 of CoreI2C instance.
\r
941 I2C_write( &g_i2c_inst, target_slave_addr, tx_buffer, write_length,
\r
944 // Wait for completion and record the outcome
\r
945 status = I2C_wait_complete( &g_i2c_inst, I2C_NO_TIMEOUT );
\r
951 i2c_instance_t * this_i2c,
\r
952 uint8_t serial_addr,
\r
953 const uint8_t * write_buffer,
\r
954 uint16_t write_size,
\r
958 /*-------------------------------------------------------------------------*//**
\r
960 ------------------------------------------------------------------------------
\r
961 This function initiates an I2C master read transaction. This function returns
\r
962 immediately after initiating the transaction.
\r
963 The contents of the read buffer passed as parameter should not be modified
\r
964 until the read transaction completes. It also means that the memory allocated
\r
965 for the read buffer should not be freed or should not go out of scope before
\r
966 the read completes. You can check for the read transaction completion using
\r
967 the I2C_status() function.
\r
968 ------------------------------------------------------------------------------
\r
970 The this_i2c parameter is a pointer to the i2c_instance_t data structure
\r
971 holding all data related to a specific CoreI2C channel. For example, if only
\r
972 one channel is initialized, this data structure holds the information of
\r
973 channel 0 of the instantiated CoreI2C hardware.
\r
975 @param serial_addr:
\r
976 This parameter specifies the serial address of the target I2C device.
\r
979 This is a pointer to a buffer where the data received from the target device
\r
981 Care must be taken not to release the memory used by this buffer before the
\r
982 read transaction completes. For example, it is not appropriate to return
\r
983 from a function allocating this buffer as an auto array variable before the
\r
984 read transaction completes as this would result in the buffer's memory being
\r
985 de-allocated from the stack when the function returns. This memory could
\r
986 then be subsequently reallocated resulting in the read transaction
\r
987 corrupting the newly allocated memory.
\r
990 This parameter specifies the number of bytes to read from the target device.
\r
991 This size must not exceed the size of the read_buffer buffer.
\r
994 The options parameter is used to indicate if the I2C bus should be released
\r
995 on completion of the read transaction. Using the I2C_RELEASE_BUS
\r
996 constant for the options parameter causes a STOP bit to be generated at the
\r
997 end of the read transaction causing the bus to be released for other I2C
\r
998 devices to use. Using the I2C_HOLD_BUS constant as options parameter
\r
999 prevents a STOP bit from being generated at the end of the read transaction,
\r
1000 preventing other I2C devices from initiating a bus transaction.
\r
1006 #define COREI2C_BASE_ADDR 0xC0000000u
\r
1007 #define COREI2C_DUMMY_ADDR 0x10u
\r
1008 #define DATA_LENGTH 16u
\r
1010 i2c_instance_t g_i2c_inst;
\r
1012 uint8_t rx_buffer[DATA_LENGTH];
\r
1013 uint8_t read_length = DATA_LENGTH;
\r
1017 uint8_t target_slave_addr = 0x12;
\r
1018 i2c_status_t status;
\r
1020 // Initialize base CoreI2C instance
\r
1021 I2C_init( &g_i2c_inst, COREI2C_BASE_ADDR, COREI2C_DUMMY_ADDR,
\r
1022 I2C_PCLK_DIV_256 );
\r
1024 // Read data from target slave Channel 0 of CoreI2C instance.
\r
1025 I2C_read( &g_i2c_inst, target_slave_addr, rx_buffer, read_length,
\r
1026 I2C_RELEASE_BUS );
\r
1028 status = I2C_wait_complete( &g_i2c_inst, I2C_NO_TIMEOUT );
\r
1034 i2c_instance_t * this_i2c,
\r
1035 uint8_t serial_addr,
\r
1036 uint8_t * read_buffer,
\r
1037 uint16_t read_size,
\r
1041 /*-------------------------------------------------------------------------*//**
\r
1042 I2C master write-read
\r
1043 ------------------------------------------------------------------------------
\r
1044 This function initiates an I2C write-read transaction where data is first
\r
1045 written to the target device before issuing a restart condition and changing
\r
1046 the direction of the I2C transaction in order to read from the target device.
\r
1048 The same warnings about buffer allocation in I2C_write() and I2C_read()
\r
1049 apply to this function.
\r
1050 ------------------------------------------------------------------------------
\r
1052 The this_i2c parameter is a pointer to the i2c_instance_t data structure
\r
1053 holding all data related to a specific CoreI2C channel. For example, if only
\r
1054 one channel is initialized, this data structure holds the information of
\r
1055 channel 0 of the instantiated CoreI2C hardware.
\r
1057 @param serial_addr:
\r
1058 This parameter specifies the serial address of the target I2C device.
\r
1060 @param addr_offset:
\r
1061 This parameter is a pointer to the buffer containing the data that will be
\r
1062 sent to the slave during the write phase of the write-read transaction. This
\r
1063 data is typically used to specify an address offset specifying to the I2C
\r
1064 slave device what data it must return during the read phase of the
\r
1065 write-read transaction.
\r
1067 @param offset_size:
\r
1068 This parameter specifies the number of offset bytes to be written during the
\r
1069 write phase of the write-read transaction. This is typically the size of the
\r
1070 buffer pointed to by the addr_offset parameter.
\r
1072 @param read_buffer:
\r
1073 This parameter is a pointer to the buffer where the data read from the I2C
\r
1074 slave will be stored.
\r
1077 This parameter specifies the number of bytes to read from the target I2C
\r
1078 slave device. This size must not exceed the size of the buffer pointed to by
\r
1079 the read_buffer parameter.
\r
1082 The options parameter is used to indicate if the I2C bus should be released
\r
1083 on completion of the write-read transaction. Using the I2C_RELEASE_BUS
\r
1084 constant for the options parameter causes a STOP bit to be generated at the
\r
1085 end of the write-read transaction causing the bus to be released for other
\r
1086 I2C devices to use. Using the I2C_HOLD_BUS constant as options parameter
\r
1087 prevents a STOP bit from being generated at the end of the write-read
\r
1088 transaction, preventing other I2C devices from initiating a bus transaction.
\r
1094 #define COREI2C_BASE_ADDR 0xC0000000u
\r
1095 #define COREI2C_DUMMY_ADDR 0x10u
\r
1096 #define TX_LENGTH 16u
\r
1097 #define RX_LENGTH 8u
\r
1099 i2c_instance_t g_i2c_inst;
\r
1100 uint8_t rx_buffer[RX_LENGTH];
\r
1101 uint8_t read_length = RX_LENGTH;
\r
1102 uint8_t tx_buffer[TX_LENGTH];
\r
1103 uint8_t write_length = TX_LENGTH;
\r
1107 uint8_t target_slave_addr = 0x12;
\r
1108 i2c_status_t status;
\r
1109 // Initialize base CoreI2C instance
\r
1110 I2C_init( &g_i2c_inst, COREI2C_BASE_ADDR, COREI2C_DUMMY_ADDR,
\r
1111 I2C_PCLK_DIV_256 );
\r
1113 I2C_write_read( &g_i2c_inst, target_slave_addr, tx_buffer, write_length,
\r
1114 rx_buffer, read_length, I2C_RELEASE_BUS );
\r
1116 status = I2C_wait_complete( &g_i2c_inst, I2C_NO_TIMEOUT );
\r
1120 void I2C_write_read
\r
1122 i2c_instance_t * this_i2c,
\r
1123 uint8_t serial_addr,
\r
1124 const uint8_t * addr_offset,
\r
1125 uint16_t offset_size,
\r
1126 uint8_t * read_buffer,
\r
1127 uint16_t read_size,
\r
1131 /*-------------------------------------------------------------------------*//**
\r
1133 ------------------------------------------------------------------------------
\r
1134 This function indicates the current state of a CoreI2C channel.
\r
1135 ------------------------------------------------------------------------------
\r
1137 The this_i2c parameter is a pointer to the i2c_instance_t data structure
\r
1138 holding all data related to a specific CoreI2C channel. For example, if only
\r
1139 one channel is initialized, this data structure holds the information of
\r
1140 channel 0 of the instantiated CoreI2C hardware.
\r
1141 ------------------------------------------------------------------------------
\r
1143 The return value indicates the current state of a CoreI2C channel or the
\r
1144 outcome of the previous transaction if no transaction is in progress.
\r
1145 Possible return values are:
\r
1147 The last I2C transaction has completed successfully.
\r
1149 There is an I2C transaction in progress.
\r
1151 The last I2C transaction failed.
\r
1153 The request has failed to complete in the allotted time.
\r
1157 i2c_instance_t g_i2c_inst;
\r
1159 while( I2C_IN_PROGRESS == I2C_get_status( &g_i2c_inst ) )
\r
1161 // Do something useful while waiting for I2C operation to complete
\r
1162 our_i2c_busy_task();
\r
1165 if( I2C_SUCCESS != I2C_get_status( &g_i2c_inst ) )
\r
1167 // Something went wrong...
\r
1168 our_i2c_error_recovery( &g_i2c_inst );
\r
1172 i2c_status_t I2C_get_status
\r
1174 i2c_instance_t * this_i2c
\r
1177 /*-------------------------------------------------------------------------*//**
\r
1178 Wait for I2C transaction completion.
\r
1179 ------------------------------------------------------------------------------
\r
1180 This function waits for the current I2C transaction to complete. The return
\r
1181 value indicates whether the last I2C transaction was successful or not.
\r
1182 ------------------------------------------------------------------------------
\r
1184 The this_i2c parameter is a pointer to the i2c_instance_t data structure
\r
1185 holding all data related to a specific CoreI2C channel. For example, if only
\r
1186 one channel is initialized, this data structure holds the information of
\r
1187 channel 0 of the instantiated CoreI2C hardware.
\r
1188 @param timeout_ms:
\r
1189 The timeout_ms parameter specified the delay within which the current I2C
\r
1190 transaction is expected to complete. The time out delay is given in
\r
1191 milliseconds. I2C_wait_complete() will return I2C_TIMED_OUT if the current
\r
1192 transaction has not completed after the time out delay has expired. This
\r
1193 parameter can be set to I2C_NO_TIMEOUT to indicate that I2C_wait_complete()
\r
1194 must not time out.
\r
1195 ------------------------------------------------------------------------------
\r
1197 The return value indicates the outcome of the last I2C transaction. It can
\r
1198 be one of the following:
\r
1200 The last I2C transaction has completed successfully.
\r
1202 The last I2C transaction failed.
\r
1204 The last transaction failed to complete within the time out delay given
\r
1205 as second parameter.
\r
1209 #define COREI2C_BASE_ADDR 0xC0000000u
\r
1210 #define COREI2C_DUMMY_ADDR 0x10u
\r
1211 #define DATA_LENGTH 16u
\r
1213 i2c_instance_t g_i2c_inst;
\r
1215 uint8_t rx_buffer[DATA_LENGTH];
\r
1216 uint8_t read_length = DATA_LENGTH;
\r
1220 uint8_t target_slave_addr = 0x12;
\r
1221 i2c_status_t status;
\r
1223 // Initialize base CoreI2C instance
\r
1224 I2C_init( &g_i2c_inst, COREI2C_BASE_ADDR, COREI2C_DUMMY_ADDR,
\r
1225 I2C_PCLK_DIV_256 );
\r
1227 // Read data from Channel 0 of CoreI2C instance.
\r
1228 I2C_read( &g_i2c_inst, target_slave_addr, rx_buffer, read_length,
\r
1229 I2C_RELEASE_BUS );
\r
1231 // Wait for completion and record the outcome
\r
1232 status = I2C_wait_complete( &g_i2c_inst, I2C_NO_TIMEOUT );
\r
1236 i2c_status_t I2C_wait_complete
\r
1238 i2c_instance_t * this_i2c,
\r
1239 uint32_t timeout_ms
\r
1242 /*-------------------------------------------------------------------------*//**
\r
1243 Time out delay expiration.
\r
1244 ------------------------------------------------------------------------------
\r
1245 This function is used to control the expiration of the time out delay
\r
1246 specified as a parameter to the I2C_wait_complete() function. It must be
\r
1247 called from the interrupt service routine of a periodic interrupt source such
\r
1248 as the Cortex-M3 SysTick timer interrupt. It takes the period of the interrupt
\r
1249 source as its ms_since_last_tick parameter and uses it as the time base for
\r
1250 the I2C_wait_complete() function
\92s time out delay.
\r
1252 Note: This function does not need to be called if the I2C_wait_complete()
\r
1253 function is called with a timeout_ms value of I2C_NO_TIMEOUT.
\r
1254 Note: If this function is not called then the I2C_wait_complete() function
\r
1255 will behave as if its timeout_ms was specified as I2C_NO_TIMEOUT and it
\r
1256 will not time out.
\r
1257 Note: If this function is being called from an interrupt handler (e.g SysTick)
\r
1258 it is important that the calling interrupt have a lower priority than
\r
1259 the CoreI2C interrupt(s) to ensure any updates to shared data are
\r
1262 ------------------------------------------------------------------------------
\r
1264 The this_i2c parameter is a pointer to the i2c_instance_t data structure
\r
1265 holding all data related to a specific CoreI2C channel. For example, if only
\r
1266 one channel is initialized, this data structure holds the information of
\r
1267 channel 0 of the instantiated CoreI2C hardware.
\r
1268 @param ms_since_last_tick:
\r
1269 The ms_since_last_tick parameter specifies the number of milliseconds that
\r
1270 elapsed since the last call to I2C_system_tick(). This parameter would
\r
1271 typically be a constant specifying the interrupt rate of a timer used to
\r
1272 generate system ticks.
\r
1273 ------------------------------------------------------------------------------
\r
1278 The example below shows an example of how the I2C_system_tick() function
\r
1279 would be called in a Cortex-M3 based system. I2C_system_tick() is called for
\r
1280 each I2C channel from the Cortex-M3 SysTick timer interrupt service routine.
\r
1281 The SysTick is configured to generate an interrupt every 10 milliseconds in
\r
1282 the example below.
\r
1284 #define SYSTICK_INTERVAL_MS 10
\r
1286 void SysTick_Handler(void)
\r
1288 I2C_system_tick(&g_core_i2c0, SYSTICK_INTERVAL_MS);
\r
1289 I2C_system_tick(&g_core_i2c2, SYSTICK_INTERVAL_MS);
\r
1293 void I2C_system_tick
\r
1295 i2c_instance_t * this_i2c,
\r
1296 uint32_t ms_since_last_tick
\r
1299 /*******************************************************************************
\r
1300 *******************************************************************************
\r
1302 * Slave specific functions
\r
1304 * The following functions are only used within the implementation of an I2C
\r
1308 /*-------------------------------------------------------------------------*//**
\r
1309 I2C slave transmit buffer configuration.
\r
1310 ------------------------------------------------------------------------------
\r
1311 This function specifies the memory buffer holding the data that will be sent
\r
1312 to the I2C master when this CoreI2C channel is the target of an I2C read or
\r
1313 write-read transaction.
\r
1314 ------------------------------------------------------------------------------
\r
1316 The this_i2c parameter is a pointer to the i2c_instance_t data structure
\r
1317 holding all data related to a specific CoreI2C channel. For example, if only
\r
1318 one channel is initialized, this data structure holds the information of
\r
1319 channel 0 of the instantiated CoreI2C hardware.
\r
1322 This parameter is a pointer to the memory buffer holding the data to be
\r
1323 returned to the I2C master when this CoreI2C channel is the target of an
\r
1324 I2C read or write-read transaction.
\r
1327 Size of the transmit buffer pointed to by the tx_buffer parameter.
\r
1333 #define COREI2C_BASE_ADDR 0xC0000000u
\r
1334 #define SLAVE_SER_ADDR 0x10u
\r
1335 #define SLAVE_TX_BUFFER_SIZE 10u
\r
1337 i2c_instance_t g_i2c_inst;
\r
1339 uint8_t g_slave_tx_buffer[SLAVE_TX_BUFFER_SIZE] = { 1, 2, 3, 4, 5,
\r
1344 // Initialize the CoreI2C driver with its base address, I2C serial
\r
1345 // address and serial clock divider.
\r
1346 I2C_init( &g_i2c_inst, COREI2C_BASE_ADDR, SLAVE_SER_ADDR,
\r
1347 I2C_PCLK_DIV_256 );
\r
1349 // Specify the transmit buffer containing the data that will be
\r
1350 // returned to the master during read and write-read transactions.
\r
1351 I2C_set_slave_tx_buffer( &g_i2c_inst, g_slave_tx_buffer,
\r
1352 sizeof(g_slave_tx_buffer) );
\r
1356 void I2C_set_slave_tx_buffer
\r
1358 i2c_instance_t * this_i2c,
\r
1359 const uint8_t * tx_buffer,
\r
1363 /*-------------------------------------------------------------------------*//**
\r
1364 I2C slave receive buffer configuration.
\r
1365 ------------------------------------------------------------------------------
\r
1366 This function specifies the memory buffer that will be used by the CoreI2C
\r
1367 channel to receive data when it is a slave. This buffer is the memory where
\r
1368 data will be stored when the CoreI2C channel is the target of an I2C master
\r
1369 write transaction (i.e. when it is the slave).
\r
1370 ------------------------------------------------------------------------------
\r
1372 The this_i2c parameter is a pointer to the i2c_instance_t data structure
\r
1373 holding all data related to a specific CoreI2C channel. For example, if only
\r
1374 one channel is initialized, this data structure holds the information of
\r
1375 channel 0 of the instantiated CoreI2C hardware.
\r
1378 This parameter is a pointer to the memory buffer allocated by the caller
\r
1379 software to be used as a slave receive buffer.
\r
1382 Size of the slave receive buffer. This is the amount of memory that is
\r
1383 allocated to the buffer pointed to by rx_buffer.
\r
1384 Note: This buffer size indirectly specifies the maximum I2C write
\r
1385 transaction length this CoreI2C channel can be the target of. This
\r
1386 is because this CoreI2C channel responds to further received
\r
1387 bytes with a non-acknowledge bit (NACK) as soon as its receive
\r
1388 buffer is full. This causes the write transaction to fail.
\r
1394 #define COREI2C_BASE_ADDR 0xC0000000u
\r
1395 #define SLAVE_SER_ADDR 0x10u
\r
1396 #define SLAVE_RX_BUFFER_SIZE 10u
\r
1398 i2c_instance_t g_i2c_inst;
\r
1400 uint8_t g_slave_rx_buffer[SLAVE_RX_BUFFER_SIZE];
\r
1404 // Initialize the CoreI2C driver with its base address, I2C serial
\r
1405 // address and serial clock divider.
\r
1406 I2C_init( &g_i2c_inst, COREI2C_BASE_ADDR, SLAVE_SER_ADDR,
\r
1407 I2C_PCLK_DIV_256 );
\r
1409 // Specify the buffer used to store the data written by the I2C master.
\r
1410 I2C_set_slave_rx_buffer( &g_i2c_inst, g_slave_rx_buffer,
\r
1411 sizeof(g_slave_rx_buffer) );
\r
1415 void I2C_set_slave_rx_buffer
\r
1417 i2c_instance_t * this_i2c,
\r
1418 uint8_t * rx_buffer,
\r
1422 /*-------------------------------------------------------------------------*//**
\r
1423 I2C slave memory offset length configuration.
\r
1424 ------------------------------------------------------------------------------
\r
1425 This function is used as part of the configuration of a CoreI2C channel for
\r
1426 operation as a slave supporting write-read transactions. It specifies the
\r
1427 number of bytes expected as part of the write phase of a write-read
\r
1428 transaction. The bytes received during the write phase of a write-read
\r
1429 transaction will be interpreted as an offset into the slave's transmit buffer.
\r
1430 This allows random access into the I2C slave transmit buffer from a remote
\r
1432 ------------------------------------------------------------------------------
\r
1434 The this_i2c parameter is a pointer to the i2c_instance_t data structure
\r
1435 holding all data related to a specific CoreI2C channel. For example, if only
\r
1436 one channel is initialized, this data structure holds the information of
\r
1437 channel 0 of the instantiated CoreI2C hardware.
\r
1439 @param offset_length:
\r
1440 The offset_length parameter configures the number of bytes to be interpreted
\r
1441 by the CoreI2C slave as a memory offset value during the write phase of
\r
1442 write-read transactions. The maximum value for the offset_length parameter
\r
1443 is two. The value of offset_length has the following effect on the
\r
1444 interpretation of the received data.
\r
1446 If offset_length is 0, the offset into the transmit buffer is fixed at 0.
\r
1448 If offset_length is 1, a single byte of received data is interpreted as an
\r
1449 unsigned 8 bit offset value in the range 0 to 255.
\r
1451 If offset_length is 2, 2 bytes of received data are interpreted as an
\r
1452 unsigned 16 bit offset value in the range 0 to 65535. The first byte
\r
1453 received in this case provides the high order bits of the offset and
\r
1454 the second byte provides the low order bits.
\r
1456 If the number of bytes received does not match the non 0 value of
\r
1457 offset_length the transmit buffer offset is set to 0.
\r
1463 #define COREI2C_BASE_ADDR 0xC0000000u
\r
1464 #define SLAVE_SER_ADDR 0x10u
\r
1465 #define SLAVE_TX_BUFFER_SIZE 10u
\r
1467 i2c_instance_t g_i2c_inst;
\r
1469 uint8_t g_slave_tx_buffer[SLAVE_TX_BUFFER_SIZE] = { 1, 2, 3, 4, 5,
\r
1474 // Initialize the CoreI2C driver with its base address, I2C serial
\r
1475 // address and serial clock divider.
\r
1476 I2C_init( &g_i2c_inst, COREI2C_BASE_ADDR, SLAVE_SER_ADDR,
\r
1477 I2C_PCLK_DIV_256 );
\r
1478 I2C_set_slave_tx_buffer( &g_i2c_inst, g_slave_tx_buffer,
\r
1479 sizeof(g_slave_tx_buffer) );
\r
1480 I2C_set_slave_mem_offset_length( &g_i2c_inst, 1 );
\r
1484 void I2C_set_slave_mem_offset_length
\r
1486 i2c_instance_t * this_i2c,
\r
1487 uint8_t offset_length
\r
1490 /*-------------------------------------------------------------------------*//**
\r
1491 I2C write handler registration.
\r
1492 ------------------------------------------------------------------------------
\r
1493 Register the function that is called to process the data written to this
\r
1494 CoreI2C channel when it is the slave in an I2C write transaction.
\r
1495 Note: If a write handler is registered, it is called on completion of the
\r
1496 write phase of a write-read transaction and responsible for processing
\r
1497 the received data in the slave receive buffer and populating the slave
\r
1498 transmit buffer with the data that will be transmitted to the I2C master
\r
1499 as part of the read phase of the write-read transaction. If a write
\r
1500 handler is not registered, the write data of a write read transaction is
\r
1501 interpreted as an offset into the slave
\92s transmit buffer and handled by
\r
1503 ------------------------------------------------------------------------------
\r
1505 The this_i2c parameter is a pointer to the i2c_instance_t data structure
\r
1506 holding all data related to a specific CoreI2C channel. For example, if only
\r
1507 one channel is initialized, this data structure holds the information of
\r
1508 channel 0 of the instantiated CoreI2C hardware.
\r
1511 Pointer to the function that will process the I2C write request.
\r
1517 #define COREI2C_BASE_ADDR 0xC0000000u
\r
1518 #define SLAVE_SER_ADDR 0x10u
\r
1519 #define SLAVE_TX_BUFFER_SIZE 10u
\r
1521 i2c_instance_t g_i2c_inst;
\r
1523 uint8_t g_slave_tx_buffer[SLAVE_TX_BUFFER_SIZE] = { 1, 2, 3, 4, 5,
\r
1526 // local function prototype
\r
1527 void slave_write_handler
\r
1529 i2c_instance_t * this_i2c,
\r
1530 uint8_t * p_rx_data,
\r
1536 // Initialize the CoreI2C driver with its base address, I2C serial
\r
1537 // address and serial clock divider.
\r
1538 I2C_init( &g_i2c_inst, COREI2C_BASE_ADDR, SLAVE_SER_ADDR,
\r
1539 I2C_PCLK_DIV_256 );
\r
1540 I2C_set_slave_tx_buffer( &g_i2c_inst, g_slave_tx_buffer,
\r
1541 sizeof(g_slave_tx_buffer) );
\r
1542 I2C_set_slave_mem_offset_length( &g_i2c_inst, 1 );
\r
1543 I2C_register_write_handler( &g_i2c_inst, slave_write_handler );
\r
1547 void I2C_register_write_handler
\r
1549 i2c_instance_t * this_i2c,
\r
1550 i2c_slave_wr_handler_t handler
\r
1553 /*-------------------------------------------------------------------------*//**
\r
1555 ------------------------------------------------------------------------------
\r
1556 This function enables slave mode operation for a CoreI2C channel. It enables
\r
1557 the CoreI2C slave to receive data when it is the target of an I2C read, write
\r
1558 or write-read transaction.
\r
1559 ------------------------------------------------------------------------------
\r
1561 The this_i2c parameter is a pointer to the i2c_instance_t data structure
\r
1562 holding all data related to a specific CoreI2C channel. For example, if only
\r
1563 one channel is initialized, this data structure holds the information of
\r
1564 channel 0 of the instantiated CoreI2C hardware.
\r
1570 // Enable I2C slave
\r
1571 I2C_enable_slave( &g_i2c_inst );
\r
1574 void I2C_enable_slave
\r
1576 i2c_instance_t * this_i2c
\r
1579 /*-------------------------------------------------------------------------*//**
\r
1580 I2C slave disable.
\r
1581 ------------------------------------------------------------------------------
\r
1582 This function disables slave mode operation for a CoreI2C channel. It stops
\r
1583 the CoreI2C slave acknowledging I2C read, write or write-read transactions
\r
1585 ------------------------------------------------------------------------------
\r
1587 The this_i2c parameter is a pointer to the i2c_instance_t data structure
\r
1588 holding all data related to a specific CoreI2C channel. For example, if only
\r
1589 one channel is initialized, this data structure holds the information of
\r
1590 channel 0 of the instantiated CoreI2C hardware.
\r
1596 // Disable I2C slave
\r
1597 I2C_disable_slave( &g_i2c_inst );
\r
1600 void I2C_disable_slave
\r
1602 i2c_instance_t * this_i2c
\r
1604 /*-------------------------------------------------------------------------*//**
\r
1605 Set I2C slave second address.
\r
1606 ------------------------------------------------------------------------------
\r
1607 The function I2C_set_slave_second_addr() sets the secondary slave address for
\r
1608 a CoreI2C slave device. This is an additional slave address which might be
\r
1609 required in certain applications, for example to enable fail-safe operation in
\r
1610 a system. As the CoreI2C device supports 7-bit addressing, the highest value
\r
1611 which can be assigned to second slave address is 127 (0x7F).
\r
1612 Note: This function does not support CoreI2C hardware configured with a fixed
\r
1613 second slave address. The current implementation of the ADDR1[0] register
\r
1614 bit makes it difficult for the driver to support both programmable and
\r
1615 fixed second slave address, so we choose to support programmable only.
\r
1616 ------------------------------------------------------------------------------
\r
1618 The this_i2c parameter is a pointer to the i2c_instance_t data structure
\r
1619 holding all data related to a specific CoreI2C channel. For example, if only
\r
1620 one channel is initialized, this data structure holds the information of
\r
1621 channel 0 of the instantiated CoreI2C hardware.
\r
1623 @param second_slave_addr:
\r
1624 The second_slave_addr parameter is the secondary slave address of the I2C
\r
1632 #define COREI2C_BASE_ADDR 0xC0000000u
\r
1633 #define SLAVE_SER_ADDR 0x10u
\r
1634 #define SECOND_SLAVE_ADDR 0x20u
\r
1636 i2c_instance_t g_i2c_inst;
\r
1639 // Initialize the CoreI2C driver with its base address, primary I2C
\r
1640 // serial address and serial clock divider.
\r
1641 I2C_init( &g_i2c_inst, COREI2C_BASE_ADDR, SLAVE_SER_ADDR,
\r
1642 I2C_PCLK_DIV_256 );
\r
1643 I2C_set_slave_second_addr( &g_i2c_inst, SECOND_SLAVE_ADDR );
\r
1647 void I2C_set_slave_second_addr
\r
1649 i2c_instance_t * this_i2c,
\r
1650 uint8_t second_slave_addr
\r
1653 /*-------------------------------------------------------------------------*//**
\r
1654 Disable second slave address.
\r
1655 ------------------------------------------------------------------------------
\r
1656 The function I2C_disable_slave_second_addr() disables the secondary slave
\r
1657 address of the CoreI2C slave device.
\r
1658 Note: This version of the driver only supports CoreI2C hardware configured
\r
1659 with a programmable second slave address.
\r
1660 ------------------------------------------------------------------------------
\r
1662 The this_i2c parameter is a pointer to the i2c_instance_t data structure
\r
1663 holding all data related to a specific CoreI2C channel. For example, if only
\r
1664 one channel is initialized, this data structure holds the information of
\r
1665 channel 0 of the instantiated CoreI2C hardware.
\r
1672 i2c_instance_t g_i2c_inst;
\r
1673 I2C_disable_slave_second_addr( &g_i2c_inst);
\r
1676 void I2C_disable_slave_second_addr
\r
1678 i2c_instance_t * this_i2c
\r
1681 /*-------------------------------------------------------------------------*//**
\r
1682 The I2C_set_gca() function is used to set the general call acknowledgement bit
\r
1683 of a CoreI2C slave device. This allows all channels of the CoreI2C slave
\r
1684 device respond to a general call or broadcast message from an I2C master.
\r
1685 ------------------------------------------------------------------------------
\r
1687 The this_i2c parameter is a pointer to the i2c_instance_t data structure
\r
1688 holding all data related to a specific CoreI2C channel. For example, if only
\r
1689 one channel is initialized, this data structure holds the information of
\r
1690 channel 0 of the instantiated CoreI2C hardware.
\r
1697 i2c_instance_t g_i2c_inst;
\r
1699 // Enable recognition of the General Call Address
\r
1700 I2C_set_gca( &g_i2c_inst );
\r
1705 i2c_instance_t * this_i2c
\r
1708 /*-------------------------------------------------------------------------*//**
\r
1709 The I2C_clear_gca() function is used to clear the general call acknowledgement
\r
1710 bit of a CoreI2C slave device. This will stop all channels of the I2C slave
\r
1711 device responding to any general call or broadcast message from the master.
\r
1712 ------------------------------------------------------------------------------
\r
1714 The this_i2c parameter is a pointer to the i2c_instance_t data structure
\r
1715 holding all data related to a specific CoreI2C channel. For example, if only
\r
1716 one channel is initialized, this data structure holds the information of
\r
1717 channel 0 of the instantiated CoreI2C hardware.
\r
1724 i2c_instance_t g_i2c_inst;
\r
1726 // Disable recognition of the General Call Address
\r
1727 I2C_clear_gca( &g_i2c_inst );
\r
1731 void I2C_clear_gca
\r
1733 i2c_instance_t * this_i2c
\r
1736 /*------------------------------------------------------------------------------
\r
1737 I2C SMBUS specific APIs
\r
1738 ----------------------------------------------------------------------------*/
\r
1740 /*-------------------------------------------------------------------------*//**
\r
1741 The I2C_smbus_init() function enables SMBus timeouts and status logic for a
\r
1743 Note: This and any of the other SMBus related functionality will only have an
\r
1744 effect if the CoreI2C was instantiated with the Generate SMBus Logic
\r
1746 Note: If the CoreI2C was instantiated with the Generate IPMI Logic option
\r
1747 checked this function will enable the IPMI 3mS SCL low timeout but none
\r
1748 of the other SMBus functions will have any effect.
\r
1749 ------------------------------------------------------------------------------
\r
1751 The this_i2c parameter is a pointer to the i2c_instance_t data structure
\r
1752 holding all data related to a specific CoreI2C channel. For example, if only
\r
1753 one channel is initialized, this data structure holds the information of
\r
1754 channel 0 of the instantiated CoreI2C hardware.
\r
1761 #define COREI2C_BASE_ADDR 0xC0000000u
\r
1762 #define SLAVE_SER_ADDR 0x10u
\r
1764 i2c_instance_t g_i2c_inst;
\r
1766 void system_init( void )
\r
1768 I2C_init( &g_i2c_inst, COREI2C_BASE_ADDR, SLAVE_SER_ADDR,
\r
1769 I2C_PCLK_DIV_256 );
\r
1771 // Initialize SMBus feature
\r
1772 I2C_smbus_init( &g_i2c_inst);
\r
1776 void I2C_smbus_init
\r
1778 i2c_instance_t * this_i2c
\r
1781 /*-------------------------------------------------------------------------*//**
\r
1782 The I2C_enable_smbus_irq() function is used to enable the CoreI2C channel
\92s
\r
1783 SMBSUS and SMBALERT SMBus interrupts.
\r
1784 ------------------------------------------------------------------------------
\r
1786 The this_i2c parameter is a pointer to the i2c_instance_t data structure
\r
1787 holding all data related to a specific CoreI2C channel. For example, if only
\r
1788 one channel is initialized, this data structure holds the information of
\r
1789 channel 0 of the instantiated CoreI2C hardware.
\r
1792 The irq_type specify the SMBUS interrupt(s) which will be enabled.
\r
1793 The two possible interrupts are:
\r
1796 To enable both ints in one call, use I2C_SMBALERT_IRQ | I2C_SMBSUS_IRQ.
\r
1803 #define COREI2C_BASE_ADDR 0xC0000000u
\r
1804 #define SLAVE_SER_ADDR 0x10u
\r
1806 i2c_instance_t g_i2c_inst;
\r
1810 I2C_init( &g_i2c_inst, COREI2C_BASE_ADDR, SLAVE_SER_ADDR,
\r
1811 I2C_PCLK_DIV_256 );
\r
1813 // Initialize SMBus feature
\r
1814 I2C_smbus_init( &g_i2c_inst );
\r
1816 // Enable both I2C_SMBALERT_IRQ & I2C_SMBSUS_IRQ interrupts
\r
1817 I2C_enable_smbus_irq( &g_i2c_inst,
\r
1818 (uint8_t)(I2C_SMBALERT_IRQ | I2C_SMBSUS_IRQ) );
\r
1822 void I2C_enable_smbus_irq
\r
1824 i2c_instance_t * this_i2c,
\r
1828 /*-------------------------------------------------------------------------*//**
\r
1829 The I2C_disable_smbus_irq() function is used to disable the CoreI2C channel
\92s
\r
1830 SMBSUS and SMBALERT SMBus interrupts.
\r
1831 ------------------------------------------------------------------------------
\r
1833 The this_i2c parameter is a pointer to the i2c_instance_t data structure
\r
1834 holding all data related to a specific CoreI2C channel. For example, if only
\r
1835 one channel is initialized, this data structure holds the information of
\r
1836 channel 0 of the instantiated CoreI2C hardware.
\r
1839 The irq_type specifies the SMBUS interrupt(s) which will be disabled.
\r
1840 The two possible interrupts are:
\r
1843 To disable both ints in one call, use I2C_SMBALERT_IRQ | I2C_SMBSUS_IRQ.
\r
1850 #define COREI2C_BASE_ADDR 0xC0000000u
\r
1851 #define SLAVE_SER_ADDR 0x10u
\r
1853 i2c_instance_t g_i2c_inst;
\r
1857 I2C_init( &g_i2c_inst, COREI2C_BASE_ADDR, SLAVE_SER_ADDR,
\r
1858 I2C_PCLK_DIV_256 );
\r
1860 // Initialize SMBus feature
\r
1861 I2C_smbus_init( &g_i2c_inst );
\r
1863 // Enable both SMBALERT & SMBSUS interrupts
\r
1864 I2C_enable_smbus_irq( &g_i2c_inst,
\r
1865 (uint8_t)(I2C_SMBALERT_IRQ | I2C_SMBSUS_IRQ));
\r
1869 // Disable the SMBALERT interrupt
\r
1870 I2C_disable_smbus_irq( &g_i2c_inst, I2C_SMBALERT_IRQ );
\r
1874 void I2C_disable_smbus_irq
\r
1876 i2c_instance_t * this_i2c,
\r
1880 /*-------------------------------------------------------------------------*//**
\r
1881 The function I2C_suspend_smbus_slave() forces any SMBUS slave devices
\r
1882 connected to a CoreI2C channel into power down or suspend mode by asserting
\r
1883 the channel's SMBSUS signal. The CoreI2C channel is the SMBus master in this
\r
1885 ------------------------------------------------------------------------------
\r
1887 The this_i2c parameter is a pointer to the i2c_instance_t data structure
\r
1888 holding all data related to a specific CoreI2C channel. For example, if only
\r
1889 one channel is initialized, this data structure holds the information of
\r
1890 channel 0 of the instantiated CoreI2C hardware.
\r
1897 #define COREI2C_BASE_ADDR 0xC0000000u
\r
1898 #define SLAVE_SER_ADDR 0x10u
\r
1900 i2c_instance_t g_i2c_inst;
\r
1904 I2C_init( &g_i2c_inst, COREI2C_BASE_ADDR, SLAVE_SER_ADDR,
\r
1905 I2C_PCLK_DIV_256 );
\r
1907 // Initialize SMBus feature
\r
1908 I2C_smbus_init( &g_i2c_inst );
\r
1910 // suspend SMBus slaves
\r
1911 I2C_suspend_smbus_slave( &g_i2c_inst );
\r
1915 // Re-enable SMBus slaves
\r
1916 I2C_resume_smbus_slave( &g_i2c_inst );
\r
1920 void I2C_suspend_smbus_slave
\r
1922 i2c_instance_t * this_i2c
\r
1925 /*-------------------------------------------------------------------------*//**
\r
1926 The function I2C_resume_smbus_slave() de-asserts the CoreI2C channel's SMBSUS
\r
1927 signal to take any connected slave devices out of suspend mode. The CoreI2C
\r
1928 channel is the SMBus master in this case.
\r
1929 ------------------------------------------------------------------------------
\r
1931 The this_i2c parameter is a pointer to the i2c_instance_t data structure
\r
1932 holding all data related to a specific CoreI2C channel. For example, if only
\r
1933 one channel is initialized, this data structure holds the information of
\r
1934 channel 0 of the instantiated CoreI2C hardware.
\r
1941 #define COREI2C_BASE_ADDR 0xC0000000u
\r
1942 #define SLAVE_SER_ADDR 0x10u
\r
1944 i2c_instance_t g_i2c_inst;
\r
1948 I2C_init( &g_i2c_inst, COREI2C_BASE_ADDR, SLAVE_SER_ADDR,
\r
1949 I2C_PCLK_DIV_256 );
\r
1951 // Initialize SMBus feature
\r
1952 I2C_smbus_init( &g_i2c_inst );
\r
1954 // suspend SMBus slaves
\r
1955 I2C_suspend_smbus_slave( &g_i2c_inst );
\r
1959 // Re-enable SMBus slaves
\r
1960 I2C_resume_smbus_slave( &g_i2c_inst );
\r
1964 void I2C_resume_smbus_slave
\r
1966 i2c_instance_t * this_i2c
\r
1969 /*-------------------------------------------------------------------------*//**
\r
1970 The I2C_reset_smbus() function resets the CoreI2C channel's SMBus connection
\r
1971 by forcing SCLK low for 35mS. The reset is automatically cleared after 35ms
\r
1972 have elapsed. The CoreI2C channel is the SMBus master in this case.
\r
1973 ------------------------------------------------------------------------------
\r
1975 The this_i2c parameter is a pointer to the i2c_instance_t data structure
\r
1976 holding all data related to a specific CoreI2C channel. For example, if only
\r
1977 one channel is initialized, this data structure holds the information of
\r
1978 channel 0 of the instantiated CoreI2C hardware.
\r
1985 #define COREI2C_BASE_ADDR 0xC0000000u
\r
1986 #define SLAVE_SER_ADDR 0x10u
\r
1988 i2c_instance_t g_i2c_inst;
\r
1992 I2C_init( &g_i2c_inst, COREI2C_BASE_ADDR, SLAVE_SER_ADDR,
\r
1993 I2C_PCLK_DIV_256 );
\r
1995 // Initialize SMBus feature
\r
1996 I2C_smbus_init( &g_i2c_inst );
\r
1998 // Make sure the SMBus channel is in a known state by resetting it
\r
1999 I2C_reset_smbus( &g_i2c_inst );
\r
2003 void I2C_reset_smbus
\r
2005 i2c_instance_t * this_i2c
\r
2008 /*-------------------------------------------------------------------------*//**
\r
2009 The I2C_set_smbus_alert() function is used to force master communication with
\r
2010 an I2C slave device by asserting the CoreI2C channel
\92s SMBALERT signal. The
\r
2011 CoreI2C channel is the SMBus slave in this case.
\r
2012 ------------------------------------------------------------------------------
\r
2014 The this_i2c parameter is a pointer to the i2c_instance_t data structure
\r
2015 holding all data related to a specific CoreI2C channel. For example, if only
\r
2016 one channel is initialized, this data structure holds the information of
\r
2017 channel 0 of the instantiated CoreI2C hardware.
\r
2024 #define COREI2C_BASE_ADDR 0xC0000000u
\r
2025 #define SLAVE_SER_ADDR 0x10u
\r
2027 i2c_instance_t g_i2c_inst;
\r
2031 I2C_init( &g_i2c_inst, COREI2C_BASE_ADDR, SLAVE_SER_ADDR,
\r
2032 I2C_PCLK_DIV_256 );
\r
2034 // Initialize SMBus feature
\r
2035 I2C_smbus_init( &g_i2c_inst );
\r
2037 // Get the SMBus masters attention
\r
2038 I2C_set_smbus_alert( &g_i2c_inst );
\r
2042 // Once we are happy, drop the alert
\r
2043 I2C_clear_smbus_alert( &g_i2c_inst );
\r
2047 void I2C_set_smbus_alert
\r
2049 i2c_instance_t * this_i2c
\r
2052 /*-------------------------------------------------------------------------*//**
\r
2053 The I2C_clear_smbus_alert() function is used de-assert the CoreI2C channel
\92s
\r
2054 SMBALERT signal once a slave device has had a response from the master. The
\r
2055 CoreI2C channel is the SMBus slave in this case.
\r
2056 ------------------------------------------------------------------------------
\r
2058 The this_i2c parameter is a pointer to the i2c_instance_t data structure
\r
2059 holding all data related to a specific CoreI2C channel. For example, if only
\r
2060 one channel is initialized, this data structure holds the information of
\r
2061 channel 0 of the instantiated CoreI2C hardware.
\r
2068 #define COREI2C_BASE_ADDR 0xC0000000u
\r
2069 #define SLAVE_SER_ADDR 0x10u
\r
2071 i2c_instance_t g_i2c_inst;
\r
2075 I2C_init( &g_i2c_inst, COREI2C_BASE_ADDR, SLAVE_SER_ADDR,
\r
2076 I2C_PCLK_DIV_256 );
\r
2078 // Initialize SMBus feature
\r
2079 I2C_smbus_init( &g_i2c_inst );
\r
2081 // Get the SMBus masters attention
\r
2082 I2C_set_smbus_alert( &g_i2c_inst );
\r
2086 // Once we are happy, drop the alert
\r
2087 I2C_clear_smbus_alert( &g_i2c_inst );
\r
2091 void I2C_clear_smbus_alert
\r
2093 i2c_instance_t * this_i2c
\r
2096 /*-------------------------------------------------------------------------*//**
\r
2097 The I2C_get_irq_status function returns information on which interrupts are
\r
2098 currently pending in a CoreI2C channel.
\r
2099 The interrupts supported by CoreI2C are:
\r
2103 The macros I2C_NO_IRQ, I2C_SMBALERT_IRQ, I2C_SMBSUS_IRQ and I2C_INTR_IRQ are
\r
2104 provided for use with this function.
\r
2105 ------------------------------------------------------------------------------
\r
2107 The this_i2c parameter is a pointer to the i2c_instance_t data structure
\r
2108 holding all data related to a specific CoreI2C channel. For example, if only
\r
2109 one channel is initialized, this data structure holds the information of
\r
2110 channel 0 of the instantiated CoreI2C hardware.
\r
2113 This function returns the status of the CoreI2C channel
\92s interrupts as a
\r
2114 single byte bitmap where a bit is set to indicate a pending interrupt.
\r
2115 The following are the bit positions associated with each interrupt type:
\r
2116 Bit 0 - SMBUS_ALERT_IRQ
\r
2117 Bit 1 - SMBSUS_IRQ
\r
2119 It returns 0, if there are no pending interrupts.
\r
2123 #define COREI2C_BASE_ADDR 0xC0000000u
\r
2124 #define SLAVE_SER_ADDR 0x10u
\r
2126 i2c_instance_t g_i2c_inst;
\r
2130 uint8_t irq_to_enable = I2C_SMBALERT_IRQ | I2C_SMBSUS_IRQ;
\r
2131 uint8_t pending_irq = 0u;
\r
2133 I2C_init( &g_i2c_inst, COREI2C_BASE_ADDR, SLAVE_SER_ADDR,
\r
2134 I2C_PCLK_DIV_256 );
\r
2136 // Initialize SMBus feature
\r
2137 I2C_smbus_init( &g_i2c_inst );
\r
2139 // Enable both I2C_SMBALERT_IRQ & I2C_SMBSUS_IRQ irq
\r
2140 I2C_enable_smbus_irq( &g_i2c_inst, irq_to_enable );
\r
2142 // Get I2C IRQ type
\r
2143 pending_irq = I2C_get_irq_status( &g_i2c_inst );
\r
2145 // Let's assume, in system, INTR and SMBALERT IRQ is pending.
\r
2146 // So pending_irq will return status of both the IRQs
\r
2148 if( pending_irq & I2C_SMBALERT_IRQ )
\r
2150 // if true, it means SMBALERT_IRQ is there in pending IRQ list
\r
2152 if( pending_irq & I2C_INTR_IRQ )
\r
2154 // if true, it means I2C_INTR_IRQ is there in pending IRQ list
\r
2159 uint8_t I2C_get_irq_status
\r
2161 i2c_instance_t * this_i2c
\r
2164 /*-------------------------------------------------------------------------*//**
\r
2165 The I2C_set_user_data() function is used to allow the association of a block
\r
2166 of application specific data with a CoreI2C channel. The composition of the
\r
2167 data block is an application matter and the driver simply provides the means
\r
2168 for the application to set and retrieve the pointer. This may for example be
\r
2169 used to provide additional channel specific information to the slave write
\r
2171 ------------------------------------------------------------------------------
\r
2173 The this_i2c parameter is a pointer to the i2c_instance_t data structure
\r
2174 holding all data related to a specific CoreI2C channel. For example, if only
\r
2175 one channel is initialized, this data structure holds the information of
\r
2176 channel 0 of the instantiated CoreI2C hardware.
\r
2178 @param p_user_data:
\r
2179 The p_user_data parameter is a pointer to the user specific data block for
\r
2180 this channel. It is defined as void * as the driver does not know the actual
\r
2181 type of data being pointed to and simply stores the pointer for later
\r
2182 retrieval by the application.
\r
2189 #define COREI2C_BASE_ADDR 0xC0000000u
\r
2190 #define SLAVE_SER_ADDR 0x10u
\r
2192 i2c_instance_t g_i2c_inst;
\r
2193 app_data_t channel_xdata;
\r
2197 app_data_t *p_xdata;
\r
2199 I2C_init( &g_i2c_inst, COREI2C_BASE_ADDR, SLAVE_SER_ADDR,
\r
2200 I2C_PCLK_DIV_256 );
\r
2202 // Store location of user data in instance structure
\r
2203 I2C_set_user_data( &g_i2c_inst, (void *)&channel_xdata );
\r
2207 // Retrieve location of user data and do some work on it
\r
2208 p_xdata = (app_data_t *)I2C_get_user_data( &g_i2c_inst );
\r
2209 if( NULL != p_xdata )
\r
2211 p_xdata->foo = 123;
\r
2216 void I2C_set_user_data
\r
2218 i2c_instance_t * this_i2c,
\r
2219 void * p_user_data
\r
2222 /*-------------------------------------------------------------------------*//**
\r
2223 The I2C_get_user_data() function is used to allow the retrieval of the address
\r
2224 of a block of application specific data associated with a CoreI2C channel.
\r
2225 The composition of the data block is an application matter and the driver
\r
2226 simply provides the means for the application to set and retrieve the pointer.
\r
2227 This may for example be used to provide additional channel specific
\r
2228 information to the slave write handler.
\r
2229 ------------------------------------------------------------------------------
\r
2231 The this_i2c parameter is a pointer to the i2c_instance_t data structure
\r
2232 holding all data related to a specific CoreI2C channel. For example, if only
\r
2233 one channel is initialized, this data structure holds the information of
\r
2234 channel 0 of the instantiated CoreI2C hardware.
\r
2237 This function returns a pointer to the user specific data block for this
\r
2238 channel. It is defined as void * as the driver does not know the actual type
\r
2239 of data being pointed. If no user data has been registered for this channel
\r
2240 a NULL pointer is returned.
\r
2244 #define COREI2C_BASE_ADDR 0xC0000000u
\r
2245 #define SLAVE_SER_ADDR 0x10u
\r
2247 i2c_instance_t g_i2c_inst;
\r
2248 app_data_t channel_xdata;
\r
2252 app_data_t *p_xdata;
\r
2254 I2C_init( &g_i2c_inst, COREI2C_BASE_ADDR, SLAVE_SER_ADDR,
\r
2255 I2C_PCLK_DIV_256 );
\r
2257 // Store location of user data in instance structure
\r
2258 I2C_set_user_data( &g_i2c_inst, (void *)&channel_xdata );
\r
2262 // Retrieve location of user data and do some work on it
\r
2263 p_xdata = (app_data_t *)I2C_get_user_data( &g_i2c_inst );
\r
2264 if( NULL != p_xdata )
\r
2266 p_xdata->foo = 123;
\r
2271 void * I2C_get_user_data
\r
2273 i2c_instance_t * this_i2c
\r
2276 #ifdef __cplusplus
\r