1 /*******************************************************************************
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2 * (c) Copyright 2007-2015 Microsemi SoC Products Group. All rights reserved.
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4 * SVN $Revision: 7967 $
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5 * SVN $Date: 2015-10-09 18:48:26 +0530 (Fri, 09 Oct 2015) $
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8 #ifndef __CORE_TIMER_REGISTERS
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9 #define __CORE_TIMER_REGISTERS 1
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11 /*------------------------------------------------------------------------------
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12 * TimerLoad register details
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14 #define TimerLoad_REG_OFFSET 0x00
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19 #define LoadValue_OFFSET 0x00
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20 #define LoadValue_MASK 0xFFFFFFFF
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21 #define LoadValue_SHIFT 0
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23 /*------------------------------------------------------------------------------
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24 * TimerValue register details
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26 #define TimerValue_REG_OFFSET 0x04
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29 * CurrentValue bits.
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31 #define CurrentValue_OFFSET 0x04
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32 #define CurrentValue_MASK 0xFFFFFFFF
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33 #define CurrentValue_SHIFT 0
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35 /*------------------------------------------------------------------------------
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36 * TimerControl register details
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38 #define TimerControl_REG_OFFSET 0x08
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43 #define TimerEnable_OFFSET 0x08
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44 #define TimerEnable_MASK 0x00000001
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45 #define TimerEnable_SHIFT 0
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48 * InterruptEnable bits.
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50 #define InterruptEnable_OFFSET 0x08
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51 #define InterruptEnable_MASK 0x00000002
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52 #define InterruptEnable_SHIFT 1
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57 #define TimerMode_OFFSET 0x08
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58 #define TimerMode_MASK 0x00000004
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59 #define TimerMode_SHIFT 2
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61 /*------------------------------------------------------------------------------
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62 * TimerPrescale register details
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64 #define TimerPrescale_REG_OFFSET 0x0C
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69 #define Prescale_OFFSET 0x0C
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70 #define Prescale_MASK 0x0000000F
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71 #define Prescale_SHIFT 0
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73 /*------------------------------------------------------------------------------
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74 * TimerIntClr register details
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76 #define TimerIntClr_REG_OFFSET 0x10
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81 #define TimerIntClr_OFFSET 0x10
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82 #define TimerIntClr_MASK 0xFFFFFFFF
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83 #define TimerIntClr_SHIFT 0
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85 /*------------------------------------------------------------------------------
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86 * TimerRIS register details
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88 #define TimerRIS_REG_OFFSET 0x14
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91 * RawTimerInterrupt bits.
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93 #define RawTimerInterrupt_OFFSET 0x14
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94 #define RawTimerInterrupt_MASK 0x00000001
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95 #define RawTimerInterrupt_SHIFT 0
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97 /*------------------------------------------------------------------------------
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98 * TimerMIS register details
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100 #define TimerMIS_REG_OFFSET 0x18
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103 * TimerInterrupt bits.
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105 #define TimerInterrupt_OFFSET 0x18
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106 #define TimerInterrupt_MASK 0x00000001
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107 #define TimerInterrupt_SHIFT 0
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109 #endif /* __CORE_TIMER_REGISTERS */
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