1 /* Copyright 2018 SiFive, Inc */
2 /* SPDX-License-Identifier: Apache-2.0 */
4 #include <metal/machine/platform.h>
6 #ifdef METAL_SIFIVE_GPIO0
8 #include <metal/drivers/sifive_gpio0.h>
10 #include <metal/machine.h>
12 int __metal_driver_sifive_gpio0_enable_input(struct metal_gpio *ggpio, long source)
14 long base = __metal_driver_sifive_gpio0_base(ggpio);
16 __METAL_ACCESS_ONCE((__metal_io_u32 *)(base + METAL_SIFIVE_GPIO0_INPUT_EN)) |= source;
21 int __metal_driver_sifive_gpio0_disable_input(struct metal_gpio *ggpio, long source)
23 long base = __metal_driver_sifive_gpio0_base(ggpio);
25 __METAL_ACCESS_ONCE((__metal_io_u32 *)(base + METAL_SIFIVE_GPIO0_INPUT_EN)) &= ~source;
30 long __metal_driver_sifive_gpio0_input(struct metal_gpio *ggpio)
32 long base = __metal_driver_sifive_gpio0_base(ggpio);
34 return __METAL_ACCESS_ONCE((__metal_io_u32 *)(base + METAL_SIFIVE_GPIO0_VALUE));
37 long __metal_driver_sifive_gpio0_output(struct metal_gpio *ggpio)
39 long base = __metal_driver_sifive_gpio0_base(ggpio);
41 return __METAL_ACCESS_ONCE((__metal_io_u32 *)(base + METAL_SIFIVE_GPIO0_PORT));
45 int __metal_driver_sifive_gpio0_disable_output(struct metal_gpio *ggpio, long source)
47 long base = __metal_driver_sifive_gpio0_base(ggpio);
49 __METAL_ACCESS_ONCE((__metal_io_u32 *)(base + METAL_SIFIVE_GPIO0_OUTPUT_EN)) &= ~source;
54 int __metal_driver_sifive_gpio0_enable_output(struct metal_gpio *ggpio, long source)
56 long base = __metal_driver_sifive_gpio0_base(ggpio);
58 __METAL_ACCESS_ONCE((__metal_io_u32 *)(base + METAL_SIFIVE_GPIO0_OUTPUT_EN)) |= source;
63 int __metal_driver_sifive_gpio0_output_set(struct metal_gpio *ggpio, long value)
65 long base = __metal_driver_sifive_gpio0_base(ggpio);
67 __METAL_ACCESS_ONCE((__metal_io_u32 *)(base + METAL_SIFIVE_GPIO0_PORT)) |= value;
72 int __metal_driver_sifive_gpio0_output_clear(struct metal_gpio *ggpio, long value)
74 long base = __metal_driver_sifive_gpio0_base(ggpio);
76 __METAL_ACCESS_ONCE((__metal_io_u32 *)(base + METAL_SIFIVE_GPIO0_PORT)) &= ~value;
81 int __metal_driver_sifive_gpio0_output_toggle(struct metal_gpio *ggpio, long value)
83 long base = __metal_driver_sifive_gpio0_base(ggpio);
85 __METAL_ACCESS_ONCE((__metal_io_u32 *)(base + METAL_SIFIVE_GPIO0_PORT)) =
86 __METAL_ACCESS_ONCE((__metal_io_u32 *)(base + METAL_SIFIVE_GPIO0_PORT)) ^ value;
91 int __metal_driver_sifive_gpio0_enable_io(struct metal_gpio *ggpio, long source, long dest)
93 long base = __metal_driver_sifive_gpio0_base(ggpio);
95 __METAL_ACCESS_ONCE((__metal_io_u32 *)(base + METAL_SIFIVE_GPIO0_IOF_SEL)) &= ~source;
96 __METAL_ACCESS_ONCE((__metal_io_u32 *)(base + METAL_SIFIVE_GPIO0_IOF_EN)) |= dest;
101 int __metal_driver_sifive_gpio0_disable_io(struct metal_gpio *ggpio, long source)
103 long base = __metal_driver_sifive_gpio0_base(ggpio);
105 __METAL_ACCESS_ONCE((__metal_io_u32 *)(base + METAL_SIFIVE_GPIO0_IOF_EN)) &= ~source;
110 int __metal_driver_sifive_gpio0_config_int(struct metal_gpio *ggpio, long source, int intr_type)
112 long base = __metal_driver_sifive_gpio0_base(ggpio);
116 case METAL_GPIO_INT_DISABLE:
117 __METAL_ACCESS_ONCE((__metal_io_u32 *)(base + METAL_SIFIVE_GPIO0_RISE_IE)) &= ~source;
118 __METAL_ACCESS_ONCE((__metal_io_u32 *)(base + METAL_SIFIVE_GPIO0_FALL_IE)) &= ~source;
119 __METAL_ACCESS_ONCE((__metal_io_u32 *)(base + METAL_SIFIVE_GPIO0_HIGH_IE)) &= ~source;
120 __METAL_ACCESS_ONCE((__metal_io_u32 *)(base + METAL_SIFIVE_GPIO0_LOW_IE)) &= ~source;
122 case METAL_GPIO_INT_RISING:
123 __METAL_ACCESS_ONCE((__metal_io_u32 *)(base + METAL_SIFIVE_GPIO0_RISE_IE)) |= source;
125 case METAL_GPIO_INT_FALLING:
126 __METAL_ACCESS_ONCE((__metal_io_u32 *)(base + METAL_SIFIVE_GPIO0_FALL_IE)) |= source;
128 case METAL_GPIO_INT_BOTH_EDGE:
129 __METAL_ACCESS_ONCE((__metal_io_u32 *)(base + METAL_SIFIVE_GPIO0_RISE_IE)) |= source;
130 __METAL_ACCESS_ONCE((__metal_io_u32 *)(base + METAL_SIFIVE_GPIO0_FALL_IE)) |= source;
132 case METAL_GPIO_INT_HIGH:
133 __METAL_ACCESS_ONCE((__metal_io_u32 *)(base + METAL_SIFIVE_GPIO0_HIGH_IE)) |= source;
135 case METAL_GPIO_INT_LOW:
136 __METAL_ACCESS_ONCE((__metal_io_u32 *)(base + METAL_SIFIVE_GPIO0_LOW_IE)) |= source;
138 case METAL_GPIO_INT_BOTH_LEVEL:
139 __METAL_ACCESS_ONCE((__metal_io_u32 *)(base + METAL_SIFIVE_GPIO0_HIGH_IE)) |= source;
140 __METAL_ACCESS_ONCE((__metal_io_u32 *)(base + METAL_SIFIVE_GPIO0_LOW_IE)) |= source;
142 case METAL_GPIO_INT_MAX:
143 __METAL_ACCESS_ONCE((__metal_io_u32 *)(base + METAL_SIFIVE_GPIO0_RISE_IE)) |= source;
144 __METAL_ACCESS_ONCE((__metal_io_u32 *)(base + METAL_SIFIVE_GPIO0_FALL_IE)) |= source;
145 __METAL_ACCESS_ONCE((__metal_io_u32 *)(base + METAL_SIFIVE_GPIO0_HIGH_IE)) |= source;
146 __METAL_ACCESS_ONCE((__metal_io_u32 *)(base + METAL_SIFIVE_GPIO0_LOW_IE)) |= source;
152 int __metal_driver_sifive_gpio0_clear_int(struct metal_gpio *ggpio, long source, int intr_type)
154 long base = __metal_driver_sifive_gpio0_base(ggpio);
158 case METAL_GPIO_INT_RISING:
159 __METAL_ACCESS_ONCE((__metal_io_u32 *)(base + METAL_SIFIVE_GPIO0_RISE_IP)) |= source;
161 case METAL_GPIO_INT_FALLING:
162 __METAL_ACCESS_ONCE((__metal_io_u32 *)(base + METAL_SIFIVE_GPIO0_FALL_IP)) |= source;
164 case METAL_GPIO_INT_BOTH_EDGE:
165 __METAL_ACCESS_ONCE((__metal_io_u32 *)(base + METAL_SIFIVE_GPIO0_RISE_IP)) |= source;
166 __METAL_ACCESS_ONCE((__metal_io_u32 *)(base + METAL_SIFIVE_GPIO0_FALL_IP)) |= source;
168 case METAL_GPIO_INT_HIGH:
169 __METAL_ACCESS_ONCE((__metal_io_u32 *)(base + METAL_SIFIVE_GPIO0_HIGH_IP)) |= source;
171 case METAL_GPIO_INT_LOW:
172 __METAL_ACCESS_ONCE((__metal_io_u32 *)(base + METAL_SIFIVE_GPIO0_LOW_IP)) |= source;
174 case METAL_GPIO_INT_BOTH_LEVEL:
175 __METAL_ACCESS_ONCE((__metal_io_u32 *)(base + METAL_SIFIVE_GPIO0_HIGH_IP)) |= source;
176 __METAL_ACCESS_ONCE((__metal_io_u32 *)(base + METAL_SIFIVE_GPIO0_LOW_IP)) |= source;
178 case METAL_GPIO_INT_MAX:
179 __METAL_ACCESS_ONCE((__metal_io_u32 *)(base + METAL_SIFIVE_GPIO0_RISE_IP)) |= source;
180 __METAL_ACCESS_ONCE((__metal_io_u32 *)(base + METAL_SIFIVE_GPIO0_FALL_IP)) |= source;
181 __METAL_ACCESS_ONCE((__metal_io_u32 *)(base + METAL_SIFIVE_GPIO0_HIGH_IP)) |= source;
182 __METAL_ACCESS_ONCE((__metal_io_u32 *)(base + METAL_SIFIVE_GPIO0_LOW_IP)) |= source;
188 struct metal_interrupt *
189 __metal_driver_gpio_interrupt_controller(struct metal_gpio *gpio)
191 return __metal_driver_sifive_gpio0_interrupt_parent(gpio);
194 int __metal_driver_gpio_get_interrupt_id(struct metal_gpio *gpio, int pin)
197 irq = __metal_driver_sifive_gpio0_interrupt_lines(gpio, pin);
201 __METAL_DEFINE_VTABLE(__metal_driver_vtable_sifive_gpio0) = {
202 .gpio.disable_input = __metal_driver_sifive_gpio0_disable_input,
203 .gpio.enable_input = __metal_driver_sifive_gpio0_enable_input,
204 .gpio.input = __metal_driver_sifive_gpio0_input,
205 .gpio.output = __metal_driver_sifive_gpio0_output,
206 .gpio.disable_output = __metal_driver_sifive_gpio0_disable_output,
207 .gpio.enable_output = __metal_driver_sifive_gpio0_enable_output,
208 .gpio.output_set = __metal_driver_sifive_gpio0_output_set,
209 .gpio.output_clear = __metal_driver_sifive_gpio0_output_clear,
210 .gpio.output_toggle = __metal_driver_sifive_gpio0_output_toggle,
211 .gpio.enable_io = __metal_driver_sifive_gpio0_enable_io,
212 .gpio.disable_io = __metal_driver_sifive_gpio0_disable_io,
213 .gpio.config_int = __metal_driver_sifive_gpio0_config_int,
214 .gpio.clear_int = __metal_driver_sifive_gpio0_clear_int,
215 .gpio.interrupt_controller = __metal_driver_gpio_interrupt_controller,
216 .gpio.get_interrupt_id = __metal_driver_gpio_get_interrupt_id,
219 #endif /* METAL_SIFIVE_GPIO0 */
221 typedef int no_empty_translation_units;