git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1_GCC/bsp/design.dts

   1 /dts-v1/;
   2
   3 / {
   4         #address-cells = <1>;
   5         #size-cells = <1>;
   6         compatible = "sifive,hifive1-revb";
   7         model = "sifive,hifive1-revb";
   8
   9         chosen {
  10                 stdout-path = "/soc/serial@10013000:115200";
  11                 metal,entry = <&spi0 0x10000>;
  12         };
  13
  14         cpus {
  15                 #address-cells = <1>;
  16                 #size-cells = <0>;
  17                 compatible = "sifive,fe310-g000";
  18                 L6: cpu@0 {
  19                         clocks = <&hfclk>;
  20                         compatible = "sifive,rocket0", "riscv";
  21                         device_type = "cpu";
  22                         i-cache-block-size = <64>;
  23                         i-cache-sets = <128>;
  24                         i-cache-size = <16384>;
  25                         next-level-cache = <&spi0>;
  26                         reg = <0>;
  27                         riscv,isa = "rv32imac";
  28                         riscv,pmpregions = <8>;
  29                         sifive,dtim = <&dtim>;
  30                         status = "okay";
  31                         timebase-frequency = <1000000>;
  32                         hardware-exec-breakpoint-count = <4>;
  33                         hlic: interrupt-controller {
  34                                 #interrupt-cells = <1>;
  35                                 compatible = "riscv,cpu-intc";
  36                                 interrupt-controller;
  37                         };
  38                 };
  39         };
  40
  41         soc {
  42                 #address-cells = <1>;
  43                 #size-cells = <1>;
  44                 #clock-cells = <1>;
  45                 compatible = "sifive,hifive1";
  46                 ranges;
  47                 hfxoscin: clock@0 {
  48                         #clock-cells = <0>;
  49                         compatible = "fixed-clock";
  50                         clock-frequency = <16000000>;
  51                 };
  52                 hfxoscout: clock@1 {
  53                         compatible = "sifive,fe310-g000,hfxosc";
  54                         clocks = <&hfxoscin>;
  55                         reg = <&prci 0x4>;
  56                         reg-names = "config";
  57                 };
  58                 hfroscin: clock@2 {
  59                         #clock-cells = <0>;
  60                         compatible = "fixed-clock";
  61                         clock-frequency = <72000000>;
  62                 };
  63                 hfroscout: clock@3 {
  64                         compatible = "sifive,fe310-g000,hfrosc";
  65                         clocks = <&hfroscin>;
  66                         reg = <&prci 0x0>;
  67                         reg-names = "config";
  68                 };
  69                 hfclk: clock@4 {
  70                         compatible = "sifive,fe310-g000,pll";
  71                         clocks = <&hfxoscout &hfroscout>;
  72                         clock-names = "pllref", "pllsel0";
  73                         reg = <&prci 0x8 &prci 0xc>;
  74                         reg-names = "config", "divider";
  75                         clock-frequency = <16000000>;
  76                 };
  77
  78                 lfroscin: clock@5 {
  79                         #clock-cells = <0>;
  80                         compatible = "fixed-clock";
  81                         clock-frequency = <32000000>;
  82                 };
  83                 lfclk: clock@6 {
  84                         compatible = "sifive,fe310-g000,lfrosc";
  85                         clocks = <&lfroscin>;
  86                         reg = <&aon 0x70>;
  87                         reg-names = "config";
  88                 };
  89
  90                 aon: aon@10000000 {
  91                         compatible = "sifive,aon0";
  92                         reg = <0x10000000 0x8000>;
  93                         reg-names = "mem";
  94                 };
  95
  96                 prci: prci@10008000 {
  97                         compatible = "sifive,fe310-g000,prci";
  98                         reg = <0x10008000 0x8000>;
  99                         reg-names = "mem";
 100                 };
 101
 102                 clint: clint@2000000 {
 103                         compatible = "riscv,clint0";
 104                         interrupts-extended = <&hlic 3 &hlic 7>;
 105                         reg = <0x2000000 0x10000>;
 106                         reg-names = "control";
 107                 };
 108                 local-external-interrupts-0 {
 109                         compatible = "sifive,local-external-interrupts0";
 110                         interrupt-parent = <&hlic>;
 111                         interrupts = <16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31>;
 112                 };
 113                 plic: interrupt-controller@c000000 {
 114                         #interrupt-cells = <1>;
 115                         compatible = "riscv,plic0";
 116                         interrupt-controller;
 117                         interrupts-extended = <&hlic 11>;
 118                         reg = <0xc000000 0x4000000>;
 119                         reg-names = "control";
 120                         riscv,max-priority = <7>;
 121                         riscv,ndev = <26>;
 122                 };
 123                 global-external-interrupts {
 124                         compatile = "sifive,global-external-interrupts0";
 125                         interrupt-parent = <&plic>;
 126                         interrupts = <1 2 3 4>;
 127                 };
 128
 129                 debug-controller@0 {
 130                         compatible = "sifive,debug-011", "riscv,debug-011";
 131                         interrupts-extended = <&hlic 65535>;
 132                         reg = <0x0 0x100>;
 133                         reg-names = "control";
 134                 };
 135
 136                 maskrom@1000 {
 137                         reg = <0x1000 0x2000>;
 138                         reg-names = "mem";
 139                 };
 140                 otp@20000 {
 141                         reg = <0x20000 0x2000 0x10010000 0x1000>;
 142                         reg-names = "mem", "control";
 143                 };
 144
 145                 dtim: dtim@80000000 {
 146                         compatible = "sifive,dtim0";
 147                         reg = <0x80000000 0x4000>;
 148                         reg-names = "mem";
 149                 };
 150
 151                 pwm@10015000 {
 152                         compatible = "sifive,pwm0";
 153                         interrupt-parent = <&plic>;
 154                         interrupts = <23 24 25 26>;
 155                         reg = <0x10015000 0x1000>;
 156                         reg-names = "control";
 157                 };
 158                 gpio0: gpio@10012000 {
 159                         compatible = "sifive,gpio0";
 160                         interrupt-parent = <&plic>;
 161                         interrupts = <7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22>;
 162                         reg = <0x10012000 0x1000>;
 163                         reg-names = "control";
 164                 };
 165                 uart0: serial@10013000 {
 166                         compatible = "sifive,uart0";
 167                         interrupt-parent = <&plic>;
 168                         interrupts = <5>;
 169                         reg = <0x10013000 0x1000>;
 170                         reg-names = "control";
 171                         clocks = <&hfclk>;
 172                         pinmux = <&gpio0 0x30000 0x30000>;
 173                 };
 174                 spi0: spi@10014000 {
 175                         compatible = "sifive,spi0";
 176                         interrupt-parent = <&plic>;
 177                         interrupts = <6>;
 178                         reg = <0x10014000 0x1000 0x20000000 0x7A120>;
 179                         reg-names = "control", "mem";
 180                         clocks = <&hfclk>;
 181                         pinmux = <&gpio0 0x0003C 0x0003C>;
 182                 };
 183                 i2c0: i2c@10016000 {
 184                         compatible = "sifive,i2c0";
 185                         interrupt-parent = <&plic>;
 186                         interrupts = <52>;
 187                         reg = <0x10016000 0x1000>;
 188                         reg-names = "control";
 189                 };
 190                 led@0red {
 191                         compatible = "sifive,gpio-leds";
 192                         label = "LD0red";
 193                         gpios = <&gpio0 22>;
 194                         linux,default-trigger = "none";
 195                 };
 196                 led@0green {
 197                         compatible = "sifive,gpio-leds";
 198                         label = "LD0green";
 199                         gpios = <&gpio0 19>;
 200                         linux,default-trigger = "none";
 201                 };
 202                 led@0blue {
 203                         compatible = "sifive,gpio-leds";
 204                         label = "LD0blue";
 205                         gpios = <&gpio0 21>;
 206                         linux,default-trigger = "none";
 207                 };
 208         };
 209 };