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  37 <h1>FE310-G00 PLL<a class="headerlink" href="#fe310-g00-pll" title="Permalink to this headline">¶</a></h1>
  38 <p>On targets with a PLL compatible with the FE310-G000 SoC, the PLL is configured
  39 at program initialization with a constructor. This PLL sets the clock frequency
  40 of the RISC-V CPU, and users of Freedom Metal who wish to set a specific clock
  41 rate can use Freedom Metal to request that the PLL take on a certain output rate.</p>
  42 <p>In the DeviceTree for your target, there should be a node like the following
  43 (example taken from the SiFive HiFive1):</p>
  44 <div class="highlight-DeviceTree notranslate"><div class="highlight"><pre><span></span>hfclk: clock@4 {
  45         compatible = &quot;sifive,fe310-g000,pll&quot;;
  46         clocks = &lt;&amp;hfxoscout &amp;hfroscout&gt;;
  47         clock-names = &quot;pllref&quot;, &quot;pllsel0&quot;;
  48         reg = &lt;&amp;prci 0x8 &amp;prci 0xc&gt;;
  49         reg-names = &quot;config&quot;, &quot;divider&quot;;
  50         clock-frequency = &lt;16000000&gt;;
  51 };
  52 </pre></div>
  53 </div>
  54 <p>The <code class="docutils literal notranslate"><span class="pre">clock-frequency</span></code> property of the node sets the requested clock rate of
  55 the FE310-G000 PLL. The PLL driver will attempt to configure the PLL to achieve
  56 this clock rate.</p>
  57 <p>Users should note that the FE310-G000 PLL only supports certain input/output
  58 clock rate ratios, and so the effective output rate of the PLL may differ from
  59 the requested rate.</p>
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