1 Physical Memory Protection
2 ==========================
4 Physical Memory Protection (PMP) is a part of the RISC-V Privileged Architecture
5 Specification which discribes the interface for a standard RISC-V memory
8 The PMP defines a finite number of PMP regions which can be individually configured
9 to enforce access permissions to a range of addresses in memory. Each PMP region
10 is configurable with the following options:
12 .. doxygenstruct:: metal_pmp_config
20 All PMP-related functions first depend on having a handle to the PMP device:
24 struct metal_pmp *pmp = metal_pmp_get_device();
26 /* Failed to get PMP device handle */
29 PMP initialization is optional and has the effect of disabling all PMP regions,
36 The number of PMP regions available can be retrieved from the PMP device handle:
38 .. doxygenstruct:: metal_pmp
43 Configuring a PMP Region
44 ------------------------
46 Freedom Metal has a set of APIs for configuring a PMP region. The most generic of these
49 .. doxygenfunction:: metal_pmp_set_region
52 This function allows for the configuration of all PMP region settings.
54 Additional APIs are provided for granularly changing individual PMP region settings.
57 .. doxygenfunction:: metal_pmp_set_address
60 .. doxygenfunction:: metal_pmp_lock
63 .. doxygenfunction:: metal_pmp_set_writeable
67 Additional documentation for this API is provided in :doc:`the PMP API reference </apiref/pmp>`.
69 The RISC-V specification allows implementation of PMP to hard-wire the configuration
70 values of PMP regions. In these cases, attempts to configure these PMP regions will
73 Handling PMP Access Faults
74 --------------------------
76 Attempted memory accesses which the PMP is configured to prevent trigger a
77 CPU exception. These exceptions can be handled by installing a CPU exception
78 handler for exception codes related to memory access faults.
80 Additional documentation about creating and registering exception handlers can
81 be found in :doc:`the Exception Handlers Developer Guide </devguide/exceptions>`.
83 Additional Documentation
84 ------------------------
86 Additional documentation about the Physical Memory Protection system and fault
87 handling on RISC-V systems can be found in
88 `The RISC-V Privileged ISA Specification v1.10 <https://riscv.org/specifications/privileged-isa/>`_.