2 FreeRTOS V8.2.0rc1 - Copyright (C) 2014 Real Time Engineers Ltd.
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5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 This file is part of the FreeRTOS distribution.
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9 FreeRTOS is free software; you can redistribute it and/or modify it under
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10 the terms of the GNU General Public License (version 2) as published by the
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11 Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
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13 >>! NOTE: The modification to the GPL is included to allow you to !<<
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14 >>! distribute a combined work that includes FreeRTOS without being !<<
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15 >>! obliged to provide the source code for proprietary components !<<
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16 >>! outside of the FreeRTOS kernel. !<<
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18 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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19 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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20 FOR A PARTICULAR PURPOSE. Full license text is available on the following
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21 link: http://www.freertos.org/a00114.html
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25 ***************************************************************************
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27 * Having a problem? Start by reading the FAQ "My application does *
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28 * not run, what could be wrong?". Have you defined configASSERT()? *
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30 * http://www.FreeRTOS.org/FAQHelp.html *
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32 ***************************************************************************
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34 ***************************************************************************
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36 * FreeRTOS provides completely free yet professionally developed, *
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37 * robust, strictly quality controlled, supported, and cross *
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38 * platform software that is more than just the market leader, it *
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39 * is the industry's de facto standard. *
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41 * Help yourself get started quickly while simultaneously helping *
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42 * to support the FreeRTOS project by purchasing a FreeRTOS *
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43 * tutorial book, reference manual, or both: *
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44 * http://www.FreeRTOS.org/Documentation *
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46 ***************************************************************************
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48 ***************************************************************************
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50 * Investing in training allows your team to be as productive as *
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51 * possible as early as possible, lowering your overall development *
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52 * cost, and enabling you to bring a more robust product to market *
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53 * earlier than would otherwise be possible. Richard Barry is both *
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54 * the architect and key author of FreeRTOS, and so also the world's *
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55 * leading authority on what is the world's most popular real time *
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56 * kernel for deeply embedded MCU designs. Obtaining your training *
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57 * from Richard ensures your team will gain directly from his in-depth *
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58 * product knowledge and years of usage experience. Contact Real Time *
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59 * Engineers Ltd to enquire about the FreeRTOS Masterclass, presented *
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60 * by Richard Barry: http://www.FreeRTOS.org/contact
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62 ***************************************************************************
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64 ***************************************************************************
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66 * You are receiving this top quality software for free. Please play *
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67 * fair and reciprocate by reporting any suspected issues and *
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68 * participating in the community forum: *
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69 * http://www.FreeRTOS.org/support *
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73 ***************************************************************************
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75 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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76 license and Real Time Engineers Ltd. contact details.
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78 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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79 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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80 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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82 http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
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83 Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
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85 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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86 Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
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87 licenses offer ticketed support, indemnification and commercial middleware.
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89 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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90 engineered and independently SIL3 certified version for use in safety and
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91 mission critical applications that require provable dependability.
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96 /* Hardware specific includes. */
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97 #include "iodefine.h"
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98 #include "typedefine.h"
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99 #include "r_ether.h"
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102 /* FreeRTOS includes. */
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103 #include "FreeRTOS.h"
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105 #include "semphr.h"
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107 /* uIP includes. */
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108 #include "net/uip.h"
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110 /* The time to wait between attempts to obtain a free buffer. */
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111 #define emacBUFFER_WAIT_DELAY_ms ( 3 / portTICK_PERIOD_MS )
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113 /* The number of times emacBUFFER_WAIT_DELAY_ms should be waited before giving
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114 up on attempting to obtain a free buffer all together. */
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115 #define emacBUFFER_WAIT_ATTEMPTS ( 30 )
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117 /* The number of Rx descriptors. */
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118 #define emacNUM_RX_DESCRIPTORS 8
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120 /* The number of Tx descriptors. When using uIP there is not point in having
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122 #define emacNUM_TX_BUFFERS 2
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124 /* The total number of EMAC buffers to allocate. */
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125 #define emacNUM_BUFFERS ( emacNUM_RX_DESCRIPTORS + emacNUM_TX_BUFFERS )
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127 /* The time to wait for the Tx descriptor to become free. */
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128 #define emacTX_WAIT_DELAY_ms ( 10 / portTICK_PERIOD_MS )
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130 /* The total number of times to wait emacTX_WAIT_DELAY_ms for the Tx descriptor to
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132 #define emacTX_WAIT_ATTEMPTS ( 50 )
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134 /* Only Rx end and Tx end interrupts are used by this driver. */
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135 #define emacTX_END_INTERRUPT ( 1UL << 21UL )
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136 #define emacRX_END_INTERRUPT ( 1UL << 18UL )
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138 /*-----------------------------------------------------------*/
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140 /* The buffers and descriptors themselves. */
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141 static volatile ethfifo xRxDescriptors[ emacNUM_RX_DESCRIPTORS ] __attribute__((aligned(16)));
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142 static volatile ethfifo xTxDescriptors[ emacNUM_TX_BUFFERS ] __attribute__((aligned(16)));
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143 static char xEthernetBuffers[ emacNUM_BUFFERS ][ UIP_BUFSIZE ] __attribute__((aligned(16)));
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145 /* Used to indicate which buffers are free and which are in use. If an index
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146 contains 0 then the corresponding buffer in xEthernetBuffers is free, otherwise
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147 the buffer is in use or about to be used. */
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148 static unsigned char ucBufferInUse[ emacNUM_BUFFERS ];
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150 /*-----------------------------------------------------------*/
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153 * Initialise both the Rx and Tx descriptors.
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155 static void prvInitialiseDescriptors( void );
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158 * Return a pointer to a free buffer within xEthernetBuffers.
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160 static unsigned char *prvGetNextBuffer( void );
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163 * Return a buffer to the list of free buffers.
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165 static void prvReturnBuffer( unsigned char *pucBuffer );
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168 * Examine the status of the next Rx FIFO to see if it contains new data.
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170 static unsigned long prvCheckRxFifoStatus( void );
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173 * Setup the microcontroller for communication with the PHY.
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175 static void prvResetMAC( void );
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178 * Configure the Ethernet interface peripherals.
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180 static void prvConfigureEtherCAndEDMAC( void );
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183 * Something has gone wrong with the descriptor usage. Reset all the buffers
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186 static void prvResetEverything( void );
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189 * Handler for the EMAC peripheral. See the documentation for this
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190 * port on http://www.FreeRTOS.org for more information on defining interrupt
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193 void vEMAC_ISR_Handler( void ) __attribute__((interrupt));
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195 /*-----------------------------------------------------------*/
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197 /* Points to the Rx descriptor currently in use. */
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198 static ethfifo *pxCurrentRxDesc = NULL;
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200 /* The buffer used by the uIP stack to both receive and send. This points to
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201 one of the Ethernet buffers when its actually in use. */
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202 unsigned char *uip_buf = NULL;
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204 /*-----------------------------------------------------------*/
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206 void vInitEmac( void )
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208 /* Software reset. */
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211 /* Set the Rx and Tx descriptors into their initial state. */
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212 prvInitialiseDescriptors();
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214 /* Set the MAC address into the ETHERC */
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215 ETHERC.MAHR = ( ( unsigned long ) configMAC_ADDR0 << 24UL ) |
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216 ( ( unsigned long ) configMAC_ADDR1 << 16UL ) |
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217 ( ( unsigned long ) configMAC_ADDR2 << 8UL ) |
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218 ( unsigned long ) configMAC_ADDR3;
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220 ETHERC.MALR.BIT.MA = ( ( unsigned long ) configMAC_ADDR4 << 8UL ) |
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221 ( unsigned long ) configMAC_ADDR5;
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223 /* Perform rest of interface hardware configuration. */
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224 prvConfigureEtherCAndEDMAC();
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226 /* Nothing received yet, so uip_buf points nowhere. */
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229 /* Initialize the PHY */
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232 /*-----------------------------------------------------------*/
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234 void vEMACWrite( void )
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238 /* Wait until the second transmission of the last packet has completed. */
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239 for( x = 0; x < emacTX_WAIT_ATTEMPTS; x++ )
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241 if( ( xTxDescriptors[ 1 ].status & ACT ) != 0 )
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243 /* Descriptor is still active. */
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244 vTaskDelay( emacTX_WAIT_DELAY_ms );
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252 /* Is the descriptor free after waiting for it? */
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253 if( ( xTxDescriptors[ 1 ].status & ACT ) != 0 )
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255 /* Something has gone wrong. */
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256 prvResetEverything();
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259 /* Setup both descriptors to transmit the frame. */
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260 xTxDescriptors[ 0 ].buf_p = ( char * ) uip_buf;
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261 xTxDescriptors[ 0 ].bufsize = uip_len;
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262 xTxDescriptors[ 1 ].buf_p = ( char * ) uip_buf;
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263 xTxDescriptors[ 1 ].bufsize = uip_len;
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265 /* uip_buf is being sent by the Tx descriptor. Allocate a new buffer
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266 for use by the stack. */
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267 uip_buf = prvGetNextBuffer();
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269 /* Clear previous settings and go. */
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270 xTxDescriptors[0].status &= ~( FP1 | FP0 );
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271 xTxDescriptors[0].status |= ( FP1 | FP0 | ACT );
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272 xTxDescriptors[1].status &= ~( FP1 | FP0 );
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273 xTxDescriptors[1].status |= ( FP1 | FP0 | ACT );
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275 EDMAC.EDTRR.LONG = 0x00000001;
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277 /*-----------------------------------------------------------*/
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279 unsigned long ulEMACRead( void )
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281 unsigned long ulBytesReceived;
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283 ulBytesReceived = prvCheckRxFifoStatus();
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285 if( ulBytesReceived > 0 )
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287 /* Mark the pxDescriptor buffer as free as uip_buf is going to be set to
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288 the buffer that contains the received data. */
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289 prvReturnBuffer( uip_buf );
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291 /* Point uip_buf to the data about ot be processed. */
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292 uip_buf = ( void * ) pxCurrentRxDesc->buf_p;
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294 /* Allocate a new buffer to the descriptor, as uip_buf is now using it's
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296 pxCurrentRxDesc->buf_p = ( char * ) prvGetNextBuffer();
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298 /* Prepare the descriptor to go again. */
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299 pxCurrentRxDesc->status &= ~( FP1 | FP0 );
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300 pxCurrentRxDesc->status |= ACT;
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302 /* Move onto the next buffer in the ring. */
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303 pxCurrentRxDesc = pxCurrentRxDesc->next;
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305 if( EDMAC.EDRRR.LONG == 0x00000000L )
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307 /* Restart Ethernet if it has stopped */
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308 EDMAC.EDRRR.LONG = 0x00000001L;
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312 return ulBytesReceived;
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314 /*-----------------------------------------------------------*/
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316 long lEMACWaitForLink( void )
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320 /* Set the link status. */
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321 switch( phy_set_autonegotiate() )
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323 /* Half duplex link */
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324 case PHY_LINK_100H:
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325 ETHERC.ECMR.BIT.DM = 0;
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326 ETHERC.ECMR.BIT.RTM = 1;
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331 ETHERC.ECMR.BIT.DM = 0;
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332 ETHERC.ECMR.BIT.RTM = 0;
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337 /* Full duplex link */
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338 case PHY_LINK_100F:
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339 ETHERC.ECMR.BIT.DM = 1;
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340 ETHERC.ECMR.BIT.RTM = 1;
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345 ETHERC.ECMR.BIT.DM = 1;
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346 ETHERC.ECMR.BIT.RTM = 0;
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355 if( lReturn == pdPASS )
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357 /* Enable receive and transmit. */
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358 ETHERC.ECMR.BIT.RE = 1;
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359 ETHERC.ECMR.BIT.TE = 1;
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361 /* Enable EDMAC receive */
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362 EDMAC.EDRRR.LONG = 0x1;
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367 /*-----------------------------------------------------------*/
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369 static void prvInitialiseDescriptors( void )
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371 volatile ethfifo *pxDescriptor;
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374 for( x = 0; x < emacNUM_BUFFERS; x++ )
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376 /* Ensure none of the buffers are shown as in use at the start. */
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377 ucBufferInUse[ x ] = pdFALSE;
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380 /* Initialise the Rx descriptors. */
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381 for( x = 0; x < emacNUM_RX_DESCRIPTORS; x++ )
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383 pxDescriptor = &( xRxDescriptors[ x ] );
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384 pxDescriptor->buf_p = &( xEthernetBuffers[ x ][ 0 ] );
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386 pxDescriptor->bufsize = UIP_BUFSIZE;
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387 pxDescriptor->size = 0;
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388 pxDescriptor->status = ACT;
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389 pxDescriptor->next = ( struct Descriptor * ) &xRxDescriptors[ x + 1 ];
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391 /* Mark this buffer as in use. */
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392 ucBufferInUse[ x ] = pdTRUE;
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395 /* The last descriptor points back to the start. */
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396 pxDescriptor->status |= DL;
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397 pxDescriptor->next = ( struct Descriptor * ) &xRxDescriptors[ 0 ];
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399 /* Initialise the Tx descriptors. */
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400 for( x = 0; x < emacNUM_TX_BUFFERS; x++ )
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402 pxDescriptor = &( xTxDescriptors[ x ] );
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404 /* A buffer is not allocated to the Tx descriptor until a send is
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405 actually required. */
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406 pxDescriptor->buf_p = NULL;
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408 pxDescriptor->bufsize = UIP_BUFSIZE;
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409 pxDescriptor->size = 0;
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410 pxDescriptor->status = 0;
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411 pxDescriptor->next = ( struct Descriptor * ) &xTxDescriptors[ x + 1 ];
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414 /* The last descriptor points back to the start. */
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415 pxDescriptor->status |= DL;
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416 pxDescriptor->next = ( struct Descriptor * ) &( xTxDescriptors[ 0 ] );
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418 /* Use the first Rx descriptor to start with. */
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419 pxCurrentRxDesc = ( struct Descriptor * ) &( xRxDescriptors[ 0 ] );
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421 /*-----------------------------------------------------------*/
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423 static unsigned char *prvGetNextBuffer( void )
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426 unsigned char *pucReturn = NULL;
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427 unsigned long ulAttempts = 0;
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429 while( pucReturn == NULL )
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431 /* Look through the buffers to find one that is not in use by
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433 for( x = 0; x < emacNUM_BUFFERS; x++ )
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435 if( ucBufferInUse[ x ] == pdFALSE )
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437 ucBufferInUse[ x ] = pdTRUE;
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438 pucReturn = ( unsigned char * ) &( xEthernetBuffers[ x ][ 0 ] );
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443 /* Was a buffer found? */
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444 if( pucReturn == NULL )
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448 if( ulAttempts >= emacBUFFER_WAIT_ATTEMPTS )
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453 /* Wait then look again. */
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454 vTaskDelay( emacBUFFER_WAIT_DELAY_ms );
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460 /*-----------------------------------------------------------*/
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462 static void prvReturnBuffer( unsigned char *pucBuffer )
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466 /* Return a buffer to the pool of free buffers. */
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467 for( ul = 0; ul < emacNUM_BUFFERS; ul++ )
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469 if( &( xEthernetBuffers[ ul ][ 0 ] ) == ( void * ) pucBuffer )
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471 ucBufferInUse[ ul ] = pdFALSE;
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476 /*-----------------------------------------------------------*/
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478 static void prvResetEverything( void )
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480 /* Temporary code just to see if this gets called. This function has not
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481 been implemented. */
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482 portDISABLE_INTERRUPTS();
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485 /*-----------------------------------------------------------*/
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487 static unsigned long prvCheckRxFifoStatus( void )
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489 unsigned long ulReturn = 0;
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491 if( ( pxCurrentRxDesc->status & ACT ) != 0 )
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493 /* Current descriptor is still active. */
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495 else if( ( pxCurrentRxDesc->status & FE ) != 0 )
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497 /* Frame error. Clear the error. */
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498 pxCurrentRxDesc->status &= ~( FP1 | FP0 | FE );
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499 pxCurrentRxDesc->status &= ~( RMAF | RRF | RTLF | RTSF | PRE | CERF );
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500 pxCurrentRxDesc->status |= ACT;
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501 pxCurrentRxDesc = pxCurrentRxDesc->next;
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503 if( EDMAC.EDRRR.LONG == 0x00000000UL )
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505 /* Restart Ethernet if it has stopped. */
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506 EDMAC.EDRRR.LONG = 0x00000001UL;
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511 /* The descriptor contains a frame. Because of the size of the buffers
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512 the frame should always be complete. */
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513 if( ( pxCurrentRxDesc->status & FP0 ) == FP0 )
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515 ulReturn = pxCurrentRxDesc->size;
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519 /* Do not expect to get here. */
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520 prvResetEverything();
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526 /*-----------------------------------------------------------*/
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528 static void prvResetMAC( void )
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530 /* Ensure the EtherC and EDMAC are enabled. */
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531 SYSTEM.MSTPCRB.BIT.MSTPB15 = 0;
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532 vTaskDelay( 100 / portTICK_PERIOD_MS );
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534 EDMAC.EDMR.BIT.SWR = 1;
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536 /* Crude wait for reset to complete. */
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537 vTaskDelay( 500 / portTICK_PERIOD_MS );
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539 /*-----------------------------------------------------------*/
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541 static void prvConfigureEtherCAndEDMAC( void )
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543 /* Initialisation code taken from Renesas example project. */
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545 /* TODO: Check bit 5 */
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546 ETHERC.ECSR.LONG = 0x00000037; /* Clear all ETHERC statuS BFR, PSRTO, LCHNG, MPD, ICD */
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548 /* Set the EDMAC interrupt priority. */
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549 _IPR( _ETHER_EINT ) = configKERNEL_INTERRUPT_PRIORITY;
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551 /* TODO: Check bit 5 */
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552 /* Enable interrupts of interest only. */
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553 EDMAC.EESIPR.LONG = emacTX_END_INTERRUPT | emacRX_END_INTERRUPT;
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554 ETHERC.RFLR.LONG = 1518; /* Ether payload is 1500+ CRC */
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555 ETHERC.IPGR.LONG = 0x00000014; /* Intergap is 96-bit time */
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558 EDMAC.EESR.LONG = 0x47FF0F9F; /* Clear all ETHERC and EDMAC status bits */
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559 #ifdef __RX_LITTLE_ENDIAN__
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560 EDMAC.EDMR.BIT.DE = 1;
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562 EDMAC.RDLAR = ( void * ) pxCurrentRxDesc; /* Initialaize Rx Descriptor List Address */
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563 EDMAC.TDLAR = ( void * ) &( xTxDescriptors[ 0 ] ); /* Initialaize Tx Descriptor List Address */
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564 EDMAC.TRSCER.LONG = 0x00000000; /* Copy-back status is RFE & TFE only */
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565 EDMAC.TFTR.LONG = 0x00000000; /* Threshold of Tx_FIFO */
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566 EDMAC.FDR.LONG = 0x00000000; /* Transmit fifo & receive fifo is 256 bytes */
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567 EDMAC.RMCR.LONG = 0x00000003; /* Receive function is normal mode(continued) */
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568 ETHERC.ECMR.BIT.PRM = 0; /* Ensure promiscuous mode is off. */
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570 /* Enable the interrupt... */
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571 _IEN( _ETHER_EINT ) = 1;
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573 /*-----------------------------------------------------------*/
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575 void vEMAC_ISR_Handler( void )
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577 unsigned long ul = EDMAC.EESR.LONG;
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578 long lHigherPriorityTaskWoken = pdFALSE;
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579 extern QueueHandle_t xEMACEventQueue;
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580 const unsigned long ulRxEvent = uipETHERNET_RX_EVENT;
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582 /* Re-enabled interrupts. */
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583 __asm volatile( "SETPSW I" );
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585 /* Has a Tx end occurred? */
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586 if( ul & emacTX_END_INTERRUPT )
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588 /* Only return the buffer to the pool once both Txes have completed. */
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589 prvReturnBuffer( ( void * ) xTxDescriptors[ 0 ].buf_p );
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590 EDMAC.EESR.LONG = emacTX_END_INTERRUPT;
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593 /* Has an Rx end occurred? */
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594 if( ul & emacRX_END_INTERRUPT )
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596 /* Make sure the Ethernet task is not blocked waiting for a packet. */
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597 xQueueSendFromISR( xEMACEventQueue, &ulRxEvent, &lHigherPriorityTaskWoken );
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598 portYIELD_FROM_ISR( lHigherPriorityTaskWoken );
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599 EDMAC.EESR.LONG = emacRX_END_INTERRUPT;
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