2 FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
\r
5 ***************************************************************************
\r
7 * FreeRTOS tutorial books are available in pdf and paperback. *
\r
8 * Complete, revised, and edited pdf reference manuals are also *
\r
11 * Purchasing FreeRTOS documentation will not only help you, by *
\r
12 * ensuring you get running as quickly as possible and with an *
\r
13 * in-depth knowledge of how to use FreeRTOS, it will also help *
\r
14 * the FreeRTOS project to continue with its mission of providing *
\r
15 * professional grade, cross platform, de facto standard solutions *
\r
16 * for microcontrollers - completely free of charge! *
\r
18 * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
\r
20 * Thank you for using FreeRTOS, and thank you for your support! *
\r
22 ***************************************************************************
\r
25 This file is part of the FreeRTOS distribution.
\r
27 FreeRTOS is free software; you can redistribute it and/or modify it under
\r
28 the terms of the GNU General Public License (version 2) as published by the
\r
29 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
\r
30 >>>NOTE<<< The modification to the GPL is included to allow you to
\r
31 distribute a combined work that includes FreeRTOS without being obliged to
\r
32 provide the source code for proprietary components outside of the FreeRTOS
\r
33 kernel. FreeRTOS is distributed in the hope that it will be useful, but
\r
34 WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
\r
35 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
\r
36 more details. You should have received a copy of the GNU General Public
\r
37 License and the FreeRTOS license exception along with FreeRTOS; if not it
\r
38 can be viewed here: http://www.freertos.org/a00114.html and also obtained
\r
39 by writing to Richard Barry, contact details for whom are available on the
\r
44 ***************************************************************************
\r
46 * Having a problem? Start by reading the FAQ "My application does *
\r
47 * not run, what could be wrong? *
\r
49 * http://www.FreeRTOS.org/FAQHelp.html *
\r
51 ***************************************************************************
\r
54 http://www.FreeRTOS.org - Documentation, training, latest information,
\r
55 license and contact details.
\r
57 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
\r
58 including FreeRTOS+Trace - an indispensable productivity tool.
\r
60 Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
\r
61 the code with commercial support, indemnification, and middleware, under
\r
62 the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
\r
63 provide a safety engineered and independently SIL3 certified version under
\r
64 the SafeRTOS brand: http://www.SafeRTOS.com.
\r
67 /* Hardware specific includes. */
\r
68 #include "iodefine.h"
\r
69 #include "typedefine.h"
\r
70 #include "r_ether.h"
\r
73 /* FreeRTOS includes. */
\r
74 #include "FreeRTOS.h"
\r
79 #include "net/uip.h"
\r
81 /* The time to wait between attempts to obtain a free buffer. */
\r
82 #define emacBUFFER_WAIT_DELAY_ms ( 3 / portTICK_RATE_MS )
\r
84 /* The number of times emacBUFFER_WAIT_DELAY_ms should be waited before giving
\r
85 up on attempting to obtain a free buffer all together. */
\r
86 #define emacBUFFER_WAIT_ATTEMPTS ( 30 )
\r
88 /* The number of Rx descriptors. */
\r
89 #define emacNUM_RX_DESCRIPTORS 8
\r
91 /* The number of Tx descriptors. When using uIP there is not point in having
\r
93 #define emacNUM_TX_BUFFERS 2
\r
95 /* The total number of EMAC buffers to allocate. */
\r
96 #define emacNUM_BUFFERS ( emacNUM_RX_DESCRIPTORS + emacNUM_TX_BUFFERS )
\r
98 /* The time to wait for the Tx descriptor to become free. */
\r
99 #define emacTX_WAIT_DELAY_ms ( 10 / portTICK_RATE_MS )
\r
101 /* The total number of times to wait emacTX_WAIT_DELAY_ms for the Tx descriptor to
\r
103 #define emacTX_WAIT_ATTEMPTS ( 50 )
\r
105 /* Only Rx end and Tx end interrupts are used by this driver. */
\r
106 #define emacTX_END_INTERRUPT ( 1UL << 21UL )
\r
107 #define emacRX_END_INTERRUPT ( 1UL << 18UL )
\r
109 /*-----------------------------------------------------------*/
\r
111 /* The buffers and descriptors themselves. */
\r
112 #pragma section _RX_DESC
\r
113 volatile ethfifo xRxDescriptors[ emacNUM_RX_DESCRIPTORS ];
\r
114 #pragma section _TX_DESC
\r
115 volatile ethfifo xTxDescriptors[ emacNUM_TX_BUFFERS ];
\r
116 #pragma section _ETHERNET_BUFFERS
\r
119 unsigned long ulAlignmentVariable;
\r
120 char cBuffer[ emacNUM_BUFFERS ][ UIP_BUFSIZE ];
\r
121 } xEthernetBuffers;
\r
127 /* Used to indicate which buffers are free and which are in use. If an index
\r
128 contains 0 then the corresponding buffer in xEthernetBuffers is free, otherwise
\r
129 the buffer is in use or about to be used. */
\r
130 static unsigned char ucBufferInUse[ emacNUM_BUFFERS ];
\r
132 /*-----------------------------------------------------------*/
\r
135 * Initialise both the Rx and Tx descriptors.
\r
137 static void prvInitialiseDescriptors( void );
\r
140 * Return a pointer to a free buffer within xEthernetBuffers.
\r
142 static unsigned char *prvGetNextBuffer( void );
\r
145 * Return a buffer to the list of free buffers.
\r
147 static void prvReturnBuffer( unsigned char *pucBuffer );
\r
150 * Examine the status of the next Rx FIFO to see if it contains new data.
\r
152 static unsigned long prvCheckRxFifoStatus( void );
\r
155 * Setup the microcontroller for communication with the PHY.
\r
157 static void prvResetMAC( void );
\r
160 * Configure the Ethernet interface peripherals.
\r
162 static void prvConfigureEtherCAndEDMAC( void );
\r
165 * Something has gone wrong with the descriptor usage. Reset all the buffers
\r
168 static void prvResetEverything( void );
\r
170 /*-----------------------------------------------------------*/
\r
172 /* Points to the Rx descriptor currently in use. */
\r
173 static ethfifo *pxCurrentRxDesc = NULL;
\r
175 /* The buffer used by the uIP stack to both receive and send. This points to
\r
176 one of the Ethernet buffers when its actually in use. */
\r
177 unsigned char *uip_buf = NULL;
\r
179 /*-----------------------------------------------------------*/
\r
181 void vInitEmac( void )
\r
183 /* Software reset. */
\r
186 /* Set the Rx and Tx descriptors into their initial state. */
\r
187 prvInitialiseDescriptors();
\r
189 /* Set the MAC address into the ETHERC */
\r
190 ETHERC.MAHR = ( ( unsigned long ) configMAC_ADDR0 << 24UL ) |
\r
191 ( ( unsigned long ) configMAC_ADDR1 << 16UL ) |
\r
192 ( ( unsigned long ) configMAC_ADDR2 << 8UL ) |
\r
193 ( unsigned long ) configMAC_ADDR3;
\r
195 ETHERC.MALR.BIT.MA = ( ( unsigned long ) configMAC_ADDR4 << 8UL ) |
\r
196 ( unsigned long ) configMAC_ADDR5;
\r
198 /* Perform rest of interface hardware configuration. */
\r
199 prvConfigureEtherCAndEDMAC();
\r
201 /* Nothing received yet, so uip_buf points nowhere. */
\r
204 /* Initialize the PHY */
\r
207 /*-----------------------------------------------------------*/
\r
209 void vEMACWrite( void )
\r
213 /* Wait until the second transmission of the last packet has completed. */
\r
214 for( x = 0; x < emacTX_WAIT_ATTEMPTS; x++ )
\r
216 if( ( xTxDescriptors[ 1 ].status & ACT ) != 0 )
\r
218 /* Descriptor is still active. */
\r
219 vTaskDelay( emacTX_WAIT_DELAY_ms );
\r
227 /* Is the descriptor free after waiting for it? */
\r
228 if( ( xTxDescriptors[ 1 ].status & ACT ) != 0 )
\r
230 /* Something has gone wrong. */
\r
231 prvResetEverything();
\r
234 /* Setup both descriptors to transmit the frame. */
\r
235 xTxDescriptors[ 0 ].buf_p = ( char * ) uip_buf;
\r
236 xTxDescriptors[ 0 ].bufsize = uip_len;
\r
237 xTxDescriptors[ 1 ].buf_p = ( char * ) uip_buf;
\r
238 xTxDescriptors[ 1 ].bufsize = uip_len;
\r
240 /* uip_buf is being sent by the Tx descriptor. Allocate a new buffer
\r
241 for use by the stack. */
\r
242 uip_buf = prvGetNextBuffer();
\r
244 /* Clear previous settings and go. */
\r
245 xTxDescriptors[0].status &= ~( FP1 | FP0 );
\r
246 xTxDescriptors[0].status |= ( FP1 | FP0 | ACT );
\r
247 xTxDescriptors[1].status &= ~( FP1 | FP0 );
\r
248 xTxDescriptors[1].status |= ( FP1 | FP0 | ACT );
\r
250 EDMAC.EDTRR.LONG = 0x00000001;
\r
252 /*-----------------------------------------------------------*/
\r
254 unsigned long ulEMACRead( void )
\r
256 unsigned long ulBytesReceived;
\r
258 ulBytesReceived = prvCheckRxFifoStatus();
\r
260 if( ulBytesReceived > 0 )
\r
262 /* Mark the pxDescriptor buffer as free as uip_buf is going to be set to
\r
263 the buffer that contains the received data. */
\r
264 prvReturnBuffer( uip_buf );
\r
266 /* Point uip_buf to the data about ot be processed. */
\r
267 uip_buf = ( void * ) pxCurrentRxDesc->buf_p;
\r
269 /* Allocate a new buffer to the descriptor, as uip_buf is now using it's
\r
271 pxCurrentRxDesc->buf_p = prvGetNextBuffer();
\r
273 /* Prepare the descriptor to go again. */
\r
274 pxCurrentRxDesc->status &= ~( FP1 | FP0 );
\r
275 pxCurrentRxDesc->status |= ACT;
\r
277 /* Move onto the next buffer in the ring. */
\r
278 pxCurrentRxDesc = pxCurrentRxDesc->next;
\r
280 if( EDMAC.EDRRR.LONG == 0x00000000L )
\r
282 /* Restart Ethernet if it has stopped */
\r
283 EDMAC.EDRRR.LONG = 0x00000001L;
\r
287 return ulBytesReceived;
\r
289 /*-----------------------------------------------------------*/
\r
291 long lEMACWaitForLink( void )
\r
295 /* Set the link status. */
\r
296 switch( phy_set_autonegotiate() )
\r
298 /* Half duplex link */
\r
299 case PHY_LINK_100H:
\r
300 ETHERC.ECMR.BIT.DM = 0;
\r
301 ETHERC.ECMR.BIT.RTM = 1;
\r
306 ETHERC.ECMR.BIT.DM = 0;
\r
307 ETHERC.ECMR.BIT.RTM = 0;
\r
312 /* Full duplex link */
\r
313 case PHY_LINK_100F:
\r
314 ETHERC.ECMR.BIT.DM = 1;
\r
315 ETHERC.ECMR.BIT.RTM = 1;
\r
320 ETHERC.ECMR.BIT.DM = 1;
\r
321 ETHERC.ECMR.BIT.RTM = 0;
\r
330 if( lReturn == pdPASS )
\r
332 /* Enable receive and transmit. */
\r
333 ETHERC.ECMR.BIT.RE = 1;
\r
334 ETHERC.ECMR.BIT.TE = 1;
\r
336 /* Enable EDMAC receive */
\r
337 EDMAC.EDRRR.LONG = 0x1;
\r
342 /*-----------------------------------------------------------*/
\r
344 static void prvInitialiseDescriptors( void )
\r
346 ethfifo *pxDescriptor;
\r
349 for( x = 0; x < emacNUM_BUFFERS; x++ )
\r
351 /* Ensure none of the buffers are shown as in use at the start. */
\r
352 ucBufferInUse[ x ] = pdFALSE;
\r
355 /* Initialise the Rx descriptors. */
\r
356 for( x = 0; x < emacNUM_RX_DESCRIPTORS; x++ )
\r
358 pxDescriptor = &( xRxDescriptors[ x ] );
\r
359 pxDescriptor->buf_p = &( xEthernetBuffers.cBuffer[ x ][ 0 ] );
\r
361 pxDescriptor->bufsize = UIP_BUFSIZE;
\r
362 pxDescriptor->size = 0;
\r
363 pxDescriptor->status = ACT;
\r
364 pxDescriptor->next = &xRxDescriptors[ x + 1 ];
\r
366 /* Mark this buffer as in use. */
\r
367 ucBufferInUse[ x ] = pdTRUE;
\r
370 /* The last descriptor points back to the start. */
\r
371 pxDescriptor->status |= DL;
\r
372 pxDescriptor->next = &xRxDescriptors[ 0 ];
\r
374 /* Initialise the Tx descriptors. */
\r
375 for( x = 0; x < emacNUM_TX_BUFFERS; x++ )
\r
377 pxDescriptor = &( xTxDescriptors[ x ] );
\r
379 /* A buffer is not allocated to the Tx descriptor until a send is
\r
380 actually required. */
\r
381 pxDescriptor->buf_p = NULL;
\r
383 pxDescriptor->bufsize = UIP_BUFSIZE;
\r
384 pxDescriptor->size = 0;
\r
385 pxDescriptor->status = 0;
\r
386 pxDescriptor->next = &xTxDescriptors[ x + 1 ];
\r
389 /* The last descriptor points back to the start. */
\r
390 pxDescriptor->status |= DL;
\r
391 pxDescriptor->next = &( xTxDescriptors[ 0 ] );
\r
393 /* Use the first Rx descriptor to start with. */
\r
394 pxCurrentRxDesc = &( xRxDescriptors[ 0 ] );
\r
396 /*-----------------------------------------------------------*/
\r
398 static unsigned char *prvGetNextBuffer( void )
\r
401 unsigned char *pucReturn = NULL;
\r
402 unsigned long ulAttempts = 0;
\r
404 while( pucReturn == NULL )
\r
406 /* Look through the buffers to find one that is not in use by
\r
408 for( x = 0; x < emacNUM_BUFFERS; x++ )
\r
410 if( ucBufferInUse[ x ] == pdFALSE )
\r
412 ucBufferInUse[ x ] = pdTRUE;
\r
413 pucReturn = ( unsigned char * ) &( xEthernetBuffers.cBuffer[ x ][ 0 ] );
\r
418 /* Was a buffer found? */
\r
419 if( pucReturn == NULL )
\r
423 if( ulAttempts >= emacBUFFER_WAIT_ATTEMPTS )
\r
428 /* Wait then look again. */
\r
429 vTaskDelay( emacBUFFER_WAIT_DELAY_ms );
\r
435 /*-----------------------------------------------------------*/
\r
437 static void prvReturnBuffer( unsigned char *pucBuffer )
\r
441 /* Return a buffer to the pool of free buffers. */
\r
442 for( ul = 0; ul < emacNUM_BUFFERS; ul++ )
\r
444 if( &( xEthernetBuffers.cBuffer[ ul ][ 0 ] ) == ( void * ) pucBuffer )
\r
446 ucBufferInUse[ ul ] = pdFALSE;
\r
451 /*-----------------------------------------------------------*/
\r
453 static void prvResetEverything( void )
\r
455 /* Temporary code just to see if this gets called. This function has not
\r
456 been implemented. */
\r
457 portDISABLE_INTERRUPTS();
\r
460 /*-----------------------------------------------------------*/
\r
462 static unsigned long prvCheckRxFifoStatus( void )
\r
464 unsigned long ulReturn = 0;
\r
466 if( ( pxCurrentRxDesc->status & ACT ) != 0 )
\r
468 /* Current descriptor is still active. */
\r
470 else if( ( pxCurrentRxDesc->status & FE ) != 0 )
\r
472 /* Frame error. Clear the error. */
\r
473 pxCurrentRxDesc->status &= ~( FP1 | FP0 | FE );
\r
474 pxCurrentRxDesc->status &= ~( RMAF | RRF | RTLF | RTSF | PRE | CERF );
\r
475 pxCurrentRxDesc->status |= ACT;
\r
476 pxCurrentRxDesc = pxCurrentRxDesc->next;
\r
478 if( EDMAC.EDRRR.LONG == 0x00000000UL )
\r
480 /* Restart Ethernet if it has stopped. */
\r
481 EDMAC.EDRRR.LONG = 0x00000001UL;
\r
486 /* The descriptor contains a frame. Because of the size of the buffers
\r
487 the frame should always be complete. */
\r
488 if( ( pxCurrentRxDesc->status & FP0 ) == FP0 )
\r
490 ulReturn = pxCurrentRxDesc->size;
\r
494 /* Do not expect to get here. */
\r
495 prvResetEverything();
\r
501 /*-----------------------------------------------------------*/
\r
503 static void prvResetMAC( void )
\r
505 /* Ensure the EtherC and EDMAC are enabled. */
\r
506 SYSTEM.MSTPCRB.BIT.MSTPB15 = 0;
\r
507 vTaskDelay( 100 / portTICK_RATE_MS );
\r
509 EDMAC.EDMR.BIT.SWR = 1;
\r
511 /* Crude wait for reset to complete. */
\r
512 vTaskDelay( 500 / portTICK_RATE_MS );
\r
514 /*-----------------------------------------------------------*/
\r
516 static void prvConfigureEtherCAndEDMAC( void )
\r
518 /* Initialisation code taken from Renesas example project. */
\r
520 /* TODO: Check bit 5 */
\r
521 ETHERC.ECSR.LONG = 0x00000037; /* Clear all ETHERC statuS BFR, PSRTO, LCHNG, MPD, ICD */
\r
523 /* Set the EDMAC interrupt priority. */
\r
524 _IPR( _ETHER_EINT ) = configKERNEL_INTERRUPT_PRIORITY;
\r
526 /* TODO: Check bit 5 */
\r
527 /* Enable interrupts of interest only. */
\r
528 EDMAC.EESIPR.LONG = emacTX_END_INTERRUPT | emacRX_END_INTERRUPT;
\r
529 ETHERC.RFLR.LONG = 1518; /* Ether payload is 1500+ CRC */
\r
530 ETHERC.IPGR.LONG = 0x00000014; /* Intergap is 96-bit time */
\r
533 EDMAC.EESR.LONG = 0x47FF0F9F; /* Clear all ETHERC and EDMAC status bits */
\r
535 EDMAC.EDMR.BIT.DE = 1;
\r
537 EDMAC.RDLAR = ( void * ) pxCurrentRxDesc; /* Initialaize Rx Descriptor List Address */
\r
538 EDMAC.TDLAR = &( xTxDescriptors[ 0 ] ); /* Initialaize Tx Descriptor List Address */
\r
539 EDMAC.TRSCER.LONG = 0x00000000; /* Copy-back status is RFE & TFE only */
\r
540 EDMAC.TFTR.LONG = 0x00000000; /* Threshold of Tx_FIFO */
\r
541 EDMAC.FDR.LONG = 0x00000000; /* Transmit fifo & receive fifo is 256 bytes */
\r
542 EDMAC.RMCR.LONG = 0x00000003; /* Receive function is normal mode(continued) */
\r
543 ETHERC.ECMR.BIT.PRM = 0; /* Ensure promiscuous mode is off. */
\r
545 /* Enable the interrupt... */
\r
546 _IEN( _ETHER_EINT ) = 1;
\r
548 /*-----------------------------------------------------------*/
\r
550 #pragma interrupt ( vEMAC_ISR_Handler( vect = VECT_ETHER_EINT, enable ) )
\r
551 void vEMAC_ISR_Handler( void )
\r
553 unsigned long ul = EDMAC.EESR.LONG;
\r
554 long lHigherPriorityTaskWoken = pdFALSE;
\r
555 extern xQueueHandle xEMACEventQueue;
\r
556 const unsigned long ulRxEvent = uipETHERNET_RX_EVENT;
\r
558 /* Has a Tx end occurred? */
\r
559 if( ul & emacTX_END_INTERRUPT )
\r
561 /* Only return the buffer to the pool once both Txes have completed. */
\r
562 prvReturnBuffer( ( void * ) xTxDescriptors[ 0 ].buf_p );
\r
563 EDMAC.EESR.LONG = emacTX_END_INTERRUPT;
\r
566 /* Has an Rx end occurred? */
\r
567 if( ul & emacRX_END_INTERRUPT )
\r
569 /* Make sure the Ethernet task is not blocked waiting for a packet. */
\r
570 xQueueSendFromISR( xEMACEventQueue, &ulRxEvent, &lHigherPriorityTaskWoken );
\r
571 portYIELD_FROM_ISR( lHigherPriorityTaskWoken );
\r
572 EDMAC.EESR.LONG = emacRX_END_INTERRUPT;
\r