1 #ifndef CGC_SET_VALUES_H_
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2 #define CGC_SET_VALUES_H_
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4 /* Do not modify these macros. These values are used to initialise
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5 the SCKCR and SCKCR2 registers based upon the above values. */
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7 #define FCLK_SCKCR 0x60000000L
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8 #elif (FCLK_DIV == 32)
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9 #define FCLK_SCKCR 0x50000000L
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10 #elif (FCLK_DIV == 16)
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11 #define FCLK_SCKCR 0x40000000L
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12 #elif (FCLK_DIV == 8)
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13 #define FCLK_SCKCR 0x30000000L
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14 #elif (FCLK_DIV == 4)
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15 #define FCLK_SCKCR 0x20000000L
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16 #elif (FCLK_DIV == 2)
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17 #define FCLK_SCKCR 0x10000000L
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18 #elif(FCLK_DIV == 1)
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19 #define FCLK_SCKCR 0x00000000L
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21 #define FCLK_SCKCR 0x10000000L
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25 #if (ICLK_DIV == 64)
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26 #define ICLK_SCKCR 0x06000000L
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27 #elif (ICLK_DIV == 32)
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28 #define ICLK_SCKCR 0x05000000L
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29 #elif (ICLK_DIV == 16)
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30 #define ICLK_SCKCR 0x04000000L
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31 #elif (ICLK_DIV == 8)
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32 #define ICLK_SCKCR 0x03000000L
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33 #elif (ICLK_DIV == 4)
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34 #define ICLK_SCKCR 0x02000000L
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35 #elif (ICLK_DIV == 2)
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36 #define ICLK_SCKCR 0x01000000L
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37 #elif (ICLK_DIV == 1)
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38 #define ICLK_SCKCR 0x00000000L
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40 #define ICLK_SCKCR 0x01000000L
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45 #define PSTOP1_SCKCR 0x00800000L
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47 #define PSTOP1_SCKCR 0x00000000L
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51 #if (BCLK_DIV == 64)
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52 #define BCLK_SCKCR 0x00060000L
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53 #elif (BCLK_DIV == 32)
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54 #define BCLK_SCKCR 0x00050000L
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55 #elif (BCLK_DIV == 16)
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56 #define BCLK_SCKCR 0x00040000L
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57 #elif (BCLK_DIV == 8)
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58 #define BCLK_SCKCR 0x00030000L
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59 #elif (BCLK_DIV == 4)
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60 #define BCLK_SCKCR 0x00020000L
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61 #elif (BCLK_DIV == 2)
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62 #define BCLK_SCKCR 0x00010000L
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63 #elif (BCLK_DIV == 1)
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64 #define BCLK_SCKCR 0x00000000L
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66 #define BCLK_SCKCR 0x00010000L
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70 #if (PCLK1215_DIV == 64)
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71 #define PCLK1215_SCKCR 0x00006000L
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72 #elif (PCLK1215_DIV == 32)
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73 #define PCLK1215_SCKCR 0x00005000L
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74 #elif (PCLK1215_DIV == 16)
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75 #define PCLK1215_SCKCR 0x00004000L
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76 #elif (PCLK1215_DIV == 8)
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77 #define PCLK1215_SCKCR 0x00003000L
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78 #elif (PCLK1215_DIV == 4)
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79 #define PCLK1215_SCKCR 0x00002000L
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80 #elif (PCLK1215_DIV == 2)
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81 #define PCLK1215_SCKCR 0x00001000L
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82 #elif (PCLK1215_DIV == 1)
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83 #define PCLK1215_SCKCR 0x00000000L
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85 #define PCLK1215_SCKCR 0x00001000L
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89 #if (PCLKB_DIV == 64)
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90 #define PCLKB_SCKCR 0x00000600L
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91 #elif (PCLKB_DIV == 32)
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92 #define PCLKB_SCKCR 0x00000500L
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93 #elif (PCLKB_DIV == 16)
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94 #define PCLKB_SCKCR 0x00000400L
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95 #elif (PCLKB_DIV == 8)
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96 #define PCLKB_SCKCR 0x00000300L
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97 #elif (PCLKB_DIV == 4)
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98 #define PCLKB_SCKCR 0x00000200L
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99 #elif (PCLKB_DIV == 2)
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100 #define PCLKB_SCKCR 0x00000100L
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101 #elif (PCLKB_DIV == 1)
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102 #define PCLKB_SCKCR 0x00000000L
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104 #define PCLKB_SCKCR 0x00000100L
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108 #if (PCLK47_DIV == 64)
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109 #define PCLK47_SCKCR 0x00000060L
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110 #elif (PCLK47_DIV == 32)
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111 #define PCLK47_SCKCR 0x00000050L
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112 #elif (PCLK47_DIV == 16)
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113 #define PCLK47_SCKCR 0x00000040L
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114 #elif (PCLK47_DIV == 8)
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115 #define PCLK47_SCKCR 0x00000030L
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116 #elif (PCLK47_DIV == 4)
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117 #define PCLK47_SCKCR 0x00000020L
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118 #elif (PCLK47_DIV == 2)
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119 #define PCLK47_SCKCR 0x00000010L
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120 #elif (PCLK47_DIV == 1)
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121 #define PCLK47_SCKCR 0x00000000L
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123 #define PCLK47_SCKCR 0x00000010L
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127 #if (PCLK03_DIV == 64)
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128 #define PCLK03_SCKCR 0x00000006L
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129 #elif (PCLK03_DIV == 32)
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130 #define PCLK03_SCKCR 0x00000005L
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131 #elif (PCLK03_DIV == 16)
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132 #define PCLK03_SCKCR 0x00000004L
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133 #elif (PCLK03_DIV == 8)
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134 #define PCLK03_SCKCR 0x00000003L
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135 #elif (PCLK03_DIV == 4)
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136 #define PCLK03_SCKCR 0x00000002L
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137 #elif (PCLK03_DIV == 2)
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138 #define PCLK03_SCKCR 0x00000001L
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139 #elif (PCLK03_DIV == 1)
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140 #define PCLK03_SCKCR 0x00000000L
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142 #define PCLK03_SCKCR 0x00000001L
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147 #define UCK_SCKCR2 0x00C0L
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148 #elif (UCK_DIV == 64)
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149 #define UCK_SCKCR2 0x0060L
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150 #elif (UCK_DIV == 32)
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151 #define UCK_SCKCR2 0x0050L
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152 #elif (UCK_DIV == 16)
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153 #define UCK_SCKCR2 0x0040L
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154 #elif (UCK_DIV == 8)
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155 #define UCK_SCKCR2 0x0030L
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156 #elif (UCK_DIV == 4)
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157 #define UCK_SCKCR2 0x0020L
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158 #elif (UCK_DIV == 2)
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159 #define UCK_SCKCR2 0x0010L
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161 #define UCK_SCKCR2 0x0010L
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165 #if (IEBCK_DIV == 3)
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166 #define IEBCK_SCKCR2 0x00000020L
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167 #elif (IEBCK_DIV == 4)
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168 #define IEBCK_SCKCR2 0x00000030L
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170 #define IEBCK_SCKCR2 0x00000030L
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174 #if (CLK_SOURCE == CLK_SOURCE_LOCO)
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175 /* Internal LOCO circuit - 125kHz*/
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176 #define CLK_FREQUENCY (125000L)
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177 #define FCLK_FREQUENCY (CLK_FREQUENCY / FCLK_DIV)
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178 #define ICLK_FREQUENCY (CLK_FREQUENCY / ICLK_DIV)
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179 #define BCLK_FREQUENCY (CLK_FREQUENCY / BCLK_DIV)
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180 #define PCLKA_FREQUENCY (CLK_FREQUENCY / PCLK1215_DIV)
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181 #define PCLKB_FREQUENCY (CLK_FREQUENCY / PCLKB_DIV)
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182 #define PCLK47_FREQUENCY (CLK_FREQUENCY / PCLK47_DIV)
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183 #define PCLK03_FREQUENCY (CLK_FREQUENCY / PCLK03_DIV)
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186 #elif (CLK_SOURCE == CLK_SOURCE_HOCO)
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187 /* Internal high speed on-chip oscillator (HOCO) */
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188 #define CLK_FREQUENCY (50000000L)
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189 #define FCLK_FREQUENCY (CLK_FREQUENCY / FCLK_DIV)
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190 #define ICLK_FREQUENCY (CLK_FREQUENCY / ICLK_DIV)
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191 #define BCLK_FREQUENCY (CLK_FREQUENCY / BCLK_DIV)
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192 #define PCLKA_FREQUENCY (CLK_FREQUENCY / PCLK1215_DIV)
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193 #define PCLKB_FREQUENCY (CLK_FREQUENCY / PCLKB_DIV)
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194 #define PCLK47_FREQUENCY (CLK_FREQUENCY / PCLK47_DIV)
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195 #define PCLK03_FREQUENCY (CLK_FREQUENCY / PCLK03_DIV)
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198 #elif (CLK_SOURCE == CLK_SOURCE_MAIN)
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199 /* External XTAL, but not via the PLL circuit */
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200 #define FCLK_FREQUENCY (XTAL_FREQUENCY / FCLK_DIV)
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201 #define ICLK_FREQUENCY (XTAL_FREQUENCY / ICLK_DIV)
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202 #define BCLK_FREQUENCY (XTAL_FREQUENCY / BCLK_DIV)
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203 #define PCLKA_FREQUENCY (XTAL_FREQUENCY / PCLK1215_DIV)
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204 #define PCLKB_FREQUENCY (XTAL_FREQUENCY / PCLKB_DIV)
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205 #define PCLK47_FREQUENCY (XTAL_FREQUENCY / PCLK47_DIV)
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206 #define PCLK03_FREQUENCY (XTAL_FREQUENCY / PCLK03_DIV)
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209 #elif (CLK_SOURCE == CLK_SOURCE_SUB)
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210 /* External 32khZ XTAL */
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211 #define FCLK_FREQUENCY (SUB_FREQUENCY / FCLK_DIV)
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212 #define ICLK_FREQUENCY (SUB_FREQUENCY / ICLK_DIV)
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213 #define BCLK_FREQUENCY (SUB_FREQUENCY / BCLK_DIV)
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214 #define PCLKA_FREQUENCY (SUB_FREQUENCY / PCLK1215_DIV)
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215 #define PCLKB_FREQUENCY (SUB_FREQUENCY / PCLKB_DIV)
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216 #define PCLK47_FREQUENCY (SUB_FREQUENCY / PCLK47_DIV)
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217 #define PCLK03_FREQUENCY (SUB_FREQUENCY / PCLK03_DIV)
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220 #elif (CLK_SOURCE == CLK_SOURCE_PLL)
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221 /* External XTAL, but using the PLL circuit */
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222 #define PLL_FREQUENCY (XTAL_FREQUENCY * (PLL_MUL / PLL_INPUT_FREQ_DIV))
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223 #define FCLK_FREQUENCY (PLL_FREQUENCY / FCLK_DIV)
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224 #define ICLK_FREQUENCY (PLL_FREQUENCY / ICLK_DIV)
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225 #define BCLK_FREQUENCY (PLL_FREQUENCY / BCLK_DIV)
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226 #define PCLKA_FREQUENCY (PLL_FREQUENCY / PCLK1215_DIV)
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227 #define PCLKB_FREQUENCY (PLL_FREQUENCY / PCLKB_DIV)
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228 #define PCLK47_FREQUENCY (PLL_FREQUENCY / PCLK47_DIV)
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229 #define PCLK03_FREQUENCY (PLL_FREQUENCY / PCLK03_DIV)
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