2 FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
\r
5 ***************************************************************************
\r
7 * FreeRTOS tutorial books are available in pdf and paperback. *
\r
8 * Complete, revised, and edited pdf reference manuals are also *
\r
11 * Purchasing FreeRTOS documentation will not only help you, by *
\r
12 * ensuring you get running as quickly as possible and with an *
\r
13 * in-depth knowledge of how to use FreeRTOS, it will also help *
\r
14 * the FreeRTOS project to continue with its mission of providing *
\r
15 * professional grade, cross platform, de facto standard solutions *
\r
16 * for microcontrollers - completely free of charge! *
\r
18 * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
\r
20 * Thank you for using FreeRTOS, and thank you for your support! *
\r
22 ***************************************************************************
\r
25 This file is part of the FreeRTOS distribution.
\r
27 FreeRTOS is free software; you can redistribute it and/or modify it under
\r
28 the terms of the GNU General Public License (version 2) as published by the
\r
29 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
\r
30 >>>NOTE<<< The modification to the GPL is included to allow you to
\r
31 distribute a combined work that includes FreeRTOS without being obliged to
\r
32 provide the source code for proprietary components outside of the FreeRTOS
\r
33 kernel. FreeRTOS is distributed in the hope that it will be useful, but
\r
34 WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
\r
35 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
\r
36 more details. You should have received a copy of the GNU General Public
\r
37 License and the FreeRTOS license exception along with FreeRTOS; if not it
\r
38 can be viewed here: http://www.freertos.org/a00114.html and also obtained
\r
39 by writing to Richard Barry, contact details for whom are available on the
\r
44 ***************************************************************************
\r
46 * Having a problem? Start by reading the FAQ "My application does *
\r
47 * not run, what could be wrong? *
\r
49 * http://www.FreeRTOS.org/FAQHelp.html *
\r
51 ***************************************************************************
\r
54 http://www.FreeRTOS.org - Documentation, training, latest information,
\r
55 license and contact details.
\r
57 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
\r
58 including FreeRTOS+Trace - an indispensable productivity tool.
\r
60 Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
\r
61 the code with commercial support, indemnification, and middleware, under
\r
62 the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
\r
63 provide a safety engineered and independently SIL3 certified version under
\r
64 the SafeRTOS brand: http://www.SafeRTOS.com.
\r
67 /* FreeRTOS includes. */
\r
68 #include "FreeRTOS.h"
\r
72 /* Hardware specific includes. */
\r
73 #include "r_ether.h"
\r
77 #include "net/uip.h"
\r
79 /* The time to wait between attempts to obtain a free buffer. */
\r
80 #define emacBUFFER_WAIT_DELAY_ms ( 3 / portTICK_RATE_MS )
\r
82 /* The number of times emacBUFFER_WAIT_DELAY_ms should be waited before giving
\r
83 up on attempting to obtain a free buffer all together. */
\r
84 #define emacBUFFER_WAIT_ATTEMPTS ( 30 )
\r
86 /* The number of Rx descriptors. */
\r
87 #define emacNUM_RX_DESCRIPTORS 8
\r
89 /* The number of Tx descriptors. When using uIP there is not point in having
\r
91 #define emacNUM_TX_BUFFERS 2
\r
93 /* The total number of EMAC buffers to allocate. */
\r
94 #define emacNUM_BUFFERS ( emacNUM_RX_DESCRIPTORS + emacNUM_TX_BUFFERS )
\r
96 /* The time to wait for the Tx descriptor to become free. */
\r
97 #define emacTX_WAIT_DELAY_ms ( 10 / portTICK_RATE_MS )
\r
99 /* The total number of times to wait emacTX_WAIT_DELAY_ms for the Tx descriptor to
\r
101 #define emacTX_WAIT_ATTEMPTS ( 50 )
\r
103 /* Only Rx end and Tx end interrupts are used by this driver. */
\r
104 #define emacTX_END_INTERRUPT ( 1UL << 21UL )
\r
105 #define emacRX_END_INTERRUPT ( 1UL << 18UL )
\r
107 /*-----------------------------------------------------------*/
\r
109 /* The buffers and descriptors themselves. */
\r
110 #pragma section _RX_DESC
\r
111 volatile ethfifo xRxDescriptors[ emacNUM_RX_DESCRIPTORS ];
\r
112 #pragma section _TX_DESC
\r
113 volatile ethfifo xTxDescriptors[ emacNUM_TX_BUFFERS ];
\r
114 #pragma section _ETHERNET_BUFFERS
\r
117 unsigned long ulAlignmentVariable;
\r
118 char cBuffer[ emacNUM_BUFFERS ][ UIP_BUFSIZE ];
\r
119 } xEthernetBuffers;
\r
125 /* Used to indicate which buffers are free and which are in use. If an index
\r
126 contains 0 then the corresponding buffer in xEthernetBuffers is free, otherwise
\r
127 the buffer is in use or about to be used. */
\r
128 static unsigned char ucBufferInUse[ emacNUM_BUFFERS ];
\r
130 /*-----------------------------------------------------------*/
\r
133 * Initialise both the Rx and Tx descriptors.
\r
135 static void prvInitialiseDescriptors( void );
\r
138 * Return a pointer to a free buffer within xEthernetBuffers.
\r
140 static unsigned char *prvGetNextBuffer( void );
\r
143 * Return a buffer to the list of free buffers.
\r
145 static void prvReturnBuffer( unsigned char *pucBuffer );
\r
148 * Examine the status of the next Rx FIFO to see if it contains new data.
\r
150 static unsigned long prvCheckRxFifoStatus( void );
\r
153 * Setup the microcontroller for communication with the PHY.
\r
155 static void prvResetMAC( void );
\r
158 * Configure the Ethernet interface peripherals.
\r
160 static void prvConfigureEtherCAndEDMAC( void );
\r
163 * Something has gone wrong with the descriptor usage. Reset all the buffers
\r
166 static void prvResetEverything( void );
\r
168 /*-----------------------------------------------------------*/
\r
170 /* Points to the Rx descriptor currently in use. */
\r
171 static ethfifo *pxCurrentRxDesc = NULL;
\r
173 /* The buffer used by the uIP stack to both receive and send. This points to
\r
174 one of the Ethernet buffers when its actually in use. */
\r
175 unsigned char *uip_buf = NULL;
\r
177 /*-----------------------------------------------------------*/
\r
179 void vInitEmac( void )
\r
181 /* Software reset. */
\r
184 /* Set the Rx and Tx descriptors into their initial state. */
\r
185 prvInitialiseDescriptors();
\r
187 /* Set the MAC address into the ETHERC */
\r
188 ETHERC.MAHR = ( ( unsigned long ) configMAC_ADDR0 << 24UL ) |
\r
189 ( ( unsigned long ) configMAC_ADDR1 << 16UL ) |
\r
190 ( ( unsigned long ) configMAC_ADDR2 << 8UL ) |
\r
191 ( unsigned long ) configMAC_ADDR3;
\r
193 ETHERC.MALR.BIT.MA = ( ( unsigned long ) configMAC_ADDR4 << 8UL ) |
\r
194 ( unsigned long ) configMAC_ADDR5;
\r
196 /* Perform rest of interface hardware configuration. */
\r
197 prvConfigureEtherCAndEDMAC();
\r
199 /* Nothing received yet, so uip_buf points nowhere. */
\r
202 /* Initialize the PHY */
\r
203 configASSERT( phy_init() == R_PHY_OK );
\r
205 /*-----------------------------------------------------------*/
\r
207 void vEMACWrite( void )
\r
211 /* Wait until the second transmission of the last packet has completed. */
\r
212 for( x = 0; x < emacTX_WAIT_ATTEMPTS; x++ )
\r
214 if( ( xTxDescriptors[ 1 ].status & ACT ) != 0 )
\r
216 /* Descriptor is still active. */
\r
217 vTaskDelay( emacTX_WAIT_DELAY_ms );
\r
225 /* Is the descriptor free after waiting for it? */
\r
226 if( ( xTxDescriptors[ 1 ].status & ACT ) != 0 )
\r
228 /* Something has gone wrong. */
\r
229 prvResetEverything();
\r
232 /* Setup both descriptors to transmit the frame. */
\r
233 xTxDescriptors[ 0 ].buf_p = ( char * ) uip_buf;
\r
234 xTxDescriptors[ 0 ].bufsize = uip_len;
\r
235 xTxDescriptors[ 1 ].buf_p = ( char * ) uip_buf;
\r
236 xTxDescriptors[ 1 ].bufsize = uip_len;
\r
238 /* uip_buf is being sent by the Tx descriptor. Allocate a new buffer
\r
239 for use by the stack. */
\r
240 uip_buf = prvGetNextBuffer();
\r
242 /* Clear previous settings and go. */
\r
243 xTxDescriptors[0].status &= ~( FP1 | FP0 );
\r
244 xTxDescriptors[0].status |= ( FP1 | FP0 | ACT );
\r
245 xTxDescriptors[1].status &= ~( FP1 | FP0 );
\r
246 xTxDescriptors[1].status |= ( FP1 | FP0 | ACT );
\r
248 EDMAC.EDTRR.LONG = 0x00000001;
\r
250 /*-----------------------------------------------------------*/
\r
252 unsigned long ulEMACRead( void )
\r
254 unsigned long ulBytesReceived;
\r
256 ulBytesReceived = prvCheckRxFifoStatus();
\r
258 if( ulBytesReceived > 0 )
\r
260 /* Mark the pxDescriptor buffer as free as uip_buf is going to be set to
\r
261 the buffer that contains the received data. */
\r
262 prvReturnBuffer( uip_buf );
\r
264 /* Point uip_buf to the data about ot be processed. */
\r
265 uip_buf = ( void * ) pxCurrentRxDesc->buf_p;
\r
267 /* Allocate a new buffer to the descriptor, as uip_buf is now using it's
\r
269 pxCurrentRxDesc->buf_p = prvGetNextBuffer();
\r
271 /* Prepare the descriptor to go again. */
\r
272 pxCurrentRxDesc->status &= ~( FP1 | FP0 );
\r
273 pxCurrentRxDesc->status |= ACT;
\r
275 /* Move onto the next buffer in the ring. */
\r
276 pxCurrentRxDesc = pxCurrentRxDesc->next;
\r
278 if( EDMAC.EDRRR.LONG == 0x00000000L )
\r
280 /* Restart Ethernet if it has stopped */
\r
281 EDMAC.EDRRR.LONG = 0x00000001L;
\r
285 return ulBytesReceived;
\r
287 /*-----------------------------------------------------------*/
\r
289 long lEMACWaitForLink( void )
\r
293 /* Set the link status. */
\r
294 switch( phy_set_autonegotiate() )
\r
296 /* Half duplex link */
\r
297 case PHY_LINK_100H:
\r
298 ETHERC.ECMR.BIT.DM = 0;
\r
299 ETHERC.ECMR.BIT.RTM = 1;
\r
304 ETHERC.ECMR.BIT.DM = 0;
\r
305 ETHERC.ECMR.BIT.RTM = 0;
\r
310 /* Full duplex link */
\r
311 case PHY_LINK_100F:
\r
312 ETHERC.ECMR.BIT.DM = 1;
\r
313 ETHERC.ECMR.BIT.RTM = 1;
\r
318 ETHERC.ECMR.BIT.DM = 1;
\r
319 ETHERC.ECMR.BIT.RTM = 0;
\r
328 if( lReturn == pdPASS )
\r
330 /* Enable receive and transmit. */
\r
331 ETHERC.ECMR.BIT.RE = 1;
\r
332 ETHERC.ECMR.BIT.TE = 1;
\r
334 /* Enable EDMAC receive */
\r
335 EDMAC.EDRRR.LONG = 0x1;
\r
340 /*-----------------------------------------------------------*/
\r
342 static void prvInitialiseDescriptors( void )
\r
344 ethfifo *pxDescriptor;
\r
347 for( x = 0; x < emacNUM_BUFFERS; x++ )
\r
349 /* Ensure none of the buffers are shown as in use at the start. */
\r
350 ucBufferInUse[ x ] = pdFALSE;
\r
353 /* Initialise the Rx descriptors. */
\r
354 for( x = 0; x < emacNUM_RX_DESCRIPTORS; x++ )
\r
356 pxDescriptor = &( xRxDescriptors[ x ] );
\r
357 pxDescriptor->buf_p = &( xEthernetBuffers.cBuffer[ x ][ 0 ] );
\r
359 pxDescriptor->bufsize = UIP_BUFSIZE;
\r
360 pxDescriptor->size = 0;
\r
361 pxDescriptor->status = ACT;
\r
362 pxDescriptor->next = &xRxDescriptors[ x + 1 ];
\r
364 /* Mark this buffer as in use. */
\r
365 ucBufferInUse[ x ] = pdTRUE;
\r
368 /* The last descriptor points back to the start. */
\r
369 pxDescriptor->status |= DL;
\r
370 pxDescriptor->next = &xRxDescriptors[ 0 ];
\r
372 /* Initialise the Tx descriptors. */
\r
373 for( x = 0; x < emacNUM_TX_BUFFERS; x++ )
\r
375 pxDescriptor = &( xTxDescriptors[ x ] );
\r
377 /* A buffer is not allocated to the Tx descriptor until a send is
\r
378 actually required. */
\r
379 pxDescriptor->buf_p = NULL;
\r
381 pxDescriptor->bufsize = UIP_BUFSIZE;
\r
382 pxDescriptor->size = 0;
\r
383 pxDescriptor->status = 0;
\r
384 pxDescriptor->next = &xTxDescriptors[ x + 1 ];
\r
387 /* The last descriptor points back to the start. */
\r
388 pxDescriptor->status |= DL;
\r
389 pxDescriptor->next = &( xTxDescriptors[ 0 ] );
\r
391 /* Use the first Rx descriptor to start with. */
\r
392 pxCurrentRxDesc = &( xRxDescriptors[ 0 ] );
\r
394 /*-----------------------------------------------------------*/
\r
396 static unsigned char *prvGetNextBuffer( void )
\r
399 unsigned char *pucReturn = NULL;
\r
400 unsigned long ulAttempts = 0;
\r
402 while( pucReturn == NULL )
\r
404 /* Look through the buffers to find one that is not in use by
\r
406 for( x = 0; x < emacNUM_BUFFERS; x++ )
\r
408 if( ucBufferInUse[ x ] == pdFALSE )
\r
410 ucBufferInUse[ x ] = pdTRUE;
\r
411 pucReturn = ( unsigned char * ) &( xEthernetBuffers.cBuffer[ x ][ 0 ] );
\r
416 /* Was a buffer found? */
\r
417 if( pucReturn == NULL )
\r
421 if( ulAttempts >= emacBUFFER_WAIT_ATTEMPTS )
\r
426 /* Wait then look again. */
\r
427 vTaskDelay( emacBUFFER_WAIT_DELAY_ms );
\r
433 /*-----------------------------------------------------------*/
\r
435 static void prvReturnBuffer( unsigned char *pucBuffer )
\r
439 /* Return a buffer to the pool of free buffers. */
\r
440 for( ul = 0; ul < emacNUM_BUFFERS; ul++ )
\r
442 if( &( xEthernetBuffers.cBuffer[ ul ][ 0 ] ) == ( void * ) pucBuffer )
\r
444 ucBufferInUse[ ul ] = pdFALSE;
\r
449 /*-----------------------------------------------------------*/
\r
451 static void prvResetEverything( void )
\r
453 /* Temporary code just to see if this gets called. This function has not
\r
454 been implemented. */
\r
455 portDISABLE_INTERRUPTS();
\r
458 /*-----------------------------------------------------------*/
\r
460 static unsigned long prvCheckRxFifoStatus( void )
\r
462 unsigned long ulReturn = 0;
\r
464 if( ( pxCurrentRxDesc->status & ACT ) != 0 )
\r
466 /* Current descriptor is still active. */
\r
468 else if( ( pxCurrentRxDesc->status & FE ) != 0 )
\r
470 /* Frame error. Clear the error. */
\r
471 pxCurrentRxDesc->status &= ~( FP1 | FP0 | FE );
\r
472 pxCurrentRxDesc->status &= ~( RMAF | RRF | RTLF | RTSF | PRE | CERF );
\r
473 pxCurrentRxDesc->status |= ACT;
\r
474 pxCurrentRxDesc = pxCurrentRxDesc->next;
\r
476 if( EDMAC.EDRRR.LONG == 0x00000000UL )
\r
478 /* Restart Ethernet if it has stopped. */
\r
479 EDMAC.EDRRR.LONG = 0x00000001UL;
\r
484 /* The descriptor contains a frame. Because of the size of the buffers
\r
485 the frame should always be complete. */
\r
486 if( ( pxCurrentRxDesc->status & FP0 ) == FP0 )
\r
488 ulReturn = pxCurrentRxDesc->size;
\r
492 /* Do not expect to get here. */
\r
493 prvResetEverything();
\r
499 /*-----------------------------------------------------------*/
\r
501 static void prvResetMAC( void )
\r
503 /* Ensure the EtherC and EDMAC are enabled. */
\r
504 SYSTEM.MSTPCRB.BIT.MSTPB15 = 0;
\r
505 vTaskDelay( 100 / portTICK_RATE_MS );
\r
507 EDMAC.EDMR.BIT.SWR = 1;
\r
509 /* Crude wait for reset to complete. */
\r
510 vTaskDelay( 500 / portTICK_RATE_MS );
\r
512 /*-----------------------------------------------------------*/
\r
514 static void prvConfigureEtherCAndEDMAC( void )
\r
516 /* Initialisation code taken from Renesas example project. */
\r
518 /* TODO: Check bit 5 */
\r
519 ETHERC.ECSR.LONG = 0x00000037; /* Clear all ETHERC statuS BFR, PSRTO, LCHNG, MPD, ICD */
\r
521 /* Set the EDMAC interrupt priority. */
\r
522 _IPR( _ETHER_EINT ) = configKERNEL_INTERRUPT_PRIORITY;
\r
524 /* TODO: Check bit 5 */
\r
525 /* Enable interrupts of interest only. */
\r
526 EDMAC.EESIPR.LONG = emacTX_END_INTERRUPT | emacRX_END_INTERRUPT;
\r
527 ETHERC.RFLR.LONG = 1518; /* Ether payload is 1500+ CRC */
\r
528 ETHERC.IPGR.LONG = 0x00000014; /* Intergap is 96-bit time */
\r
531 EDMAC.EESR.LONG = 0x47FF0F9F; /* Clear all ETHERC and EDMAC status bits */
\r
533 EDMAC.EDMR.BIT.DE = 1;
\r
535 EDMAC.RDLAR = ( void * ) pxCurrentRxDesc; /* Initialaize Rx Descriptor List Address */
\r
536 EDMAC.TDLAR = &( xTxDescriptors[ 0 ] ); /* Initialaize Tx Descriptor List Address */
\r
537 EDMAC.TRSCER.LONG = 0x00000000; /* Copy-back status is RFE & TFE only */
\r
538 EDMAC.TFTR.LONG = 0x00000000; /* Threshold of Tx_FIFO */
\r
539 EDMAC.FDR.LONG = 0x00000000; /* Transmit fifo & receive fifo is 256 bytes */
\r
540 EDMAC.RMCR.LONG = 0x00000003; /* Receive function is normal mode(continued) */
\r
541 ETHERC.ECMR.BIT.PRM = 0; /* Ensure promiscuous mode is off. */
\r
543 /* Enable the interrupt... */
\r
544 _IEN( _ETHER_EINT ) = 1;
\r
546 /*-----------------------------------------------------------*/
\r
548 #pragma interrupt ( vEMAC_ISR_Handler( vect = VECT_ETHER_EINT, enable ) )
\r
549 void vEMAC_ISR_Handler( void )
\r
551 unsigned long ul = EDMAC.EESR.LONG;
\r
552 long lHigherPriorityTaskWoken = pdFALSE;
\r
553 extern xQueueHandle xEMACEventQueue;
\r
554 const unsigned long ulRxEvent = uipETHERNET_RX_EVENT;
\r
556 /* Has a Tx end occurred? */
\r
557 if( ul & emacTX_END_INTERRUPT )
\r
559 /* Only return the buffer to the pool once both Txes have completed. */
\r
560 prvReturnBuffer( ( void * ) xTxDescriptors[ 0 ].buf_p );
\r
561 EDMAC.EESR.LONG = emacTX_END_INTERRUPT;
\r
564 /* Has an Rx end occurred? */
\r
565 if( ul & emacRX_END_INTERRUPT )
\r
567 /* Make sure the Ethernet task is not blocked waiting for a packet. */
\r
568 xQueueSendFromISR( xEMACEventQueue, &ulRxEvent, &lHigherPriorityTaskWoken );
\r
569 portYIELD_FROM_ISR( lHigherPriorityTaskWoken );
\r
570 EDMAC.EESR.LONG = emacRX_END_INTERRUPT;
\r