2 * FreeRTOS Kernel V10.1.0
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3 * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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28 /* Hardware specific includes. */
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29 #include "platform.h"
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30 #include "r_ether.h"
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33 /* FreeRTOS includes. */
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34 #include "FreeRTOS.h"
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39 #include "net/uip.h"
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41 /* The time to wait between attempts to obtain a free buffer. */
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42 #define emacBUFFER_WAIT_DELAY_ms ( 3 / portTICK_PERIOD_MS )
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44 /* The number of times emacBUFFER_WAIT_DELAY_ms should be waited before giving
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45 up on attempting to obtain a free buffer all together. */
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46 #define emacBUFFER_WAIT_ATTEMPTS ( 30 )
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48 /* The number of Rx descriptors. */
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49 #define emacNUM_RX_DESCRIPTORS 8
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51 /* The number of Tx descriptors. When using uIP there is not point in having
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53 #define emacNUM_TX_BUFFERS 2
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55 /* The total number of EMAC buffers to allocate. */
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56 #define emacNUM_BUFFERS ( emacNUM_RX_DESCRIPTORS + emacNUM_TX_BUFFERS )
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58 /* The time to wait for the Tx descriptor to become free. */
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59 #define emacTX_WAIT_DELAY_ms ( 10 / portTICK_PERIOD_MS )
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61 /* The total number of times to wait emacTX_WAIT_DELAY_ms for the Tx descriptor to
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63 #define emacTX_WAIT_ATTEMPTS ( 50 )
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65 /* Only Rx end and Tx end interrupts are used by this driver. */
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66 #define emacTX_END_INTERRUPT ( 1UL << 21UL )
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67 #define emacRX_END_INTERRUPT ( 1UL << 18UL )
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69 /*-----------------------------------------------------------*/
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71 /* The buffers and descriptors themselves. */
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72 #pragma section _RX_DESC
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73 volatile ethfifo xRxDescriptors[ emacNUM_RX_DESCRIPTORS ];
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74 #pragma section _TX_DESC
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75 volatile ethfifo xTxDescriptors[ emacNUM_TX_BUFFERS ];
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76 #pragma section _ETHERNET_BUFFERS
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79 unsigned long ulAlignmentVariable;
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80 char cBuffer[ emacNUM_BUFFERS ][ UIP_BUFSIZE ];
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87 /* Used to indicate which buffers are free and which are in use. If an index
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88 contains 0 then the corresponding buffer in xEthernetBuffers is free, otherwise
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89 the buffer is in use or about to be used. */
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90 static unsigned char ucBufferInUse[ emacNUM_BUFFERS ];
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92 /*-----------------------------------------------------------*/
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95 * Initialise both the Rx and Tx descriptors.
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97 static void prvInitialiseDescriptors( void );
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100 * Return a pointer to a free buffer within xEthernetBuffers.
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102 static unsigned char *prvGetNextBuffer( void );
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105 * Return a buffer to the list of free buffers.
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107 static void prvReturnBuffer( unsigned char *pucBuffer );
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110 * Examine the status of the next Rx FIFO to see if it contains new data.
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112 static unsigned long prvCheckRxFifoStatus( void );
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115 * Setup the microcontroller for communication with the PHY.
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117 static void prvResetMAC( void );
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120 * Configure the Ethernet interface peripherals.
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122 static void prvConfigureEtherCAndEDMAC( void );
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125 * Something has gone wrong with the descriptor usage. Reset all the buffers
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128 static void prvResetEverything( void );
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130 /*-----------------------------------------------------------*/
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132 /* Points to the Rx descriptor currently in use. */
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133 static ethfifo *pxCurrentRxDesc = NULL;
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135 /* The buffer used by the uIP stack to both receive and send. This points to
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136 one of the Ethernet buffers when its actually in use. */
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137 unsigned char *uip_buf = NULL;
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139 /*-----------------------------------------------------------*/
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141 void vInitEmac( void )
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143 /* Software reset. */
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146 /* Set the Rx and Tx descriptors into their initial state. */
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147 prvInitialiseDescriptors();
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149 /* Set the MAC address into the ETHERC */
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150 ETHERC.MAHR = ( ( unsigned long ) configMAC_ADDR0 << 24UL ) |
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151 ( ( unsigned long ) configMAC_ADDR1 << 16UL ) |
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152 ( ( unsigned long ) configMAC_ADDR2 << 8UL ) |
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153 ( unsigned long ) configMAC_ADDR3;
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155 ETHERC.MALR.BIT.MA = ( ( unsigned long ) configMAC_ADDR4 << 8UL ) |
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156 ( unsigned long ) configMAC_ADDR5;
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158 /* Perform rest of interface hardware configuration. */
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159 prvConfigureEtherCAndEDMAC();
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161 /* Nothing received yet, so uip_buf points nowhere. */
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164 /* Initialize the PHY */
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167 /*-----------------------------------------------------------*/
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169 void vEMACWrite( void )
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173 /* Wait until the second transmission of the last packet has completed. */
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174 for( x = 0; x < emacTX_WAIT_ATTEMPTS; x++ )
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176 if( ( xTxDescriptors[ 1 ].status & ACT ) != 0 )
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178 /* Descriptor is still active. */
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179 vTaskDelay( emacTX_WAIT_DELAY_ms );
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187 /* Is the descriptor free after waiting for it? */
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188 if( ( xTxDescriptors[ 1 ].status & ACT ) != 0 )
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190 /* Something has gone wrong. */
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191 prvResetEverything();
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194 /* Setup both descriptors to transmit the frame. */
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195 xTxDescriptors[ 0 ].buf_p = ( char * ) uip_buf;
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196 xTxDescriptors[ 0 ].bufsize = uip_len;
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197 xTxDescriptors[ 1 ].buf_p = ( char * ) uip_buf;
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198 xTxDescriptors[ 1 ].bufsize = uip_len;
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200 /* uip_buf is being sent by the Tx descriptor. Allocate a new buffer
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201 for use by the stack. */
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202 uip_buf = prvGetNextBuffer();
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204 /* Clear previous settings and go. */
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205 xTxDescriptors[0].status &= ~( FP1 | FP0 );
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206 xTxDescriptors[0].status |= ( FP1 | FP0 | ACT );
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207 xTxDescriptors[1].status &= ~( FP1 | FP0 );
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208 xTxDescriptors[1].status |= ( FP1 | FP0 | ACT );
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210 EDMAC.EDTRR.LONG = 0x00000001;
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212 /*-----------------------------------------------------------*/
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214 unsigned long ulEMACRead( void )
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216 unsigned long ulBytesReceived;
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218 ulBytesReceived = prvCheckRxFifoStatus();
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220 if( ulBytesReceived > 0 )
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222 /* Mark the pxDescriptor buffer as free as uip_buf is going to be set to
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223 the buffer that contains the received data. */
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224 prvReturnBuffer( uip_buf );
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226 /* Point uip_buf to the data about ot be processed. */
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227 uip_buf = ( void * ) pxCurrentRxDesc->buf_p;
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229 /* Allocate a new buffer to the descriptor, as uip_buf is now using it's
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231 pxCurrentRxDesc->buf_p = prvGetNextBuffer();
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233 /* Prepare the descriptor to go again. */
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234 pxCurrentRxDesc->status &= ~( FP1 | FP0 );
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235 pxCurrentRxDesc->status |= ACT;
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237 /* Move onto the next buffer in the ring. */
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238 pxCurrentRxDesc = pxCurrentRxDesc->next;
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240 if( EDMAC.EDRRR.LONG == 0x00000000L )
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242 /* Restart Ethernet if it has stopped */
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243 EDMAC.EDRRR.LONG = 0x00000001L;
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247 return ulBytesReceived;
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249 /*-----------------------------------------------------------*/
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251 long lEMACWaitForLink( void )
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255 /* Set the link status. */
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256 switch( phy_set_autonegotiate() )
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258 /* Half duplex link */
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259 case PHY_LINK_100H:
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260 ETHERC.ECMR.BIT.DM = 0;
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261 ETHERC.ECMR.BIT.RTM = 1;
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266 ETHERC.ECMR.BIT.DM = 0;
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267 ETHERC.ECMR.BIT.RTM = 0;
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272 /* Full duplex link */
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273 case PHY_LINK_100F:
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274 ETHERC.ECMR.BIT.DM = 1;
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275 ETHERC.ECMR.BIT.RTM = 1;
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280 ETHERC.ECMR.BIT.DM = 1;
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281 ETHERC.ECMR.BIT.RTM = 0;
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290 if( lReturn == pdPASS )
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292 /* Enable receive and transmit. */
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293 ETHERC.ECMR.BIT.RE = 1;
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294 ETHERC.ECMR.BIT.TE = 1;
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296 /* Enable EDMAC receive */
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297 EDMAC.EDRRR.LONG = 0x1;
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302 /*-----------------------------------------------------------*/
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304 static void prvInitialiseDescriptors( void )
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306 ethfifo *pxDescriptor;
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309 for( x = 0; x < emacNUM_BUFFERS; x++ )
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311 /* Ensure none of the buffers are shown as in use at the start. */
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312 ucBufferInUse[ x ] = pdFALSE;
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315 /* Initialise the Rx descriptors. */
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316 for( x = 0; x < emacNUM_RX_DESCRIPTORS; x++ )
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318 pxDescriptor = &( xRxDescriptors[ x ] );
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319 pxDescriptor->buf_p = &( xEthernetBuffers.cBuffer[ x ][ 0 ] );
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321 pxDescriptor->bufsize = UIP_BUFSIZE;
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322 pxDescriptor->size = 0;
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323 pxDescriptor->status = ACT;
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324 pxDescriptor->next = &xRxDescriptors[ x + 1 ];
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326 /* Mark this buffer as in use. */
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327 ucBufferInUse[ x ] = pdTRUE;
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330 /* The last descriptor points back to the start. */
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331 pxDescriptor->status |= DL;
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332 pxDescriptor->next = &xRxDescriptors[ 0 ];
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334 /* Initialise the Tx descriptors. */
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335 for( x = 0; x < emacNUM_TX_BUFFERS; x++ )
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337 pxDescriptor = &( xTxDescriptors[ x ] );
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339 /* A buffer is not allocated to the Tx descriptor until a send is
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340 actually required. */
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341 pxDescriptor->buf_p = NULL;
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343 pxDescriptor->bufsize = UIP_BUFSIZE;
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344 pxDescriptor->size = 0;
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345 pxDescriptor->status = 0;
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346 pxDescriptor->next = &xTxDescriptors[ x + 1 ];
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349 /* The last descriptor points back to the start. */
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350 pxDescriptor->status |= DL;
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351 pxDescriptor->next = &( xTxDescriptors[ 0 ] );
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353 /* Use the first Rx descriptor to start with. */
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354 pxCurrentRxDesc = &( xRxDescriptors[ 0 ] );
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356 /*-----------------------------------------------------------*/
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358 static unsigned char *prvGetNextBuffer( void )
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361 unsigned char *pucReturn = NULL;
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362 unsigned long ulAttempts = 0;
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364 while( pucReturn == NULL )
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366 /* Look through the buffers to find one that is not in use by
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368 for( x = 0; x < emacNUM_BUFFERS; x++ )
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370 if( ucBufferInUse[ x ] == pdFALSE )
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372 ucBufferInUse[ x ] = pdTRUE;
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373 pucReturn = ( unsigned char * ) &( xEthernetBuffers.cBuffer[ x ][ 0 ] );
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378 /* Was a buffer found? */
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379 if( pucReturn == NULL )
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383 if( ulAttempts >= emacBUFFER_WAIT_ATTEMPTS )
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388 /* Wait then look again. */
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389 vTaskDelay( emacBUFFER_WAIT_DELAY_ms );
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395 /*-----------------------------------------------------------*/
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397 static void prvReturnBuffer( unsigned char *pucBuffer )
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401 /* Return a buffer to the pool of free buffers. */
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402 for( ul = 0; ul < emacNUM_BUFFERS; ul++ )
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404 if( &( xEthernetBuffers.cBuffer[ ul ][ 0 ] ) == ( void * ) pucBuffer )
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406 ucBufferInUse[ ul ] = pdFALSE;
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411 /*-----------------------------------------------------------*/
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413 static void prvResetEverything( void )
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415 /* Temporary code just to see if this gets called. This function has not
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416 been implemented. */
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417 portDISABLE_INTERRUPTS();
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420 /*-----------------------------------------------------------*/
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422 static unsigned long prvCheckRxFifoStatus( void )
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424 unsigned long ulReturn = 0;
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426 if( ( pxCurrentRxDesc->status & ACT ) != 0 )
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428 /* Current descriptor is still active. */
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430 else if( ( pxCurrentRxDesc->status & FE ) != 0 )
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432 /* Frame error. Clear the error. */
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433 pxCurrentRxDesc->status &= ~( FP1 | FP0 | FE );
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434 pxCurrentRxDesc->status &= ~( RMAF | RRF | RTLF | RTSF | PRE | CERF );
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435 pxCurrentRxDesc->status |= ACT;
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436 pxCurrentRxDesc = pxCurrentRxDesc->next;
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438 if( EDMAC.EDRRR.LONG == 0x00000000UL )
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440 /* Restart Ethernet if it has stopped. */
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441 EDMAC.EDRRR.LONG = 0x00000001UL;
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446 /* The descriptor contains a frame. Because of the size of the buffers
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447 the frame should always be complete. */
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448 if( ( pxCurrentRxDesc->status & FP0 ) == FP0 )
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450 ulReturn = pxCurrentRxDesc->size;
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454 /* Do not expect to get here. */
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455 prvResetEverything();
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461 /*-----------------------------------------------------------*/
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463 static void prvResetMAC( void )
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465 /* Ensure the EtherC and EDMAC are enabled. */
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466 SYSTEM.MSTPCRB.BIT.MSTPB15 = 0;
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467 vTaskDelay( 100 / portTICK_PERIOD_MS );
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469 EDMAC.EDMR.BIT.SWR = 1;
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471 /* Crude wait for reset to complete. */
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472 vTaskDelay( 500 / portTICK_PERIOD_MS );
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474 /*-----------------------------------------------------------*/
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476 static void prvConfigureEtherCAndEDMAC( void )
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478 /* Initialisation code taken from Renesas example project. */
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480 /* TODO: Check bit 5 */
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481 ETHERC.ECSR.LONG = 0x00000037; /* Clear all ETHERC statuS BFR, PSRTO, LCHNG, MPD, ICD */
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483 /* Set the EDMAC interrupt priority. */
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484 _IPR( _ETHER_EINT ) = configKERNEL_INTERRUPT_PRIORITY;
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486 /* TODO: Check bit 5 */
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487 /* Enable interrupts of interest only. */
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488 EDMAC.EESIPR.LONG = emacTX_END_INTERRUPT | emacRX_END_INTERRUPT;
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489 ETHERC.RFLR.LONG = 1518; /* Ether payload is 1500+ CRC */
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490 ETHERC.IPGR.LONG = 0x00000014; /* Intergap is 96-bit time */
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493 EDMAC.EESR.LONG = 0x47FF0F9F; /* Clear all ETHERC and EDMAC status bits */
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495 EDMAC.EDMR.BIT.DE = 1;
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497 EDMAC.RDLAR = ( void * ) pxCurrentRxDesc; /* Initialaize Rx Descriptor List Address */
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498 EDMAC.TDLAR = &( xTxDescriptors[ 0 ] ); /* Initialaize Tx Descriptor List Address */
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499 EDMAC.TRSCER.LONG = 0x00000000; /* Copy-back status is RFE & TFE only */
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500 EDMAC.TFTR.LONG = 0x00000000; /* Threshold of Tx_FIFO */
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501 EDMAC.FDR.LONG = 0x00000000; /* Transmit fifo & receive fifo is 256 bytes */
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502 EDMAC.RMCR.LONG = 0x00000003; /* Receive function is normal mode(continued) */
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503 ETHERC.ECMR.BIT.PRM = 0; /* Ensure promiscuous mode is off. */
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505 /* Enable the interrupt... */
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506 _IEN( _ETHER_EINT ) = 1;
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508 /*-----------------------------------------------------------*/
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510 #pragma interrupt ( vEMAC_ISR_Handler( vect = VECT_ETHER_EINT, enable ) )
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511 void vEMAC_ISR_Handler( void )
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513 unsigned long ul = EDMAC.EESR.LONG;
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514 long lHigherPriorityTaskWoken = pdFALSE;
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515 extern QueueHandle_t xEMACEventQueue;
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516 const unsigned long ulRxEvent = uipETHERNET_RX_EVENT;
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518 /* Has a Tx end occurred? */
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519 if( ul & emacTX_END_INTERRUPT )
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521 /* Only return the buffer to the pool once both Txes have completed. */
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522 prvReturnBuffer( ( void * ) xTxDescriptors[ 0 ].buf_p );
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523 EDMAC.EESR.LONG = emacTX_END_INTERRUPT;
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526 /* Has an Rx end occurred? */
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527 if( ul & emacRX_END_INTERRUPT )
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529 /* Make sure the Ethernet task is not blocked waiting for a packet. */
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530 xQueueSendFromISR( xEMACEventQueue, &ulRxEvent, &lHigherPriorityTaskWoken );
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531 portYIELD_FROM_ISR( lHigherPriorityTaskWoken );
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532 EDMAC.EESR.LONG = emacRX_END_INTERRUPT;
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