2 FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.
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4 FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
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5 http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 ***************************************************************************
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9 * FreeRTOS tutorial books are available in pdf and paperback. *
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10 * Complete, revised, and edited pdf reference manuals are also *
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13 * Purchasing FreeRTOS documentation will not only help you, by *
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14 * ensuring you get running as quickly as possible and with an *
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15 * in-depth knowledge of how to use FreeRTOS, it will also help *
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16 * the FreeRTOS project to continue with its mission of providing *
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17 * professional grade, cross platform, de facto standard solutions *
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18 * for microcontrollers - completely free of charge! *
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20 * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
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22 * Thank you for using FreeRTOS, and thank you for your support! *
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24 ***************************************************************************
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27 This file is part of the FreeRTOS distribution.
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29 FreeRTOS is free software; you can redistribute it and/or modify it under
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30 the terms of the GNU General Public License (version 2) as published by the
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31 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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33 >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
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34 distribute a combined work that includes FreeRTOS without being obliged to
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35 provide the source code for proprietary components outside of the FreeRTOS
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38 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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39 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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40 FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
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41 details. You should have received a copy of the GNU General Public License
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42 and the FreeRTOS license exception along with FreeRTOS; if not it can be
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43 viewed here: http://www.freertos.org/a00114.html and also obtained by
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44 writing to Real Time Engineers Ltd., contact details for whom are available
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45 on the FreeRTOS WEB site.
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49 ***************************************************************************
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51 * Having a problem? Start by reading the FAQ "My application does *
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52 * not run, what could be wrong?" *
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54 * http://www.FreeRTOS.org/FAQHelp.html *
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56 ***************************************************************************
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59 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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60 license and Real Time Engineers Ltd. contact details.
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62 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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63 including FreeRTOS+Trace - an indispensable productivity tool, and our new
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64 fully thread aware and reentrant UDP/IP stack.
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66 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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67 Integrity Systems, who sell the code with commercial support,
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68 indemnification and middleware, under the OpenRTOS brand.
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70 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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71 engineered and independently SIL3 certified version for use in safety and
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72 mission critical applications that require provable dependability.
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75 /* Hardware specific includes. */
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76 #include "iodefine.h"
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77 #include "typedefine.h"
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78 #include "hwEthernet.h"
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79 #include "hwEthernetPhy.h"
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81 /* FreeRTOS includes. */
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82 #include "FreeRTOS.h"
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87 #include "net/uip.h"
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89 /* The time to wait between attempts to obtain a free buffer. */
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90 #define emacBUFFER_WAIT_DELAY_ms ( 3 / portTICK_RATE_MS )
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92 /* The number of times emacBUFFER_WAIT_DELAY_ms should be waited before giving
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93 up on attempting to obtain a free buffer all together. */
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94 #define emacBUFFER_WAIT_ATTEMPTS ( 30 )
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96 /* The number of Rx descriptors. */
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97 #define emacNUM_RX_DESCRIPTORS 3
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99 /* The number of Tx descriptors. When using uIP there is not point in having
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101 #define emacNUM_TX_BUFFERS 2
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103 /* The total number of EMAC buffers to allocate. */
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104 #define emacNUM_BUFFERS ( emacNUM_RX_DESCRIPTORS + emacNUM_TX_BUFFERS )
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106 /* The time to wait for the Tx descriptor to become free. */
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107 #define emacTX_WAIT_DELAY_ms ( 10 / portTICK_RATE_MS )
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109 /* The total number of times to wait emacTX_WAIT_DELAY_ms for the Tx descriptor to
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111 #define emacTX_WAIT_ATTEMPTS ( 5 )
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113 /* Only Rx end and Tx end interrupts are used by this driver. */
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114 #define emacTX_END_INTERRUPT ( 1UL << 21UL )
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115 #define emacRX_END_INTERRUPT ( 1UL << 18UL )
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117 /*-----------------------------------------------------------*/
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119 /* The buffers and descriptors themselves. */
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120 #pragma section RX_DESCR
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121 ethfifo xRxDescriptors[ emacNUM_RX_DESCRIPTORS ];
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122 #pragma section TX_DESCR
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123 ethfifo xTxDescriptors[ emacNUM_TX_BUFFERS ];
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124 #pragma section _ETHERNET_BUFFERS
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125 char xEthernetBuffers[ emacNUM_BUFFERS ][ UIP_BUFSIZE ];
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128 /* Used to indicate which buffers are free and which are in use. If an index
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129 contains 0 then the corresponding buffer in xEthernetBuffers is free, otherwise
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130 the buffer is in use or about to be used. */
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131 static unsigned char ucBufferInUse[ emacNUM_BUFFERS ];
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133 /*-----------------------------------------------------------*/
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136 * Initialise both the Rx and Tx descriptors.
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138 static void prvInitialiseDescriptors( void );
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141 * Return a pointer to a free buffer within xEthernetBuffers.
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143 static unsigned char *prvGetNextBuffer( void );
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146 * Return a buffer to the list of free buffers.
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148 static void prvReturnBuffer( unsigned char *pucBuffer );
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151 * Examine the status of the next Rx FIFO to see if it contains new data.
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153 static unsigned long prvCheckRxFifoStatus( void );
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156 * Setup the microcontroller for communication with the PHY.
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158 static void prvSetupPortPinsAndReset( void );
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161 * Configure the Ethernet interface peripherals.
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163 static void prvConfigureEtherCAndEDMAC( void );
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166 * Something has gone wrong with the descriptor usage. Reset all the buffers
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169 static void prvResetEverything( void );
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171 /*-----------------------------------------------------------*/
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173 /* Points to the Rx descriptor currently in use. */
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174 static ethfifo *xCurrentRxDesc = NULL;
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176 /* The buffer used by the uIP stack to both receive and send. This points to
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177 one of the Ethernet buffers when its actually in use. */
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178 unsigned char *uip_buf = NULL;
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180 /*-----------------------------------------------------------*/
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182 void vInitEmac( void )
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184 /* Setup the SH hardware for MII communications. */
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185 prvSetupPortPinsAndReset();
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187 /* Set the Rx and Tx descriptors into their initial state. */
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188 prvInitialiseDescriptors();
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190 /* Set the MAC address into the ETHERC */
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191 EtherC.MAHR = ( ( unsigned long ) configMAC_ADDR0 << 24UL ) |
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192 ( ( unsigned long ) configMAC_ADDR1 << 16UL ) |
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193 ( ( unsigned long ) configMAC_ADDR2 << 8UL ) |
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194 ( unsigned long ) configMAC_ADDR3;
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196 EtherC.MALR.BIT.MA = ( ( unsigned long ) configMAC_ADDR4 << 8UL ) |
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197 ( unsigned long ) configMAC_ADDR5;
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199 /* Perform rest of interface hardware configuration. */
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200 prvConfigureEtherCAndEDMAC();
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202 /* Nothing received yet, so uip_buf points nowhere. */
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205 /* Initialize the PHY */
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208 /*-----------------------------------------------------------*/
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210 void vEMACWrite( void )
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214 /* Wait until the second transmission of the last packet has completed. */
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215 for( x = 0; x < emacTX_WAIT_ATTEMPTS; x++ )
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217 if( ( xTxDescriptors[ 1 ].status & ACT ) != 0 )
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219 /* Descriptor is still active. */
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220 vTaskDelay( emacTX_WAIT_DELAY_ms );
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228 /* Is the descriptor free after waiting for it? */
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229 if( ( xTxDescriptors[ 1 ].status & ACT ) != 0 )
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231 /* Something has gone wrong. */
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232 prvResetEverything();
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235 /* Setup both descriptors to transmit the frame. */
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236 xTxDescriptors[ 0 ].buf_p = ( char * ) uip_buf;
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237 xTxDescriptors[ 0 ].bufsize = uip_len;
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238 xTxDescriptors[ 1 ].buf_p = ( char * ) uip_buf;
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239 xTxDescriptors[ 1 ].bufsize = uip_len;
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241 /* uip_buf is being sent by the Tx descriptor. Allocate a new buffer
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242 for use by the stack. */
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243 uip_buf = prvGetNextBuffer();
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245 /* Clear previous settings and go. */
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246 xTxDescriptors[0].status &= ~( FP1 | FP0 );
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247 xTxDescriptors[0].status |= ( FP1 | FP0 | ACT );
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248 xTxDescriptors[1].status &= ~( FP1 | FP0 );
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249 xTxDescriptors[1].status |= ( FP1 | FP0 | ACT );
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251 EDMAC.EDTRR.LONG = 0x00000001;
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253 /*-----------------------------------------------------------*/
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255 unsigned long ulEMACRead( void )
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257 unsigned long ulBytesReceived;
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259 ulBytesReceived = prvCheckRxFifoStatus();
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261 if( ulBytesReceived > 0 )
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263 xCurrentRxDesc->status &= ~( FP1 | FP0 );
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264 xCurrentRxDesc->status |= ACT;
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266 if( EDMAC.EDRRR.LONG == 0x00000000L )
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268 /* Restart Ethernet if it has stopped */
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269 EDMAC.EDRRR.LONG = 0x00000001L;
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272 /* Mark the pxDescriptor buffer as free as uip_buf is going to be set to
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273 the buffer that contains the received data. */
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274 prvReturnBuffer( uip_buf );
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276 uip_buf = ( void * ) xCurrentRxDesc->buf_p;
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278 /* Move onto the next buffer in the ring. */
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279 xCurrentRxDesc = xCurrentRxDesc->next;
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282 return ulBytesReceived;
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284 /*-----------------------------------------------------------*/
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286 long lEMACWaitForLink( void )
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290 /* Set the link status. */
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291 switch( phyStatus() )
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293 /* Half duplex link */
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294 case PHY_LINK_100H:
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296 EtherC.ECMR.BIT.DM = 0;
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300 /* Full duplex link */
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301 case PHY_LINK_100F:
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303 EtherC.ECMR.BIT.DM = 1;
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312 if( lReturn == pdPASS )
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314 /* Enable receive and transmit. */
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315 EtherC.ECMR.BIT.RE = 1;
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316 EtherC.ECMR.BIT.TE = 1;
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318 /* Enable EDMAC receive */
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319 EDMAC.EDRRR.LONG = 0x1;
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324 /*-----------------------------------------------------------*/
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326 static void prvInitialiseDescriptors( void )
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328 ethfifo *pxDescriptor;
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331 for( x = 0; x < emacNUM_BUFFERS; x++ )
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333 /* Ensure none of the buffers are shown as in use at the start. */
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334 ucBufferInUse[ x ] = pdFALSE;
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337 /* Initialise the Rx descriptors. */
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338 for( x = 0; x < emacNUM_RX_DESCRIPTORS; x++ )
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340 pxDescriptor = &( xRxDescriptors[ x ] );
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341 pxDescriptor->buf_p = &( xEthernetBuffers[ x ][ 0 ] );
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343 pxDescriptor->bufsize = UIP_BUFSIZE;
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344 pxDescriptor->size = 0;
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345 pxDescriptor->status = ACT;
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346 pxDescriptor->next = &xRxDescriptors[ x + 1 ];
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348 /* Mark this buffer as in use. */
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349 ucBufferInUse[ x ] = pdTRUE;
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352 /* The last descriptor points back to the start. */
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353 pxDescriptor->status |= DL;
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354 pxDescriptor->next = &xRxDescriptors[ 0 ];
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356 /* Initialise the Tx descriptors. */
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357 for( x = 0; x < emacNUM_TX_BUFFERS; x++ )
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359 pxDescriptor = &( xTxDescriptors[ x ] );
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361 /* A buffer is not allocated to the Tx descriptor until a send is
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362 actually required. */
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363 pxDescriptor->buf_p = NULL;
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365 pxDescriptor->bufsize = UIP_BUFSIZE;
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366 pxDescriptor->size = 0;
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367 pxDescriptor->status = 0;
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368 pxDescriptor->next = &xTxDescriptors[ x + 1 ];
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371 /* The last descriptor points back to the start. */
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372 pxDescriptor->status |= DL;
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373 pxDescriptor->next = &( xTxDescriptors[ 0 ] );
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375 /* Use the first Rx descriptor to start with. */
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376 xCurrentRxDesc = &( xRxDescriptors[ 0 ] );
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378 /*-----------------------------------------------------------*/
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380 static unsigned char *prvGetNextBuffer( void )
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383 unsigned char *pucReturn = NULL;
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384 unsigned long ulAttempts = 0;
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386 while( pucReturn == NULL )
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388 /* Look through the buffers to find one that is not in use by
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390 for( x = 0; x < emacNUM_BUFFERS; x++ )
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392 if( ucBufferInUse[ x ] == pdFALSE )
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394 ucBufferInUse[ x ] = pdTRUE;
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395 pucReturn = ( unsigned char * ) &( xEthernetBuffers[ x ][ 0 ] );
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400 /* Was a buffer found? */
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401 if( pucReturn == NULL )
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405 if( ulAttempts >= emacBUFFER_WAIT_ATTEMPTS )
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410 /* Wait then look again. */
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411 vTaskDelay( emacBUFFER_WAIT_DELAY_ms );
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417 /*-----------------------------------------------------------*/
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419 static void prvReturnBuffer( unsigned char *pucBuffer )
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423 /* Return a buffer to the pool of free buffers. */
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424 for( ul = 0; ul < emacNUM_BUFFERS; ul++ )
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426 if( &( xEthernetBuffers[ ul ][ 0 ] ) == ( void * ) pucBuffer )
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428 ucBufferInUse[ ul ] = pdFALSE;
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433 /*-----------------------------------------------------------*/
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435 static void prvResetEverything( void )
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437 /* Temporary code just to see if this gets called. This function has not
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438 been implemented. */
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439 portDISABLE_INTERRUPTS();
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442 /*-----------------------------------------------------------*/
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444 static unsigned long prvCheckRxFifoStatus( void )
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446 unsigned long ulReturn = 0;
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448 if( ( xCurrentRxDesc->status & ACT ) != 0 )
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450 /* Current descriptor is still active. */
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452 else if( ( xCurrentRxDesc->status & FE ) != 0 )
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454 /* Frame error. Clear the error. */
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455 xCurrentRxDesc->status &= ~( FP1 | FP0 | FE );
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456 xCurrentRxDesc->status &= ~( RMAF | RRF | RTLF | RTSF | PRE | CERF );
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457 xCurrentRxDesc->status |= ACT;
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458 xCurrentRxDesc = xCurrentRxDesc->next;
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460 if( EDMAC.EDRRR.LONG == 0x00000000UL )
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462 /* Restart Ethernet if it has stopped. */
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463 EDMAC.EDRRR.LONG = 0x00000001UL;
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468 /* The descriptor contains a frame. Because of the size of the buffers
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469 the frame should always be complete. */
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470 if( (xCurrentRxDesc->status & FP0) == FP0 )
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472 ulReturn = xCurrentRxDesc->size;
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476 /* Do not expect to get here. */
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477 prvResetEverything();
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483 /*-----------------------------------------------------------*/
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485 static void prvSetupPortPinsAndReset( void )
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487 /* Initialisation code taken from Renesas example project. */
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489 PFC.PACRL4.BIT.PA12MD = 0x7; /* Set TX_CLK input (EtherC) */
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490 PFC.PACRL3.BIT.PA11MD = 0x7; /* Set TX_EN output (EtherC) */
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491 PFC.PACRL3.BIT.PA10MD = 0x7; /* Set MII_TXD0 output (EtherC) */
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492 PFC.PACRL3.BIT.PA9MD = 0x7; /* Set MII_TXD1 output (EtherC) */
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493 PFC.PACRL3.BIT.PA8MD = 0x7; /* Set MII_TXD2 output (EtherC) */
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494 PFC.PACRL2.BIT.PA7MD = 0x7; /* Set MII_TXD3 output (EtherC) */
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495 PFC.PACRL2.BIT.PA6MD = 0x7; /* Set TX_ER output (EtherC) */
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496 PFC.PDCRH4.BIT.PD31MD = 0x7; /* Set RX_DV input (EtherC) */
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497 PFC.PDCRH4.BIT.PD30MD = 0x7; /* Set RX_ER input (EtherC) */
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498 PFC.PDCRH4.BIT.PD29MD = 0x7; /* Set MII_RXD3 input (EtherC) */
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499 PFC.PDCRH4.BIT.PD28MD = 0x7; /* Set MII_RXD2 input (EtherC) */
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500 PFC.PDCRH3.BIT.PD27MD = 0x7; /* Set MII_RXD1 input (EtherC) */
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501 PFC.PDCRH3.BIT.PD26MD = 0x7; /* Set MII_RXD0 input (EtherC) */
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502 PFC.PDCRH3.BIT.PD25MD = 0x7; /* Set RX_CLK input (EtherC) */
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503 PFC.PDCRH3.BIT.PD24MD = 0x7; /* Set CRS input (EtherC) */
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504 PFC.PDCRH2.BIT.PD23MD = 0x7; /* Set COL input (EtherC) */
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505 PFC.PDCRH2.BIT.PD22MD = 0x7; /* Set WOL output (EtherC) */
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506 PFC.PDCRH2.BIT.PD21MD = 0x7; /* Set EXOUT output (EtherC) */
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507 PFC.PDCRH2.BIT.PD20MD = 0x7; /* Set MDC output (EtherC) */
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508 PFC.PDCRH1.BIT.PD19MD = 0x7; /* Set LINKSTA input (EtherC) */
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509 PFC.PDCRH1.BIT.PD18MD = 0x7; /* Set MDIO input/output (EtherC) */
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511 STB.CR4.BIT._ETHER = 0x0;
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512 EDMAC.EDMR.BIT.SWR = 1;
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514 /* Crude wait for reset to complete. */
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515 vTaskDelay( 500 / portTICK_RATE_MS );
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517 /*-----------------------------------------------------------*/
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519 static void prvConfigureEtherCAndEDMAC( void )
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521 /* Initialisation code taken from Renesas example project. */
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523 /* TODO: Check bit 5 */
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524 EtherC.ECSR.LONG = 0x00000037; /* Clear all EtherC statuS BFR, PSRTO, LCHNG, MPD, ICD */
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526 /* TODO: Check bit 5 */
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527 EtherC.ECSIPR.LONG = 0x00000020; /* Disable EtherC status change interrupt */
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528 EtherC.RFLR.LONG = 1518; /* Ether payload is 1500+ CRC */
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529 EtherC.IPGR.LONG = 0x00000014; /* Intergap is 96-bit time */
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532 EDMAC.EESR.LONG = 0x47FF0F9F; /* Clear all EtherC and EDMAC status bits */
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533 EDMAC.RDLAR = ( void * ) xCurrentRxDesc; /* Initialaize Rx Descriptor List Address */
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534 EDMAC.TDLAR = &( xTxDescriptors[ 0 ] ); /* Initialaize Tx Descriptor List Address */
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535 EDMAC.TRSCER.LONG = 0x00000000; /* Copy-back status is RFE & TFE only */
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536 EDMAC.TFTR.LONG = 0x00000000; /* Threshold of Tx_FIFO */
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537 EDMAC.FDR.LONG = 0x00000000; /* Transmit fifo & receive fifo is 256 bytes */
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538 EDMAC.RMCR.LONG = 0x00000003; /* Receive function is normal mode(continued) */
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540 /* Set the EDMAC interrupt priority - the interrupt priority must be
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541 configKERNEL_INTERRUPT_PRIORITY no matter which peripheral is used to
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542 generate the tick interrupt. */
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543 INTC.IPR19.BIT._EDMAC = portKERNEL_INTERRUPT_PRIORITY;
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544 EDMAC.EESIPR.LONG = emacTX_END_INTERRUPT | emacRX_END_INTERRUPT; /* Enable Rx and Tx end interrupts. */
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546 /* Clear the interrupt flag. */
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547 CMT0.CMCSR.BIT.CMF = 0;
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549 /*-----------------------------------------------------------*/
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551 void vEMAC_ISR_Handler( void )
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553 unsigned long ul = EDMAC.EESR.LONG;
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554 long lHigherPriorityTaskWoken = pdFALSE;
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555 extern xSemaphoreHandle xEMACSemaphore;
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556 static long ulTxEndInts = 0;
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558 /* Has a Tx end occurred? */
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559 if( ul & emacTX_END_INTERRUPT )
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562 if( ulTxEndInts >= 2 )
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564 /* Only return the buffer to the pool once both Txes have completed. */
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565 prvReturnBuffer( ( void * ) xTxDescriptors[ 0 ].buf_p );
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568 EDMAC.EESR.LONG = emacTX_END_INTERRUPT;
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571 /* Has an Rx end occurred? */
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572 if( ul & emacRX_END_INTERRUPT )
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574 /* Make sure the Ethernet task is not blocked waiting for a packet. */
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575 xSemaphoreGiveFromISR( xEMACSemaphore, &lHigherPriorityTaskWoken );
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576 portYIELD_FROM_ISR( lHigherPriorityTaskWoken );
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577 EDMAC.EESR.LONG = emacRX_END_INTERRUPT;
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