2 FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
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5 ***************************************************************************
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7 * FreeRTOS tutorial books are available in pdf and paperback. *
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8 * Complete, revised, and edited pdf reference manuals are also *
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11 * Purchasing FreeRTOS documentation will not only help you, by *
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12 * ensuring you get running as quickly as possible and with an *
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13 * in-depth knowledge of how to use FreeRTOS, it will also help *
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14 * the FreeRTOS project to continue with its mission of providing *
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15 * professional grade, cross platform, de facto standard solutions *
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16 * for microcontrollers - completely free of charge! *
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18 * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
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20 * Thank you for using FreeRTOS, and thank you for your support! *
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22 ***************************************************************************
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25 This file is part of the FreeRTOS distribution.
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27 FreeRTOS is free software; you can redistribute it and/or modify it under
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28 the terms of the GNU General Public License (version 2) as published by the
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29 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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30 >>>NOTE<<< The modification to the GPL is included to allow you to
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31 distribute a combined work that includes FreeRTOS without being obliged to
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32 provide the source code for proprietary components outside of the FreeRTOS
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33 kernel. FreeRTOS is distributed in the hope that it will be useful, but
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34 WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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35 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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36 more details. You should have received a copy of the GNU General Public
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37 License and the FreeRTOS license exception along with FreeRTOS; if not it
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38 can be viewed here: http://www.freertos.org/a00114.html and also obtained
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39 by writing to Richard Barry, contact details for whom are available on the
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44 ***************************************************************************
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46 * Having a problem? Start by reading the FAQ "My application does *
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47 * not run, what could be wrong? *
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49 * http://www.FreeRTOS.org/FAQHelp.html *
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51 ***************************************************************************
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54 http://www.FreeRTOS.org - Documentation, training, latest information,
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55 license and contact details.
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57 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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58 including FreeRTOS+Trace - an indispensable productivity tool.
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60 Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
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61 the code with commercial support, indemnification, and middleware, under
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62 the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
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63 provide a safety engineered and independently SIL3 certified version under
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64 the SafeRTOS brand: http://www.SafeRTOS.com.
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67 /* Hardware specific includes. */
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68 #include "iodefine.h"
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69 #include "typedefine.h"
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70 #include "hwEthernet.h"
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71 #include "hwEthernetPhy.h"
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73 /* FreeRTOS includes. */
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74 #include "FreeRTOS.h"
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79 #include "net/uip.h"
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81 /* The time to wait between attempts to obtain a free buffer. */
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82 #define emacBUFFER_WAIT_DELAY_ms ( 3 / portTICK_RATE_MS )
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84 /* The number of times emacBUFFER_WAIT_DELAY_ms should be waited before giving
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85 up on attempting to obtain a free buffer all together. */
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86 #define emacBUFFER_WAIT_ATTEMPTS ( 30 )
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88 /* The number of Rx descriptors. */
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89 #define emacNUM_RX_DESCRIPTORS 3
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91 /* The number of Tx descriptors. When using uIP there is not point in having
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93 #define emacNUM_TX_BUFFERS 2
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95 /* The total number of EMAC buffers to allocate. */
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96 #define emacNUM_BUFFERS ( emacNUM_RX_DESCRIPTORS + emacNUM_TX_BUFFERS )
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98 /* The time to wait for the Tx descriptor to become free. */
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99 #define emacTX_WAIT_DELAY_ms ( 10 / portTICK_RATE_MS )
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101 /* The total number of times to wait emacTX_WAIT_DELAY_ms for the Tx descriptor to
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103 #define emacTX_WAIT_ATTEMPTS ( 5 )
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105 /* Only Rx end and Tx end interrupts are used by this driver. */
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106 #define emacTX_END_INTERRUPT ( 1UL << 21UL )
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107 #define emacRX_END_INTERRUPT ( 1UL << 18UL )
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109 /*-----------------------------------------------------------*/
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111 /* The buffers and descriptors themselves. */
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112 #pragma section RX_DESCR
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113 ethfifo xRxDescriptors[ emacNUM_RX_DESCRIPTORS ];
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114 #pragma section TX_DESCR
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115 ethfifo xTxDescriptors[ emacNUM_TX_BUFFERS ];
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116 #pragma section _ETHERNET_BUFFERS
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117 char xEthernetBuffers[ emacNUM_BUFFERS ][ UIP_BUFSIZE ];
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120 /* Used to indicate which buffers are free and which are in use. If an index
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121 contains 0 then the corresponding buffer in xEthernetBuffers is free, otherwise
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122 the buffer is in use or about to be used. */
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123 static unsigned char ucBufferInUse[ emacNUM_BUFFERS ];
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125 /*-----------------------------------------------------------*/
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128 * Initialise both the Rx and Tx descriptors.
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130 static void prvInitialiseDescriptors( void );
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133 * Return a pointer to a free buffer within xEthernetBuffers.
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135 static unsigned char *prvGetNextBuffer( void );
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138 * Return a buffer to the list of free buffers.
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140 static void prvReturnBuffer( unsigned char *pucBuffer );
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143 * Examine the status of the next Rx FIFO to see if it contains new data.
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145 static unsigned long prvCheckRxFifoStatus( void );
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148 * Setup the microcontroller for communication with the PHY.
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150 static void prvSetupPortPinsAndReset( void );
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153 * Configure the Ethernet interface peripherals.
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155 static void prvConfigureEtherCAndEDMAC( void );
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158 * Something has gone wrong with the descriptor usage. Reset all the buffers
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161 static void prvResetEverything( void );
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163 /*-----------------------------------------------------------*/
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165 /* Points to the Rx descriptor currently in use. */
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166 static ethfifo *xCurrentRxDesc = NULL;
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168 /* The buffer used by the uIP stack to both receive and send. This points to
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169 one of the Ethernet buffers when its actually in use. */
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170 unsigned char *uip_buf = NULL;
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172 /*-----------------------------------------------------------*/
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174 void vInitEmac( void )
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176 /* Setup the SH hardware for MII communications. */
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177 prvSetupPortPinsAndReset();
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179 /* Set the Rx and Tx descriptors into their initial state. */
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180 prvInitialiseDescriptors();
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182 /* Set the MAC address into the ETHERC */
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183 EtherC.MAHR = ( ( unsigned long ) configMAC_ADDR0 << 24UL ) |
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184 ( ( unsigned long ) configMAC_ADDR1 << 16UL ) |
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185 ( ( unsigned long ) configMAC_ADDR2 << 8UL ) |
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186 ( unsigned long ) configMAC_ADDR3;
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188 EtherC.MALR.BIT.MA = ( ( unsigned long ) configMAC_ADDR4 << 8UL ) |
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189 ( unsigned long ) configMAC_ADDR5;
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191 /* Perform rest of interface hardware configuration. */
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192 prvConfigureEtherCAndEDMAC();
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194 /* Nothing received yet, so uip_buf points nowhere. */
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197 /* Initialize the PHY */
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200 /*-----------------------------------------------------------*/
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202 void vEMACWrite( void )
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206 /* Wait until the second transmission of the last packet has completed. */
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207 for( x = 0; x < emacTX_WAIT_ATTEMPTS; x++ )
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209 if( ( xTxDescriptors[ 1 ].status & ACT ) != 0 )
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211 /* Descriptor is still active. */
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212 vTaskDelay( emacTX_WAIT_DELAY_ms );
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220 /* Is the descriptor free after waiting for it? */
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221 if( ( xTxDescriptors[ 1 ].status & ACT ) != 0 )
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223 /* Something has gone wrong. */
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224 prvResetEverything();
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227 /* Setup both descriptors to transmit the frame. */
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228 xTxDescriptors[ 0 ].buf_p = ( char * ) uip_buf;
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229 xTxDescriptors[ 0 ].bufsize = uip_len;
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230 xTxDescriptors[ 1 ].buf_p = ( char * ) uip_buf;
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231 xTxDescriptors[ 1 ].bufsize = uip_len;
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233 /* uip_buf is being sent by the Tx descriptor. Allocate a new buffer
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234 for use by the stack. */
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235 uip_buf = prvGetNextBuffer();
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237 /* Clear previous settings and go. */
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238 xTxDescriptors[0].status &= ~( FP1 | FP0 );
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239 xTxDescriptors[0].status |= ( FP1 | FP0 | ACT );
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240 xTxDescriptors[1].status &= ~( FP1 | FP0 );
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241 xTxDescriptors[1].status |= ( FP1 | FP0 | ACT );
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243 EDMAC.EDTRR.LONG = 0x00000001;
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245 /*-----------------------------------------------------------*/
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247 unsigned long ulEMACRead( void )
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249 unsigned long ulBytesReceived;
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251 ulBytesReceived = prvCheckRxFifoStatus();
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253 if( ulBytesReceived > 0 )
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255 xCurrentRxDesc->status &= ~( FP1 | FP0 );
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256 xCurrentRxDesc->status |= ACT;
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258 if( EDMAC.EDRRR.LONG == 0x00000000L )
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260 /* Restart Ethernet if it has stopped */
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261 EDMAC.EDRRR.LONG = 0x00000001L;
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264 /* Mark the pxDescriptor buffer as free as uip_buf is going to be set to
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265 the buffer that contains the received data. */
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266 prvReturnBuffer( uip_buf );
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268 uip_buf = ( void * ) xCurrentRxDesc->buf_p;
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270 /* Move onto the next buffer in the ring. */
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271 xCurrentRxDesc = xCurrentRxDesc->next;
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274 return ulBytesReceived;
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276 /*-----------------------------------------------------------*/
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278 long lEMACWaitForLink( void )
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282 /* Set the link status. */
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283 switch( phyStatus() )
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285 /* Half duplex link */
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286 case PHY_LINK_100H:
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288 EtherC.ECMR.BIT.DM = 0;
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292 /* Full duplex link */
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293 case PHY_LINK_100F:
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295 EtherC.ECMR.BIT.DM = 1;
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304 if( lReturn == pdPASS )
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306 /* Enable receive and transmit. */
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307 EtherC.ECMR.BIT.RE = 1;
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308 EtherC.ECMR.BIT.TE = 1;
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310 /* Enable EDMAC receive */
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311 EDMAC.EDRRR.LONG = 0x1;
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316 /*-----------------------------------------------------------*/
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318 static void prvInitialiseDescriptors( void )
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320 ethfifo *pxDescriptor;
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323 for( x = 0; x < emacNUM_BUFFERS; x++ )
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325 /* Ensure none of the buffers are shown as in use at the start. */
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326 ucBufferInUse[ x ] = pdFALSE;
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329 /* Initialise the Rx descriptors. */
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330 for( x = 0; x < emacNUM_RX_DESCRIPTORS; x++ )
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332 pxDescriptor = &( xRxDescriptors[ x ] );
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333 pxDescriptor->buf_p = &( xEthernetBuffers[ x ][ 0 ] );
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335 pxDescriptor->bufsize = UIP_BUFSIZE;
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336 pxDescriptor->size = 0;
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337 pxDescriptor->status = ACT;
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338 pxDescriptor->next = &xRxDescriptors[ x + 1 ];
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340 /* Mark this buffer as in use. */
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341 ucBufferInUse[ x ] = pdTRUE;
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344 /* The last descriptor points back to the start. */
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345 pxDescriptor->status |= DL;
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346 pxDescriptor->next = &xRxDescriptors[ 0 ];
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348 /* Initialise the Tx descriptors. */
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349 for( x = 0; x < emacNUM_TX_BUFFERS; x++ )
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351 pxDescriptor = &( xTxDescriptors[ x ] );
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353 /* A buffer is not allocated to the Tx descriptor until a send is
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354 actually required. */
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355 pxDescriptor->buf_p = NULL;
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357 pxDescriptor->bufsize = UIP_BUFSIZE;
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358 pxDescriptor->size = 0;
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359 pxDescriptor->status = 0;
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360 pxDescriptor->next = &xTxDescriptors[ x + 1 ];
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363 /* The last descriptor points back to the start. */
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364 pxDescriptor->status |= DL;
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365 pxDescriptor->next = &( xTxDescriptors[ 0 ] );
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367 /* Use the first Rx descriptor to start with. */
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368 xCurrentRxDesc = &( xRxDescriptors[ 0 ] );
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370 /*-----------------------------------------------------------*/
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372 static unsigned char *prvGetNextBuffer( void )
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375 unsigned char *pucReturn = NULL;
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376 unsigned long ulAttempts = 0;
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378 while( pucReturn == NULL )
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380 /* Look through the buffers to find one that is not in use by
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382 for( x = 0; x < emacNUM_BUFFERS; x++ )
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384 if( ucBufferInUse[ x ] == pdFALSE )
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386 ucBufferInUse[ x ] = pdTRUE;
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387 pucReturn = ( unsigned char * ) &( xEthernetBuffers[ x ][ 0 ] );
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392 /* Was a buffer found? */
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393 if( pucReturn == NULL )
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397 if( ulAttempts >= emacBUFFER_WAIT_ATTEMPTS )
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402 /* Wait then look again. */
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403 vTaskDelay( emacBUFFER_WAIT_DELAY_ms );
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409 /*-----------------------------------------------------------*/
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411 static void prvReturnBuffer( unsigned char *pucBuffer )
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415 /* Return a buffer to the pool of free buffers. */
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416 for( ul = 0; ul < emacNUM_BUFFERS; ul++ )
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418 if( &( xEthernetBuffers[ ul ][ 0 ] ) == ( void * ) pucBuffer )
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420 ucBufferInUse[ ul ] = pdFALSE;
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425 /*-----------------------------------------------------------*/
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427 static void prvResetEverything( void )
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429 /* Temporary code just to see if this gets called. This function has not
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430 been implemented. */
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431 portDISABLE_INTERRUPTS();
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434 /*-----------------------------------------------------------*/
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436 static unsigned long prvCheckRxFifoStatus( void )
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438 unsigned long ulReturn = 0;
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440 if( ( xCurrentRxDesc->status & ACT ) != 0 )
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442 /* Current descriptor is still active. */
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444 else if( ( xCurrentRxDesc->status & FE ) != 0 )
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446 /* Frame error. Clear the error. */
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447 xCurrentRxDesc->status &= ~( FP1 | FP0 | FE );
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448 xCurrentRxDesc->status &= ~( RMAF | RRF | RTLF | RTSF | PRE | CERF );
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449 xCurrentRxDesc->status |= ACT;
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450 xCurrentRxDesc = xCurrentRxDesc->next;
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452 if( EDMAC.EDRRR.LONG == 0x00000000UL )
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454 /* Restart Ethernet if it has stopped. */
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455 EDMAC.EDRRR.LONG = 0x00000001UL;
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460 /* The descriptor contains a frame. Because of the size of the buffers
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461 the frame should always be complete. */
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462 if( (xCurrentRxDesc->status & FP0) == FP0 )
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464 ulReturn = xCurrentRxDesc->size;
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468 /* Do not expect to get here. */
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469 prvResetEverything();
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475 /*-----------------------------------------------------------*/
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477 static void prvSetupPortPinsAndReset( void )
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479 /* Initialisation code taken from Renesas example project. */
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481 PFC.PACRL4.BIT.PA12MD = 0x7; /* Set TX_CLK input (EtherC) */
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482 PFC.PACRL3.BIT.PA11MD = 0x7; /* Set TX_EN output (EtherC) */
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483 PFC.PACRL3.BIT.PA10MD = 0x7; /* Set MII_TXD0 output (EtherC) */
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484 PFC.PACRL3.BIT.PA9MD = 0x7; /* Set MII_TXD1 output (EtherC) */
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485 PFC.PACRL3.BIT.PA8MD = 0x7; /* Set MII_TXD2 output (EtherC) */
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486 PFC.PACRL2.BIT.PA7MD = 0x7; /* Set MII_TXD3 output (EtherC) */
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487 PFC.PACRL2.BIT.PA6MD = 0x7; /* Set TX_ER output (EtherC) */
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488 PFC.PDCRH4.BIT.PD31MD = 0x7; /* Set RX_DV input (EtherC) */
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489 PFC.PDCRH4.BIT.PD30MD = 0x7; /* Set RX_ER input (EtherC) */
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490 PFC.PDCRH4.BIT.PD29MD = 0x7; /* Set MII_RXD3 input (EtherC) */
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491 PFC.PDCRH4.BIT.PD28MD = 0x7; /* Set MII_RXD2 input (EtherC) */
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492 PFC.PDCRH3.BIT.PD27MD = 0x7; /* Set MII_RXD1 input (EtherC) */
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493 PFC.PDCRH3.BIT.PD26MD = 0x7; /* Set MII_RXD0 input (EtherC) */
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494 PFC.PDCRH3.BIT.PD25MD = 0x7; /* Set RX_CLK input (EtherC) */
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495 PFC.PDCRH3.BIT.PD24MD = 0x7; /* Set CRS input (EtherC) */
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496 PFC.PDCRH2.BIT.PD23MD = 0x7; /* Set COL input (EtherC) */
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497 PFC.PDCRH2.BIT.PD22MD = 0x7; /* Set WOL output (EtherC) */
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498 PFC.PDCRH2.BIT.PD21MD = 0x7; /* Set EXOUT output (EtherC) */
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499 PFC.PDCRH2.BIT.PD20MD = 0x7; /* Set MDC output (EtherC) */
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500 PFC.PDCRH1.BIT.PD19MD = 0x7; /* Set LINKSTA input (EtherC) */
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501 PFC.PDCRH1.BIT.PD18MD = 0x7; /* Set MDIO input/output (EtherC) */
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503 STB.CR4.BIT._ETHER = 0x0;
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504 EDMAC.EDMR.BIT.SWR = 1;
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506 /* Crude wait for reset to complete. */
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507 vTaskDelay( 500 / portTICK_RATE_MS );
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509 /*-----------------------------------------------------------*/
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511 static void prvConfigureEtherCAndEDMAC( void )
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513 /* Initialisation code taken from Renesas example project. */
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515 /* TODO: Check bit 5 */
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516 EtherC.ECSR.LONG = 0x00000037; /* Clear all EtherC statuS BFR, PSRTO, LCHNG, MPD, ICD */
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518 /* TODO: Check bit 5 */
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519 EtherC.ECSIPR.LONG = 0x00000020; /* Disable EtherC status change interrupt */
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520 EtherC.RFLR.LONG = 1518; /* Ether payload is 1500+ CRC */
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521 EtherC.IPGR.LONG = 0x00000014; /* Intergap is 96-bit time */
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524 EDMAC.EESR.LONG = 0x47FF0F9F; /* Clear all EtherC and EDMAC status bits */
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525 EDMAC.RDLAR = ( void * ) xCurrentRxDesc; /* Initialaize Rx Descriptor List Address */
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526 EDMAC.TDLAR = &( xTxDescriptors[ 0 ] ); /* Initialaize Tx Descriptor List Address */
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527 EDMAC.TRSCER.LONG = 0x00000000; /* Copy-back status is RFE & TFE only */
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528 EDMAC.TFTR.LONG = 0x00000000; /* Threshold of Tx_FIFO */
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529 EDMAC.FDR.LONG = 0x00000000; /* Transmit fifo & receive fifo is 256 bytes */
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530 EDMAC.RMCR.LONG = 0x00000003; /* Receive function is normal mode(continued) */
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532 /* Set the EDMAC interrupt priority - the interrupt priority must be
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533 configKERNEL_INTERRUPT_PRIORITY no matter which peripheral is used to
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534 generate the tick interrupt. */
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535 INTC.IPR19.BIT._EDMAC = portKERNEL_INTERRUPT_PRIORITY;
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536 EDMAC.EESIPR.LONG = emacTX_END_INTERRUPT | emacRX_END_INTERRUPT; /* Enable Rx and Tx end interrupts. */
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538 /* Clear the interrupt flag. */
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539 CMT0.CMCSR.BIT.CMF = 0;
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541 /*-----------------------------------------------------------*/
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543 void vEMAC_ISR_Handler( void )
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545 unsigned long ul = EDMAC.EESR.LONG;
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546 long lHigherPriorityTaskWoken = pdFALSE;
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547 extern xSemaphoreHandle xEMACSemaphore;
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548 static long ulTxEndInts = 0;
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550 /* Has a Tx end occurred? */
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551 if( ul & emacTX_END_INTERRUPT )
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554 if( ulTxEndInts >= 2 )
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556 /* Only return the buffer to the pool once both Txes have completed. */
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557 prvReturnBuffer( ( void * ) xTxDescriptors[ 0 ].buf_p );
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560 EDMAC.EESR.LONG = emacTX_END_INTERRUPT;
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563 /* Has an Rx end occurred? */
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564 if( ul & emacRX_END_INTERRUPT )
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566 /* Make sure the Ethernet task is not blocked waiting for a packet. */
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567 xSemaphoreGiveFromISR( xEMACSemaphore, &lHigherPriorityTaskWoken );
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568 portYIELD_FROM_ISR( lHigherPriorityTaskWoken );
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569 EDMAC.EESR.LONG = emacRX_END_INTERRUPT;
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