2 * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
8 * http://www.apache.org/licenses/LICENSE-2.0
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
17 /******************************************************************************
19 * @brief CSI CK802 Core Peripheral Access Layer Header File
22 ******************************************************************************/
24 #ifndef __CORE_CK802_H_GENERIC
25 #define __CORE_CK802_H_GENERIC
33 /*******************************************************************************
35 ******************************************************************************/
41 /* CSI CK802 definitions */
42 #define __CK802_CSI_VERSION_MAIN (0x04U) /*!< [31:16] CSI HAL main version */
43 #define __CK802_CSI_VERSION_SUB (0x1EU) /*!< [15:0] CSI HAL sub version */
44 #define __CK802_CSI_VERSION ((__CK802_CSI_VERSION_MAIN << 16U) | \
45 __CK802_CSI_VERSION_SUB ) /*!< CSI HAL version number */
47 #define __CK80X (0x02U) /*!< CK80X Core */
50 /** __FPU_USED indicates whether an FPU is used or not.
51 This core does not support an FPU at all
55 #if defined ( __GNUC__ )
56 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
57 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
67 #endif /* __CORE_CK802_H_GENERIC */
71 #ifndef __CORE_CK802_H_DEPENDANT
72 #define __CORE_CK802_H_DEPENDANT
78 /* check device defines and use defaults */
79 //#if defined __CHECK_DEVICE_DEFINES
81 #define __CK802_REV 0x0000U
82 //#warning "__CK802_REV not defined in device header file; using default!"
85 #ifndef __NVIC_PRIO_BITS
86 #define __NVIC_PRIO_BITS 2U
87 //#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
90 #ifndef __Vendor_SysTickConfig
91 #define __Vendor_SysTickConfig 0U
92 //#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
95 #ifndef __GSR_GCR_PRESENT
96 #define __GSR_GCR_PRESENT 0U
97 //#warning "__GSR_GCR_PRESENT not defined in device header file; using default!"
100 #ifndef __MGU_PRESENT
101 #define __MGU_PRESENT 0U
102 //#warning "__MGU_PRESENT not defined in device header file; using default!"
106 /* IO definitions (access restrictions to peripheral registers) */
108 \defgroup CSI_glob_defs CSI Global Defines
110 <strong>IO Type Qualifiers</strong> are used
111 \li to specify the access to peripheral variables.
112 \li for automatic generation of peripheral register debug information.
115 #define __I volatile /*!< Defines 'read only' permissions */
117 #define __I volatile const /*!< Defines 'read only' permissions */
119 #define __O volatile /*!< Defines 'write only' permissions */
120 #define __IO volatile /*!< Defines 'read / write' permissions */
122 /* following defines should be used for structure members */
123 #define __IM volatile const /*! Defines 'read only' structure member permissions */
124 #define __OM volatile /*! Defines 'write only' structure member permissions */
125 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
127 /*@} end of group CK802 */
129 /*******************************************************************************
130 * Register Abstraction
131 Core Register contain:
135 - Core SysTick Register
136 ******************************************************************************/
138 \defgroup CSI_core_register Defines and Type Definitions
139 \brief Type definitions and defines for CK80X processor based devices.
143 \ingroup CSI_core_register
144 \defgroup CSI_CORE Status and Control Registers
145 \brief Core Register type definitions.
150 \brief 访问处理器状态寄存器(PSR)的联合体定义.
154 uint32_t C: 1; /*!< bit: 0 条件码/进位位 */
155 uint32_t _reserved0: 5; /*!< bit: 2.. 5 保留 */
156 uint32_t IE: 1; /*!< bit: 6 中断有效控制位 */
157 uint32_t IC: 1; /*!< bit: 7 中断控制位 */
158 uint32_t EE: 1; /*!< bit: 8 异常有效控制位 */
159 uint32_t MM: 1; /*!< bit: 9 不对齐异常掩盖位 */
160 uint32_t _reserved1: 6; /*!< bit: 10..15 保留 */
161 uint32_t VEC: 8; /*!< bit: 16..23 异常事件向量值 */
162 uint32_t _reserved2: 7; /*!< bit: 24..30 保留 */
163 uint32_t S: 1; /*!< bit: 31 超级用户模式设置位 */
164 } b; /*!< Structure 用来按位访问 */
165 uint32_t w; /*!< Type 整个寄存器访问 */
168 /* PSR Register Definitions */
169 #define PSR_S_Pos 31U /*!< PSR: S Position */
170 #define PSR_S_Msk (1UL << PSR_S_Pos) /*!< PSR: S Mask */
172 #define PSR_VEC_Pos 16U /*!< PSR: VEC Position */
173 #define PSR_VEC_Msk (0x7FUL << PSR_VEC_Pos) /*!< PSR: VEC Mask */
175 #define PSR_MM_Pos 9U /*!< PSR: MM Position */
176 #define PSR_MM_Msk (1UL << PSR_MM_Pos) /*!< PSR: MM Mask */
178 #define PSR_EE_Pos 8U /*!< PSR: EE Position */
179 #define PSR_EE_Msk (1UL << PSR_EE_Pos) /*!< PSR: EE Mask */
181 #define PSR_IC_Pos 7U /*!< PSR: IC Position */
182 #define PSR_IC_Msk (1UL << PSR_IC_Pos) /*!< PSR: IC Mask */
184 #define PSR_IE_Pos 6U /*!< PSR: IE Position */
185 #define PSR_IE_Msk (1UL << PSR_IE_Pos) /*!< PSR: IE Mask */
187 #define PSR_C_Pos 0U /*!< PSR: C Position */
188 #define PSR_C_Msk (1UL << PSR_C_Pos) /*!< PSR: C Mask */
191 \brief 访问高速缓存配置寄存器(CCR, CR<18, 0>)的联合体定义.
195 uint32_t MP: 1; /*!< bit: 0 内存保护设置位 */
196 uint32_t _reserved0: 6; /*!< bit: 1.. 6 保留 */
197 uint32_t BE: 1; /*!< bit: 7 Endian模式 */
198 uint32_t SCK: 3; /*!< bit: 8..10 系统和处理器的时钟比 */
199 uint32_t _reserved1: 2; /*!< bit: 11..12 保留 */
200 uint32_t BE_V2: 1; /*!< bit: 13 V2版本大小端 */
201 uint32_t _reserved2: 18; /*!< bit: 14..31 保留 */
202 } b; /*!< Structure 用来按位访问 */
203 uint32_t w; /*!< Type 整个寄存器访问 */
206 /* CCR Register Definitions */
207 #define CCR_BE_V2_Pos 13U /*!< CCR: BE_V2 Position */
208 #define CCR_BE_V2_Msk (0x1UL << CCR_ISR_Pos) /*!< CCR: BE_V2 Mask */
210 #define CCR_SCK_Pos 8U /*!< CCR: SCK Position */
211 #define CCR_SCK_Msk (0x3UL << CCR_SCK_Pos) /*!< CCR: SCK Mask */
213 #define CCR_BE_Pos 7U /*!< CCR: BE Position */
214 #define CCR_BE_Msk (0x1UL << CCR_BE_Pos) /*!< CCR: BE Mask */
216 #define CCR_MP_Pos 0U /*!< CCR: MP Position */
217 #define CCR_MP_Msk (0x1UL << CCR_MP_Pos) /*!< CCR: MP Mask */
220 \brief 访问可高缓和访问权限配置寄存器(CAPR, CR<19,0>)的联合体定义..
224 uint32_t X0: 1; /*!< bit: 0 不可执行属性设置位 */
225 uint32_t X1: 1; /*!< bit: 1 不可执行属性设置位 */
226 uint32_t X2: 1; /*!< bit: 2 不可执行属性设置位 */
227 uint32_t X3: 1; /*!< bit: 3 不可执行属性设置位 */
228 uint32_t X4: 1; /*!< bit: 4 不可执行属性设置位 */
229 uint32_t X5: 1; /*!< bit: 5 不可执行属性设置位 */
230 uint32_t X6: 1; /*!< bit: 6 不可执行属性设置位 */
231 uint32_t X7: 1; /*!< bit: 7 不可执行属性设置位 */
232 uint32_t AP0: 2; /*!< bit: 8.. 9 访问权限设置位 */
233 uint32_t AP1: 2; /*!< bit: 10..11 访问权限设置位 */
234 uint32_t AP2: 2; /*!< bit: 12..13 访问权限设置位 */
235 uint32_t AP3: 2; /*!< bit: 14..15 访问权限设置位 */
236 uint32_t AP4: 2; /*!< bit: 16..17 访问权限设置位 */
237 uint32_t AP5: 2; /*!< bit: 18..19 访问权限设置位 */
238 uint32_t AP6: 2; /*!< bit: 20..21 访问权限设置位 */
239 uint32_t AP7: 2; /*!< bit: 22..23 访问权限设置位 */
240 uint32_t S0: 1; /*!< bit: 24 安全属性设置位 */
241 uint32_t S1: 1; /*!< bit: 25 安全属性设置位 */
242 uint32_t S2: 1; /*!< bit: 26 安全属性设置位 */
243 uint32_t S3: 1; /*!< bit: 27 安全属性设置位 */
244 uint32_t S4: 1; /*!< bit: 28 安全属性设置位 */
245 uint32_t S5: 1; /*!< bit: 29 安全属性设置位 */
246 uint32_t S6: 1; /*!< bit: 30 安全属性设置位 */
247 uint32_t S7: 1; /*!< bit: 31 安全属性设置位 */
248 } b; /*!< Structure 用来按位访问 */
249 uint32_t w; /*!< Type 整个寄存器访问 */
252 /* CAPR Register Definitions */
253 #define CAPR_S7_Pos 31U /*!< CAPR: S7 Position */
254 #define CAPR_S7_Msk (1UL << CAPR_S7_Pos) /*!< CAPR: S7 Mask */
256 #define CAPR_S6_Pos 30U /*!< CAPR: S6 Position */
257 #define CAPR_S6_Msk (1UL << CAPR_S6_Pos) /*!< CAPR: S6 Mask */
259 #define CAPR_S5_Pos 29U /*!< CAPR: S5 Position */
260 #define CAPR_S5_Msk (1UL << CAPR_S5_Pos) /*!< CAPR: S5 Mask */
262 #define CAPR_S4_Pos 28U /*!< CAPR: S4 Position */
263 #define CAPR_S4_Msk (1UL << CAPR_S4_Pos) /*!< CAPR: S4 Mask */
265 #define CAPR_S3_Pos 27U /*!< CAPR: S3 Position */
266 #define CAPR_S3_Msk (1UL << CAPR_S3_Pos) /*!< CAPR: S3 Mask */
268 #define CAPR_S2_Pos 26U /*!< CAPR: S2 Position */
269 #define CAPR_S2_Msk (1UL << CAPR_S2_Pos) /*!< CAPR: S2 Mask */
271 #define CAPR_S1_Pos 25U /*!< CAPR: S1 Position */
272 #define CAPR_S1_Msk (1UL << CAPR_S1_Pos) /*!< CAPR: S1 Mask */
274 #define CAPR_S0_Pos 24U /*!< CAPR: S0 Position */
275 #define CAPR_S0_Msk (1UL << CAPR_S0_Pos) /*!< CAPR: S0 Mask */
277 #define CAPR_AP7_Pos 22U /*!< CAPR: AP7 Position */
278 #define CAPR_AP7_Msk (0x3UL << CAPR_AP7_Pos) /*!< CAPR: AP7 Mask */
280 #define CAPR_AP6_Pos 20U /*!< CAPR: AP6 Position */
281 #define CAPR_AP6_Msk (0x3UL << CAPR_AP6_Pos) /*!< CAPR: AP6 Mask */
283 #define CAPR_AP5_Pos 18U /*!< CAPR: AP5 Position */
284 #define CAPR_AP5_Msk (0x3UL << CAPR_AP5_Pos) /*!< CAPR: AP5 Mask */
286 #define CAPR_AP4_Pos 16U /*!< CAPR: AP4 Position */
287 #define CAPR_AP4_Msk (0x3UL << CAPR_AP4_Pos) /*!< CAPR: AP4 Mask */
289 #define CAPR_AP3_Pos 14U /*!< CAPR: AP3 Position */
290 #define CAPR_AP3_Msk (0x3UL << CAPR_AP3_Pos) /*!< CAPR: AP3 Mask */
292 #define CAPR_AP2_Pos 12U /*!< CAPR: AP2 Position */
293 #define CAPR_AP2_Msk (0x3UL << CAPR_AP2_Pos) /*!< CAPR: AP2 Mask */
295 #define CAPR_AP1_Pos 10U /*!< CAPR: AP1 Position */
296 #define CAPR_AP1_Msk (0x3UL << CAPR_AP1_Pos) /*!< CAPR: AP1 Mask */
298 #define CAPR_AP0_Pos 8U /*!< CAPR: AP0 Position */
299 #define CAPR_AP0_Msk (0x3UL << CAPR_AP0_Pos) /*!< CAPR: AP0 Mask */
301 #define CAPR_X7_Pos 7U /*!< CAPR: X7 Position */
302 #define CAPR_X7_Msk (0x1UL << CAPR_X7_Pos) /*!< CAPR: X7 Mask */
304 #define CAPR_X6_Pos 6U /*!< CAPR: X6 Position */
305 #define CAPR_X6_Msk (0x1UL << CAPR_X6_Pos) /*!< CAPR: X6 Mask */
307 #define CAPR_X5_Pos 5U /*!< CAPR: X5 Position */
308 #define CAPR_X5_Msk (0x1UL << CAPR_X5_Pos) /*!< CAPR: X5 Mask */
310 #define CAPR_X4_Pos 4U /*!< CAPR: X4 Position */
311 #define CAPR_X4_Msk (0x1UL << CAPR_X4_Pos) /*!< CAPR: X4 Mask */
313 #define CAPR_X3_Pos 3U /*!< CAPR: X3 Position */
314 #define CAPR_X3_Msk (0x1UL << CAPR_X3_Pos) /*!< CAPR: X3 Mask */
316 #define CAPR_X2_Pos 2U /*!< CAPR: X2 Position */
317 #define CAPR_X2_Msk (0x1UL << CAPR_X2_Pos) /*!< CAPR: X2 Mask */
319 #define CAPR_X1_Pos 1U /*!< CAPR: X1 Position */
320 #define CAPR_X1_Msk (0x1UL << CAPR_X1_Pos) /*!< CAPR: X1 Mask */
322 #define CAPR_X0_Pos 0U /*!< CAPR: X0 Position */
323 #define CAPR_X0_Msk (0x1UL << CAPR_X0_Pos) /*!< CAPR: X0 Mask */
326 \brief 访问保护区控制寄存器(PACR, CR<20,0>)的联合体定义.
330 uint32_t E: 1; /*!< bit: 0 保护区有效设置 */
331 uint32_t Size: 5; /*!< bit: 1.. 5 保护区大小 */
332 uint32_t _reserved0: 4; /*!< bit: 6.. 9 保留 */
333 uint32_t base_addr: 22; /*!< bit: 10..31 保护区地址的高位 */
334 } b; /*!< Structure 用来按位访问 */
335 uint32_t w; /*!< Type 整个寄存器访问 */
338 /* PACR Register Definitions */
339 #define PACR_BASE_ADDR_Pos 10U /*!< PACR: base_addr Position */
340 #define PACK_BASE_ADDR_Msk (0x3FFFFFUL << PACR_BASE_ADDR_Pos) /*!< PACR: base_addr Mask */
342 #define PACR_SIZE_Pos 1U /*!< PACR: Size Position */
343 #define PACK_SIZE_Msk (0x1FUL << PACR_SIZE_Pos) /*!< PACR: Size Mask */
345 #define PACR_E_Pos 0U /*!< PACR: E Position */
346 #define PACK_E_Msk (0x1UL << PACR_E_Pos) /*!< PACR: E Mask */
349 \brief 访问保护区选择寄存器(PRSR,CR<21,0>)的联合体定义.
353 uint32_t RID: 3; /*!< bit: 0.. 2 保护区索引值 */
354 uint32_t _reserved0: 30; /*!< bit: 3..31 保留 */
355 } b; /*!< Structure 用来按位访问 */
356 uint32_t w; /*!< Type 整个寄存器访问 */
359 /* PRSR Register Definitions */
360 #define PRSR_RID_Pos 0U /*!< PRSR: RID Position */
361 #define PRSR_RID_Msk (0x7UL << PRSR_RID_Pos) /*!< PRSR: RID Mask */
363 /*@} end of group CSI_CORE */
367 \ingroup CSI_core_register
368 \defgroup CSI_NVIC Vectored Interrupt Controller (NVIC)
369 \brief Type definitions for the NVIC Registers
374 \brief 访问矢量中断控制器的结构体.
377 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) 中断使能设置寄存器 */
378 uint32_t RESERVED0[15U];
379 __IOM uint32_t IWER[1U]; /*!< Offset: 0x040 (R/W) 中断低功耗唤醒设置寄存器 */
380 uint32_t RESERVED1[15U];
381 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) 中断使能清除寄存器 */
382 uint32_t RESERVED2[15U];
383 __IOM uint32_t IWDR[1U]; /*!< Offset: 0x0c0 (R/W) 中断低功耗唤醒清除寄存器 */
384 uint32_t RESERVED3[15U];
385 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) 中断等待设置寄存器 */
386 uint32_t RESERVED4[15U];
387 __IOM uint32_t ISSR[1U]; /*!< Offset: 0x140 (R/W) 安全中断使能设置寄存器 */
388 uint32_t RESERVED5[15U];
389 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) 中断等待清除寄存器 */
390 uint32_t RESERVED6[31U];
391 __IOM uint32_t IABR[1U]; /*!< Offset: 0x200 (R/W) 中断响应状态寄存器 */
392 uint32_t RESERVED7[63U];
393 __IOM uint32_t IPR[8U]; /*!< Offset: 0x300 (R/W) 中断优先级设置寄存器 */
394 uint32_t RESERVED8[504U];
395 __IM uint32_t ISR; /*!< Offset: 0xB00 (R/ ) 中断状态寄存器 */
396 __IOM uint32_t IPTR; /*!< Offset: 0xB04 (R/W) 中断优先级阈值寄存器 */
399 /*@} end of group CSI_NVIC */
402 \ingroup CSI_core_register
403 \defgroup CSI_SysTick System Tick Timer (CORET)
404 \brief Type definitions for the System Timer Registers.
412 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) 控制状态寄存器 */
413 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) 回填值寄存器 */
414 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) 当前值寄存器 */
415 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) 校准寄存器 */
418 /* CORET Control / Status Register Definitions */
419 #define CORET_CTRL_COUNTFLAG_Pos 16U /*!< CORET CTRL: COUNTFLAG Position */
420 #define CORET_CTRL_COUNTFLAG_Msk (1UL << CORET_CTRL_COUNTFLAG_Pos) /*!< CORET CTRL: COUNTFLAG Mask */
422 #define CORET_CTRL_CLKSOURCE_Pos 2U /*!< CORET CTRL: CLKSOURCE Position */
423 #define CORET_CTRL_CLKSOURCE_Msk (1UL << CORET_CTRL_CLKSOURCE_Pos) /*!< CORET CTRL: CLKSOURCE Mask */
425 #define CORET_CTRL_TICKINT_Pos 1U /*!< CORET CTRL: TICKINT Position */
426 #define CORET_CTRL_TICKINT_Msk (1UL << CORET_CTRL_TICKINT_Pos) /*!< CORET CTRL: TICKINT Mask */
428 #define CORET_CTRL_ENABLE_Pos 0U /*!< CORET CTRL: ENABLE Position */
429 #define CORET_CTRL_ENABLE_Msk (1UL /*<< CORET_CTRL_ENABLE_Pos*/) /*!< CORET CTRL: ENABLE Mask */
431 /* CORET Reload Register Definitions */
432 #define CORET_LOAD_RELOAD_Pos 0U /*!< CORET LOAD: RELOAD Position */
433 #define CORET_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< CORET_LOAD_RELOAD_Pos*/) /*!< CORET LOAD: RELOAD Mask */
435 /* CORET Current Register Definitions */
436 #define CORET_VAL_CURRENT_Pos 0U /*!< CORET VAL: CURRENT Position */
437 #define CORET_VAL_CURRENT_Msk (0xFFFFFFUL /*<< CORET_VAL_CURRENT_Pos*/) /*!< CORET VAL: CURRENT Mask */
439 /* CORET Calibration Register Definitions */
440 #define CORET_CALIB_NOREF_Pos 31U /*!< CORET CALIB: NOREF Position */
441 #define CORET_CALIB_NOREF_Msk (1UL << CORET_CALIB_NOREF_Pos) /*!< CORET CALIB: NOREF Mask */
443 #define CORET_CALIB_SKEW_Pos 30U /*!< CORET CALIB: SKEW Position */
444 #define CORET_CALIB_SKEW_Msk (1UL << CORET_CALIB_SKEW_Pos) /*!< CORET CALIB: SKEW Mask */
446 #define CORET_CALIB_TENMS_Pos 0U /*!< CORET CALIB: TENMS Position */
447 #define CORET_CALIB_TENMS_Msk (0xFFFFFFUL /*<< CORET_CALIB_TENMS_Pos*/) /*!< CORET CALIB: TENMS Mask */
449 /*@} end of group CSI_SysTick */
452 \ingroup CSI_core_register
454 \brief Type definitions for the DCC.
462 uint32_t RESERVED0[13U];
463 __IOM uint32_t HCR; /*!< Offset: 0x034 (R/W) */
464 __IM uint32_t EHSR; /*!< Offset: 0x03C (R/ ) */
465 uint32_t RESERVED1[6U];
467 __IM uint32_t DERJW; /*!< Offset: 0x058 (R/ ) 数据交换寄存器 CPU读*/
468 __OM uint32_t DERJR; /*!< Offset: 0x058 ( /W) 数据交换寄存器 CPU写*/
473 #define DCC_HCR_JW_Pos 18U /*!< DCC HCR: jw_int_en Position */
474 #define DCC_HCR_JW_Msk (1UL << DCC_HCR_JW_Pos) /*!< DCC HCR: jw_int_en Mask */
476 #define DCC_HCR_JR_Pos 19U /*!< DCC HCR: jr_int_en Position */
477 #define DCC_HCR_JR_Msk (1UL << DCC_HCR_JR_Pos) /*!< DCC HCR: jr_int_en Mask */
479 #define DCC_EHSR_JW_Pos 1U /*!< DCC EHSR: jw_vld Position */
480 #define DCC_EHSR_JW_Msk (1UL << DCC_EHSR_JW_Pos) /*!< DCC EHSR: jw_vld Mask */
482 #define DCC_EHSR_JR_Pos 2U /*!< DCC EHSR: jr_vld Position */
483 #define DCC_EHSR_JR_Msk (1UL << DCC_EHSR_JR_Pos) /*!< DCC EHSR: jr_vld Mask */
485 /*@} end of group CSI_DCC */
489 \ingroup CSI_core_register
490 \defgroup CSI_core_bitfield Core register bit field macros
491 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
496 \brief Mask and shift a bit field value for use in a register bit range.
497 \param[in] field Name of the register bit field.
498 \param[in] value Value of the bit field.
499 \return Masked and shifted value.
501 #define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
504 \brief Mask and shift a register value to extract a bit filed value.
505 \param[in] field Name of the register bit field.
506 \param[in] value Value of register.
507 \return Masked and shifted bit field value.
509 #define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
511 /*@} end of group CSI_core_bitfield */
514 \ingroup CSI_core_register
515 \defgroup CSI_core_base Core Definitions
516 \brief Definitions for base addresses, unions, and structures.
520 /* Memory mapping of CK802 Hardware */
521 #define TCIP_BASE (0xE000E000UL) /*!< Titly Coupled IP Base Address */
522 #define CORET_BASE (TCIP_BASE + 0x0010UL) /*!< CORET Base Address */
523 #define NVIC_BASE (TCIP_BASE + 0x0100UL) /*!< NVIC Base Address */
524 #define DCC_BASE (0xE0011000UL) /*!< DCC Base Address */
526 #define CORET ((CORET_Type *) CORET_BASE ) /*!< SysTick configuration struct */
527 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
528 #define DCC ((DCC_Type *) DCC_BASE ) /*!< DCC configuration struct */
533 \brief Set Wake up Interrupt
534 \details Sets the wake up bit of an external interrupt.
535 \param [in] IRQn Interrupt number. Value cannot be negative.
537 void drv_nvic_set_wakeup_irq(int32_t IRQn);
538 void drv_nvic_clear_wakeup_irq(int32_t IRQn);
544 #endif /* __CORE_CK802_H_DEPENDANT */
546 #endif /* __CSI_GENERIC */