2 * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
8 * http://www.apache.org/licenses/LICENSE-2.0
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
17 /******************************************************************************
19 * @brief CSI Header File for reg.
22 ******************************************************************************/
30 \brief Enable IRQ Interrupts
31 \details Enables IRQ interrupts by setting the IE-bit in the PSR.
32 Can only be executed in Privileged modes.
34 __ALWAYS_INLINE void __enable_irq(void)
36 __ASM volatile("psrset ie");
42 \brief Disable IRQ Interrupts
43 \details Disables IRQ interrupts by clearing the IE-bit in the PSR.
44 Can only be executed in Privileged modes.
46 __ALWAYS_INLINE void __disable_irq(void)
48 __ASM volatile("psrclr ie");
53 \details Returns the content of the PSR Register.
54 \return PSR Register value
56 __ALWAYS_INLINE uint32_t __get_PSR(void)
60 __ASM volatile("mfcr %0, psr" : "=r"(result));
66 \details Writes the given value to the PSR Register.
67 \param [in] psr PSR Register value to set
69 __ALWAYS_INLINE void __set_PSR(uint32_t psr)
71 __ASM volatile("mtcr %0, psr" : : "r"(psr));
76 \details Returns the content of the SP Register.
77 \return SP Register value
79 __ALWAYS_INLINE uint32_t __get_SP(void)
83 __ASM volatile("mov %0, sp" : "=r"(result));
89 \details Writes the given value to the SP Register.
90 \param [in] sp SP Register value to set
92 __ALWAYS_INLINE void __set_SP(uint32_t sp)
94 __ASM volatile("mov sp, %0" : : "r"(sp): "sp");
99 \brief Get VBR Register
100 \details Returns the content of the VBR Register.
101 \return VBR Register value
103 __ALWAYS_INLINE uint32_t __get_VBR(void)
107 __ASM volatile("mfcr %0, vbr" : "=r"(result));
113 \details Writes the given value to the VBR Register.
114 \param [in] vbr VBR Register value to set
116 __ALWAYS_INLINE void __set_VBR(uint32_t vbr)
118 __ASM volatile("mtcr %0, vbr" : : "r"(vbr));
122 \brief Get EPC Register
123 \details Returns the content of the EPC Register.
124 \return EPC Register value
126 __ALWAYS_INLINE uint32_t __get_EPC(void)
130 __ASM volatile("mfcr %0, epc" : "=r"(result));
136 \details Writes the given value to the EPC Register.
137 \param [in] epc EPC Register value to set
139 __ALWAYS_INLINE void __set_EPC(uint32_t epc)
141 __ASM volatile("mtcr %0, epc" : : "r"(epc));
146 \details Returns the content of the EPSR Register.
147 \return EPSR Register value
149 __ALWAYS_INLINE uint32_t __get_EPSR(void)
153 __ASM volatile("mfcr %0, epsr" : "=r"(result));
159 \details Writes the given value to the EPSR Register.
160 \param [in] epsr EPSR Register value to set
162 __ALWAYS_INLINE void __set_EPSR(uint32_t epsr)
164 __ASM volatile("mtcr %0, epsr" : : "r"(epsr));
168 \brief Get CPUID Register
169 \details Returns the content of the CPUID Register.
170 \return CPUID Register value
172 __ALWAYS_INLINE uint32_t __get_CPUID(void)
177 __ASM volatile("mfcr %0, cr13" : "=r"(result));
179 __ASM volatile("mfcr %0, cr<13, 0>" : "=r"(result));
184 #if (__SOFTRESET_PRESENT == 1U)
187 \details Assigns the given value to the SRCR.
188 \param [in] srcr SRCR value to set
190 __ALWAYS_INLINE void __set_SRCR(uint32_t srcr)
192 __ASM volatile("mtcr %0, cr<31, 0>\n" : : "r"(srcr));
194 #endif /* __SOFTRESET_PRESENT == 1U */
196 #if (__MGU_PRESENT == 1U)
199 \details Returns the current value of the CCR.
200 \return CCR Register value
202 __ALWAYS_INLINE uint32_t __get_CCR(void)
204 register uint32_t result;
207 __ASM volatile("mfcr %0, cr18\n" : "=r"(result));
209 __ASM volatile("mfcr %0, cr<18, 0>\n" : "=r"(result));
217 \details Assigns the given value to the CCR.
218 \param [in] ccr CCR value to set
220 __ALWAYS_INLINE void __set_CCR(uint32_t ccr)
223 __ASM volatile("mtcr %0, cr18\n" : : "r"(ccr));
225 __ASM volatile("mtcr %0, cr<18, 0>\n" : : "r"(ccr));
232 \details Returns the current value of the CAPR.
233 \return CAPR Register value
235 __ALWAYS_INLINE uint32_t __get_CAPR(void)
237 register uint32_t result;
240 __ASM volatile("mfcr %0, cr19\n" : "=r"(result));
242 __ASM volatile("mfcr %0, cr<19, 0>\n" : "=r"(result));
249 \details Assigns the given value to the CAPR.
250 \param [in] capr CAPR value to set
252 __ALWAYS_INLINE void __set_CAPR(uint32_t capr)
255 __ASM volatile("mtcr %0, cr19\n" : : "r"(capr));
257 __ASM volatile("mtcr %0, cr<19, 0>\n" : : "r"(capr));
264 \details Assigns the given value to the PACR.
266 \param [in] pacr PACR value to set
268 __ALWAYS_INLINE void __set_PACR(uint32_t pacr)
271 __ASM volatile("mtcr %0, cr20\n" : : "r"(pacr));
273 __ASM volatile("mtcr %0, cr<20, 0>\n" : : "r"(pacr));
280 \details Returns the current value of PACR.
283 __ALWAYS_INLINE uint32_t __get_PACR(void)
288 __ASM volatile("mfcr %0, cr20" : "=r"(result));
290 __ASM volatile("mfcr %0, cr<20, 0>" : "=r"(result));
297 \details Assigns the given value to the PRSR.
299 \param [in] prsr PRSR value to set
301 __ALWAYS_INLINE void __set_PRSR(uint32_t prsr)
304 __ASM volatile("mtcr %0, cr21\n" : : "r"(prsr));
306 __ASM volatile("mtcr %0, cr<21, 0>\n" : : "r"(prsr));
312 \details Returns the current value of PRSR.
315 __ALWAYS_INLINE uint32_t __get_PRSR(void)
320 __ASM volatile("mfcr %0, cr21" : "=r"(result));
322 __ASM volatile("mfcr %0, cr<21, 0>" : "=r"(result));
326 #endif /* __MGU_PRESENT == 1U */
330 \details Returns the current value of user r14.
333 __ALWAYS_INLINE uint32_t __get_UR14(void)
338 __ASM volatile("mov %0, sp" : "=r"(result));
340 __ASM volatile("mfcr %0, cr<14, 1>" : "=r"(result));
346 \brief Enable interrupts and exceptions
347 \details Enables interrupts and exceptions by setting the IE-bit and EE-bit in the PSR.
348 Can only be executed in Privileged modes.
350 __ALWAYS_INLINE void __enable_excp_irq(void)
352 __ASM volatile("psrset ee, ie");
357 \brief Disable interrupts and exceptions
358 \details Disables interrupts and exceptions by clearing the IE-bit and EE-bit in the PSR.
359 Can only be executed in Privileged modes.
361 __ALWAYS_INLINE void __disable_excp_irq(void)
363 __ASM volatile("psrclr ee, ie");
366 #if (__GSR_GCR_PRESENT == 1U)
369 \details Returns the content of the GSR Register.
370 \return GSR Register value
372 __ALWAYS_INLINE uint32_t __get_GSR(void)
377 __ASM volatile("mfcr %0, cr12" : "=r"(result));
379 __ASM volatile("mfcr %0, cr<12, 0>" : "=r"(result));
386 \details Returns the content of the GCR Register.
387 \return GCR Register value
389 __ALWAYS_INLINE uint32_t __get_GCR(void)
394 __ASM volatile("mfcr %0, cr11" : "=r"(result));
396 __ASM volatile("mfcr %0, cr<11, 0>" : "=r"(result));
403 \details Writes the given value to the GCR Register.
404 \param [in] gcr GCR Register value to set
406 __ALWAYS_INLINE void __set_GCR(uint32_t gcr)
409 __ASM volatile("mtcr %0, cr11" : : "r"(gcr));
411 __ASM volatile("mtcr %0, cr<11, 0>" : : "r"(gcr));
415 #endif /* (__GSR_GCR_PRESENT == 1U) */
418 #endif /* _CSI_REG_H_ */