2 * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
8 * http://www.apache.org/licenses/LICENSE-2.0
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
17 /******************************************************************************
19 * @brief CSI Core Layer Header File
22 ******************************************************************************/
35 /* ################################## NVIC function ############################################ */
38 \brief initialize the NVIC interrupt controller
39 \param [in] prio_bits the priority bits of NVIC interrupt controller.
41 void drv_nvic_init(uint32_t prio_bits);
44 \brief Enable External Interrupt
45 \details Enables a device-specific interrupt in the NVIC interrupt controller.
46 \param [in] irq_num External interrupt number. Value cannot be negative.
48 void drv_nvic_enable_irq(int32_t irq_num);
50 \brief Disable External Interrupt
51 \details Disables a device-specific interrupt in the NVIC interrupt controller.
52 \param [in] irq_num External interrupt number. Value cannot be negative.
54 void drv_nvic_disable_irq(int32_t irq_num);
57 \brief Get Pending Interrupt
58 \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
59 \param [in] irq_num Interrupt number.
60 \return 0 Interrupt status is not pending.
61 \return 1 Interrupt status is pending.
63 uint32_t drv_nvic_get_pending_irq(int32_t irq_num);
66 \brief Set Pending Interrupt
67 \details Sets the pending bit of an external interrupt.
68 \param [in] irq_num Interrupt number. Value cannot be negative.
70 void drv_nvic_set_pending_irq(int32_t irq_num);
73 \brief Clear Pending Interrupt
74 \details Clears the pending bit of an external interrupt.
75 \param [in] irq_num External interrupt number. Value cannot be negative.
77 void drv_nvic_clear_pending_irq(int32_t irq_num);
80 \brief Get Active Interrupt
81 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
82 \param [in] irq_num Device specific interrupt number.
83 \return 0 Interrupt status is not active.
84 \return 1 Interrupt status is active.
85 \note irq_num must not be negative.
87 uint32_t drv_nvic_get_active(int32_t irq_num);
90 \brief Set Interrupt Priority
91 \details Sets the priority of an interrupt.
92 \note The priority cannot be set for every core interrupt.
93 \param [in] irq_num Interrupt number.
94 \param [in] priority Priority to set.
96 void drv_nvic_set_prio(int32_t irq_num, uint32_t priority);
98 \brief Get Interrupt Priority
99 \details Reads the priority of an interrupt.
100 The interrupt number can be positive to specify an external (device specific) interrupt,
101 or negative to specify an internal (core) interrupt.
102 \param [in] irq_num Interrupt number.
103 \return Interrupt Priority.
104 Value is aligned automatically to the implemented priority bits of the microcontroller.
106 uint32_t drv_nvic_get_prio(int32_t irq_num);
108 /*@} end of CSI_Core_NVICFunctions */
111 /* ########################## Cache functions #################################### */
114 \brief Enable I-Cache
115 \details Turns on I-Cache
117 void drv_icache_enable(void);
120 \brief Disable I-Cache
121 \details Turns off I-Cache
123 void drv_icache_disable(void);
126 \brief Invalidate I-Cache
127 \details Invalidates I-Cache
129 void drv_icache_invalid(void);
132 \brief Enable D-Cache
133 \details Turns on D-Cache
134 \note I-Cache also turns on.
136 void drv_dcache_enable(void);
139 \brief Disable D-Cache
140 \details Turns off D-Cache
141 \note I-Cache also turns off.
143 void drv_dcache_disable(void);
146 \brief Invalidate D-Cache
147 \details Invalidates D-Cache
148 \note I-Cache also invalid
150 void drv_dcache_invalid(void);
154 \details Cleans D-Cache
155 \note I-Cache also cleans
157 void drv_dcache_clean(void);
160 \brief Clean & Invalidate D-Cache
161 \details Cleans and Invalidates D-Cache
162 \note I-Cache also flush.
164 void drv_dcache_clean_invalid(void);
168 \brief D-Cache Invalidate by address
169 \details Invalidates D-Cache for the given address
170 \param[in] addr address (aligned to 16-byte boundary)
171 \param[in] dsize size of memory block (in number of bytes)
173 void drv_dcache_invalid_range(uint32_t *addr, int32_t dsize);
176 \brief D-Cache Clean by address
177 \details Cleans D-Cache for the given address
178 \param[in] addr address (aligned to 16-byte boundary)
179 \param[in] dsize size of memory block (in number of bytes)
181 void drv_dcache_clean_range(uint32_t *addr, int32_t dsize);
184 \brief D-Cache Clean and Invalidate by address
185 \details Cleans and invalidates D_Cache for the given address
186 \param[in] addr address (aligned to 16-byte boundary)
187 \param[in] dsize size of memory block (in number of bytes)
189 void drv_dcache_clean_invalid_range(uint32_t *addr, int32_t dsize);
192 \brief setup cacheable range Cache
193 \details setup Cache range
195 void drv_cache_set_range(uint32_t index, uint32_t baseAddr, uint32_t size, uint32_t enable);
198 \brief Enable cache profile
199 \details Turns on Cache profile
201 void drv_cache_enable_profile(void);
204 \brief Disable cache profile
205 \details Turns off Cache profile
207 void drv_cache_disable_profile(void);
209 \brief Reset cache profile
210 \details Reset Cache profile
212 void drv_cache_reset_profile(void);
215 \brief cache access times
216 \details Cache access times
217 \note every 256 access add 1.
219 uint32_t drv_cache_get_access_time(void);
222 \brief cache miss times
223 \details Cache miss times
224 \note every 256 miss add 1.
226 uint32_t drv_cache_get_miss_time(void);
228 /* ################################## SysTick function ############################################ */
231 \brief CORE timer Configuration
232 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
233 Counter is in free running mode to generate periodic interrupts.
234 \param [in] ticks Number of ticks between two interrupts.
235 \param [in] irq_num core timer Interrupt number.
236 \return 0 Function succeeded.
237 \return 1 Function failed.
238 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
239 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
240 must contain a vendor-specific implementation of this function.
242 uint32_t drv_coret_config(uint32_t ticks, int32_t irq_num);
245 \brief get CORE timer reload value
246 \return CORE timer counter value.
248 uint32_t drv_coret_get_load(void);
251 \brief get CORE timer counter value
252 \return CORE timer counter value.
254 uint32_t drv_coret_get_value(void);
257 \brief Save the Irq context
258 \details save the psr result before disable irq.
259 \param [in] irq_num External interrupt number. Value cannot be negative.
261 __ALWAYS_INLINE uint32_t drv_irq_save(void)
264 result = __get_PSR();
270 \brief Restore the Irq context
271 \details restore saved primask state.
272 \param [in] irq_state psr irq state.
274 __ALWAYS_INLINE void drv_irq_restore(uint32_t irq_state)
276 __set_PSR(irq_state);
284 #endif /* _CORE_H_ */