2 * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
8 * http://www.apache.org/licenses/LICENSE-2.0
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
16 /******************************************************************************
18 * @brief header file for setting system frequency.
21 ******************************************************************************/
22 #ifndef _CK_SYS_FREQ_H_
23 #define _CK_SYS_FREQ_H_
28 #define PMU_MCLK_SEL (CSKY_CLKGEN_BASE + 0x4)
29 #define MCLK_REG_VAL 0x8UL
31 #define PMU_CLK_STABLE (CSKY_CLKGEN_BASE + 0x18)
32 #define PMU_PLL_CTRL (CSKY_CLKGEN_BASE + 0x2c)
34 #define TRC_ADDR (CSKY_OTP_BASE + 0x20)
35 #define TRC_REG_VAL 0x1UL
37 #define EXTERNAL_CLK_SOURCE 0x8UL
38 #define EXTERNAL_CLK_16M (EXTERNAL_CLK_SOURCE * 2)
39 #define EXTERNAL_CLK_24M (EXTERNAL_CLK_SOURCE * 3)
40 #define EXTERNAL_CLK_32M (EXTERNAL_CLK_SOURCE * 4)
41 #define EXTERNAL_CLK_40M (EXTERNAL_CLK_SOURCE * 5)
42 #define EXTERNAL_CLK_48M (EXTERNAL_CLK_SOURCE * 6)
44 #define CLK_8M_REG_VAL 0xc0202UL
45 #define CLK_16M_REG_VAL 0xc0204UL
46 #define CLK_24M_REG_VAL 0xc0206UL
47 #define CLK_32M_REG_VAL 0xc0208UL
48 #define CLK_40M_REG_VAL 0xc020aUL
49 #define CLK_48M_REG_VAL 0xc020cUL
52 IHS_CLK = 0, //internal high speed clock
53 EHS_CLK = 1 //external high speed clock
65 void ck_set_sys_freq (clk_gen_t source, clk_val_t val);
67 #endif /* _CK_SYS_FREQ_H_ */