git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/T-HEAD_CB2201_CDK/csi/csi_driver/csky/hobbit3/include/pin_name.h

   1 /*
   2  * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
   3  *
   4  * Licensed under the Apache License, Version 2.0 (the "License");
   5  * you may not use this file except in compliance with the License.
   6  * You may obtain a copy of the License at
   7  *
   8  *   http://www.apache.org/licenses/LICENSE-2.0
   9  *
  10  * Unless required by applicable law or agreed to in writing, software
  11  * distributed under the License is distributed on an "AS IS" BASIS,
  12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  13  * See the License for the specific language governing permissions and
  14  * limitations under the License.
  15  */
  16
  17 /******************************************************************************
  18  * @file     pin_name.h
  19  * @brief    header file for the pin_name
  20  * @version  V1.0
  21  * @date     02. June 2017
  22  ******************************************************************************/
  23 #ifndef _PINNAMES_H
  24 #define _PINNAMES_H
  25
  26
  27 #ifdef __cplusplus
  28 extern "C" {
  29 #endif
  30
  31
  32 typedef enum {
  33         PA0_I2C0SCL_SPI1CS1_SPU0_UART1TX = 0,
  34         PA1_I2C0SDA_SPI1CS2_SPU1_UART1RX,
  35         PA2_QSPI0CLK_XX_XX_XX,
  36         PA3_QSPI0MISO_XX_XX_XX,
  37         PA4_QSPI0MOSI_XX_XX_XX,
  38         PA5_QSPI0HOLD_XX_XX_XX,
  39         PA6_QSPI0WP_XX_XX_XX,
  40         PA7_QSPI0CS0_XX_XX_XX,
  41         PA8_UART0TX_XX_SPU2_SIROUT0,
  42         PA9_UART0RX_XX_SPU3_SIRIN0,
  43         PA10_UART0CTS_USI0SCLK_SPU4_I2C0SCL,
  44         PA11_UART0RTS_USI0SD0_SPU5_I2C0SDA,
  45         PA12_XX_USI0SD1_XX_UART2RX,
  46         PA13_XX_USI0NSS_XX_UART2TX,
  47         PA14_SPI0CS2_FAULT_I2C1SDA_XX,
  48         PA15_SPI0CS1_XX_I2C1SCL_XX,
  49         PA16_SPI0CS0_PWMTRIG0_XX_USI1SCLK,
  50         PA17_SPI0MOSI_PWMTRIG1_XX_USI1SD0,
  51         PA18_SPI0MISO_XX_SPU6_USI1SD1,
  52         PA19_SPI0SCK_FAULT_SPU7_USI1NSS,
  53         PA20_UART1RX_PWM0_SPU8_SIRIN1,
  54         PA21_UART1TX_PWM1_SPU9_SIROUT1,
  55         PA22_UART1CTS_PWM2_SPU10_XX,
  56         PA23_UART1RTS_PWM3_SPU11_XX,
  57         PA24_USI1NSS_PWM4_SPU12_XX,
  58         PA25_USI1SD1_PWM5_SPU13_XX,
  59         PA26_USI1SD0_PWM6_SPU14_XX,
  60         PA27_USI1SCLK_PWM7_SPU15_XX,
  61         PA28_I2C1SCL_PWM8_SPU16_XX,
  62         PA29_I2C1SDA_PWM9_SPU17_XX,
  63         PA30_I2C0SDA_PWM10_SPU18_XX,
  64         PA31_I2C0SCL_PWM11_SPU19_XX,
  65         PB0_UART2TX_XX_XX_SIROUT2,
  66         PB1_UART2RX_XX_XX_SIRIN2,
  67         PB2_UART2RTS_XX_XX_XX,
  68         PB3_UART2CTS_XX_XX_XX,
  69         PB4_XX_XX_SPU20_UART3TX,
  70         PB5_QSPI1CS1_XX_SPU21_UART3RX,
  71         PB6_QSPI1WP_XX_SPU22_XX,
  72         PB7_QSPI1HOLD_XX_SPU23_XX,
  73         PB8_QSPI1CS0_PWMTRIG0_SPU24_XX,
  74         PB9_QSPI1MOSI_PWMTRIG1_SPU25_XX,
  75         PB10_QSPI1MISO_XX_SPU26_I2C1SDA,
  76         PB11_QSPI1CLK_XX_SPU27_I2C1SCL,
  77         PB12_UART3RX_SPI1CS0_SPU28_SIRIN3,
  78         PB13_UART3TX_SPI1MISO_SPU29_SIROUT3,
  79         PB14_UART3RTS_SPI1MOSI_SPU30_XX,
  80         PB15_UART3CTS_SPI1SCK_SPU31_XX,
  81 }
  82 pin_name_t;
  83
  84 typedef enum {
  85     PORTA = 0,
  86     PORTB = 1
  87 } port_name_t;
  88
  89 #ifdef __cplusplus
  90 }
  91 #endif
  92
  93 #endif