2 * FreeRTOS Kernel V10.0.0
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3 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software. If you wish to use our Amazon
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14 * FreeRTOS name, please do so in a fair use way that does not cause confusion.
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16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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18 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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19 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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20 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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23 * http://www.FreeRTOS.org
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24 * http://aws.amazon.com/freertos
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26 * 1 tab == 4 spaces!
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29 /* Scheduler includes. */
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30 #include "FreeRTOS.h"
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33 /* Demo includes. */
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34 #include "IntQueueTimer.h"
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35 #include "IntQueue.h"
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37 /* Xtensa includes. */
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38 #include <xtensa/corebits.h>
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39 #include <xtensa/config/system.h>
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40 #include <xtensa_api.h>
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41 #include <xtensa/hal.h>
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42 /*-----------------------------------------------------------*/
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44 /* Check if Timer1 is available. */
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45 #if XCHAL_TIMER1_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
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46 #if XCHAL_INT_LEVEL( XCHAL_TIMER1_INTERRUPT ) <= XCHAL_EXCM_LEVEL
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47 #define SECOND_TIMER_AVAILABLE 1
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51 #ifndef SECOND_TIMER_AVAILABLE
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52 #define SECOND_TIMER_AVAILABLE 0
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56 * Timer0 is used to drive systick and therefore we use Timer1
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57 * as second interrupt which runs on a higher priority than
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58 * Timer0. This ensures that systick will get interrupted by
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59 * this timer and hence we can test interrupt nesting.
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61 #define SECOND_TIMER_INDEX 1
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64 * Frequency of the second timer - This timer is configured at
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65 * a frequency offset of 17 from the systick timer.
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67 #define SECOND_TIMER_TICK_RATE_HZ ( configTICK_RATE_HZ + 17 )
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68 #define SECOND_TIMER_TICK_DIVISOR ( configCPU_CLOCK_HZ / SECOND_TIMER_TICK_RATE_HZ )
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69 /*-----------------------------------------------------------*/
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71 /* Defined in main_full.c. */
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72 extern BaseType_t xTimerForQueueTestInitialized;
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73 /*-----------------------------------------------------------*/
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76 * Interrupt handler for timer interrupt.
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78 #if( SECOND_TIMER_AVAILABLE == 1 )
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79 static void prvTimer2Handler( void *arg );
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80 #endif /* SECOND_TIMER_AVAILABLE */
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81 /*-----------------------------------------------------------*/
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83 void vInitialiseTimerForIntQueueTest( void )
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85 unsigned currentCycleCount, firstComparatorValue;
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87 /* Inform the tick hook function that it can access queues now. */
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88 xTimerForQueueTestInitialized = pdTRUE;
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90 #if( SECOND_TIMER_AVAILABLE == 1 )
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92 /* Install the interrupt handler for second timer. */
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93 xt_set_interrupt_handler( XCHAL_TIMER1_INTERRUPT, prvTimer2Handler, NULL );
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95 /* Read the current cycle count. */
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96 currentCycleCount = xthal_get_ccount();
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98 /* Calculate time of the first timer interrupt. */
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99 firstComparatorValue = currentCycleCount + SECOND_TIMER_TICK_DIVISOR;
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101 /* Set the comparator. */
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102 xthal_set_ccompare( SECOND_TIMER_INDEX, firstComparatorValue );
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104 /* Enable timer interrupt. */
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105 xt_ints_on( ( 1 << XCHAL_TIMER1_INTERRUPT ) );
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107 #endif /* SECOND_TIMER_AVAILABLE */
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109 /*-----------------------------------------------------------*/
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112 * Xtensa timers work by comparing a cycle counter with a preset value.
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113 * Once the match occurs an interrupt is generated, and the handler has
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114 * to set a new cycle count into the comparator. To avoid clock drift
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115 * due to interrupt latency, the new cycle count is computed from the
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116 * old, not the time the interrupt was serviced. However if a timer
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117 * interrupt is ever serviced more than one tick late, it is necessary
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118 * to process multiple ticks until the new cycle count is in the future,
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119 * otherwise the next timer interrupt would not occur until after the
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120 * cycle counter had wrapped (2^32 cycles later).
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124 old_ccompare = read_ccompare_i();
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125 write_ccompare_i( old_ccompare + divisor );
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127 diff = read_ccount() - old_ccompare;
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128 } while ( diff > divisor );
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130 #if( SECOND_TIMER_AVAILABLE == 1 )
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132 static void prvTimer2Handler( void *arg )
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134 unsigned oldComparatorValue, newComparatorValue, currentCycleCount;
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136 /* Unused arguments. */
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141 /* Read old comparator value. */
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142 oldComparatorValue = xthal_get_ccompare( SECOND_TIMER_INDEX );
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144 /* Calculate the new comparator value. */
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145 newComparatorValue = oldComparatorValue + SECOND_TIMER_TICK_DIVISOR;
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147 /* Update comparator and clear interrupt. */
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148 xthal_set_ccompare( SECOND_TIMER_INDEX, newComparatorValue );
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151 portYIELD_FROM_ISR( xSecondTimerHandler() );
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153 /* Ensure comparator update is complete. */
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154 xthal_icache_sync();
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156 /* Read current cycle count to check if we need to process more
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157 * ticks to catch up. */
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158 currentCycleCount = xthal_get_ccount();
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160 } while( ( currentCycleCount - oldComparatorValue ) > SECOND_TIMER_TICK_DIVISOR );
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163 #endif /* SECOND_TIMER_AVAILABLE */
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164 /*-----------------------------------------------------------*/
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