2 FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.
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4 FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
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5 http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 ***************************************************************************
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9 * FreeRTOS tutorial books are available in pdf and paperback. *
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10 * Complete, revised, and edited pdf reference manuals are also *
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13 * Purchasing FreeRTOS documentation will not only help you, by *
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14 * ensuring you get running as quickly as possible and with an *
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15 * in-depth knowledge of how to use FreeRTOS, it will also help *
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16 * the FreeRTOS project to continue with its mission of providing *
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17 * professional grade, cross platform, de facto standard solutions *
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18 * for microcontrollers - completely free of charge! *
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20 * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
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22 * Thank you for using FreeRTOS, and thank you for your support! *
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24 ***************************************************************************
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27 This file is part of the FreeRTOS distribution.
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29 FreeRTOS is free software; you can redistribute it and/or modify it under
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30 the terms of the GNU General Public License (version 2) as published by the
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31 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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33 >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
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34 distribute a combined work that includes FreeRTOS without being obliged to
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35 provide the source code for proprietary components outside of the FreeRTOS
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38 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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39 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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40 FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
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41 details. You should have received a copy of the GNU General Public License
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42 and the FreeRTOS license exception along with FreeRTOS; if not it can be
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43 viewed here: http://www.freertos.org/a00114.html and also obtained by
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44 writing to Real Time Engineers Ltd., contact details for whom are available
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45 on the FreeRTOS WEB site.
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49 ***************************************************************************
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51 * Having a problem? Start by reading the FAQ "My application does *
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52 * not run, what could be wrong?" *
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54 * http://www.FreeRTOS.org/FAQHelp.html *
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56 ***************************************************************************
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59 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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60 license and Real Time Engineers Ltd. contact details.
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62 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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63 including FreeRTOS+Trace - an indispensable productivity tool, and our new
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64 fully thread aware and reentrant UDP/IP stack.
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66 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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67 Integrity Systems, who sell the code with commercial support,
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68 indemnification and middleware, under the OpenRTOS brand.
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70 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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71 engineered and independently SIL3 certified version for use in safety and
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72 mission critical applications that require provable dependability.
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78 + Modified char* types to compile without warning when using GCC V4.0.1.
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79 + Corrected the address to which the MAC address is written. Thanks to
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80 Bill Knight for this correction.
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84 + Changed the default MAC address to something more realistic.
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88 /* Standard includes. */
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92 /* Scheduler include files. */
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93 #include "FreeRTOS.h"
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99 /* Application includes. */
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101 #include "html_pages.h"
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103 /*-----------------------------------------------------------*/
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105 /* Hardwired i2c address of the WIZNet device. */
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106 #define tcpDEVICE_ADDRESS ( ( unsigned char ) 0x00 )
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108 /* Constants used to configure the Tx and Rx buffer sizes within the WIZnet
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110 #define tcp8K_RX ( ( unsigned char ) 0x03 )
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111 #define tcp8K_TX ( ( unsigned char ) 0x03 )
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113 /* Constants used to generate the WIZnet internal buffer addresses. */
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114 #define tcpSINGLE_SOCKET_ADDR_MASK ( ( unsigned long ) 0x1fff )
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115 #define tcpSINGLE_SOCKET_ADDR_OFFSET ( ( unsigned long ) 0x4000 )
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117 /* Bit definitions of the commands that can be sent to the command register. */
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118 #define tcpRESET_CMD ( ( unsigned char ) 0x80 )
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119 #define tcpSYS_INIT_CMD ( ( unsigned char ) 0x01 )
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120 #define tcpSOCK_STREAM ( ( unsigned char ) 0x01 )
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121 #define tcpSOCK_INIT ( ( unsigned char ) 0x02 )
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122 #define tcpLISTEN_CMD ( ( unsigned char ) 0x08 )
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123 #define tcpRECEIVE_CMD ( ( unsigned char ) 0x40 )
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124 #define tcpDISCONNECT_CMD ( ( unsigned char ) 0x10 )
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125 #define tcpSEND_CMD ( ( unsigned char ) 0x20 )
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127 /* Constants required to handle the interrupts. */
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128 #define tcpCLEAR_EINT0 ( 1 )
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129 #define i2cCLEAR_ALL_INTERRUPTS ( ( unsigned char ) 0xff )
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130 #define i2cCHANNEL_0_ISR_ENABLE ( ( unsigned char ) 0x01 )
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131 #define i2cCHANNEL_0_ISR_DISABLE ( ( unsigned char ) 0x00 )
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132 #define tcpWAKE_ON_EINT0 ( 1 )
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133 #define tcpENABLE_EINT0_FUNCTION ( ( unsigned long ) 0x01 )
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134 #define tcpEINT0_VIC_CHANNEL_BIT ( ( unsigned long ) 0x4000 )
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135 #define tcpEINT0_VIC_CHANNEL ( ( unsigned long ) 14 )
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136 #define tcpEINT0_VIC_ENABLE ( ( unsigned long ) 0x0020 )
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138 /* Various delays used in the driver. */
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139 #define tcpRESET_DELAY ( ( portTickType ) 16 / portTICK_RATE_MS )
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140 #define tcpINIT_DELAY ( ( portTickType ) 500 / portTICK_RATE_MS )
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141 #define tcpLONG_DELAY ( ( portTickType ) 500 / portTICK_RATE_MS )
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142 #define tcpSHORT_DELAY ( ( portTickType ) 5 / portTICK_RATE_MS )
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143 #define tcpCONNECTION_WAIT_DELAY ( ( portTickType ) 100 / portTICK_RATE_MS )
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144 #define tcpNO_DELAY ( ( portTickType ) 0 )
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146 /* Length of the data to read for various register reads. */
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147 #define tcpSTATUS_READ_LEN ( ( unsigned long ) 1 )
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148 #define tcpSHADOW_READ_LEN ( ( unsigned long ) 1 )
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150 /* Register addresses within the WIZnet device. */
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151 #define tcpCOMMAND_REG ( ( unsigned short ) 0x0000 )
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152 #define tcpGATEWAY_ADDR_REG ( ( unsigned short ) 0x0080 )
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153 #define tcpSUBNET_MASK_REG ( ( unsigned short ) 0x0084 )
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154 #define tcpSOURCE_HA_REG ( ( unsigned short ) 0x0088 )
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155 #define tpcSOURCE_IP_REG ( ( unsigned short ) 0x008E )
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156 #define tpcSOCKET_OPT_REG ( ( unsigned short ) 0x00A1 )
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157 #define tcpSOURCE_PORT_REG ( ( unsigned short ) 0x00AE )
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158 #define tcpTX_WRITE_POINTER_REG ( ( unsigned short ) 0x0040 )
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159 #define tcpTX_READ_POINTER_REG ( ( unsigned short ) 0x0044 )
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160 #define tcpTX_ACK_POINTER_REG ( ( unsigned short ) 0x0018 )
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161 #define tcpTX_MEM_SIZE_REG ( ( unsigned short ) 0x0096 )
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162 #define tcpRX_MEM_SIZE_REG ( ( unsigned short ) 0x0095 )
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163 #define tcpINTERRUPT_STATUS_REG ( ( unsigned short ) 0x0004 )
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164 #define tcpTX_WRITE_SHADOW_REG ( ( unsigned short ) 0x01F0 )
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165 #define tcpTX_ACK_SHADOW_REG ( ( unsigned short ) 0x01E2 )
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166 #define tcpISR_MASK_REG ( ( unsigned short ) 0x0009 )
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167 #define tcpINTERRUPT_REG ( ( unsigned short ) 0x0008 )
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168 #define tcpSOCKET_STATE_REG ( ( unsigned short ) 0x00a0 )
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170 /* Constants required for hardware setup. */
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171 #define tcpRESET_ACTIVE_LOW ( ( unsigned long ) 0x20 )
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172 #define tcpRESET_ACTIVE_HIGH ( ( unsigned long ) 0x10 )
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174 /* Constants defining the source of the WIZnet ISR. */
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175 #define tcpISR_SYS_INIT ( ( unsigned char ) 0x01 )
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176 #define tcpISR_SOCKET_INIT ( ( unsigned char ) 0x02 )
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177 #define tcpISR_ESTABLISHED ( ( unsigned char ) 0x04 )
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178 #define tcpISR_CLOSED ( ( unsigned char ) 0x08 )
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179 #define tcpISR_TIMEOUT ( ( unsigned char ) 0x10 )
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180 #define tcpISR_TX_COMPLETE ( ( unsigned char ) 0x20 )
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181 #define tcpISR_RX_COMPLETE ( ( unsigned char ) 0x40 )
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183 /* Constants defining the socket status bits. */
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184 #define tcpSTATUS_ESTABLISHED ( ( unsigned char ) 0x06 )
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185 #define tcpSTATUS_LISTEN ( ( unsigned char ) 0x02 )
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187 /* Misc constants. */
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188 #define tcpNO_STATUS_BITS ( ( unsigned char ) 0x00 )
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189 #define i2cNO_ADDR_REQUIRED ( ( unsigned short ) 0x0000 )
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190 #define i2cNO_DATA_REQUIRED ( 0x0000 )
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191 #define tcpISR_QUEUE_LENGTH ( ( unsigned portBASE_TYPE ) 10 )
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192 #define tcpISR_QUEUE_ITEM_SIZE ( ( unsigned portBASE_TYPE ) 0 )
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193 #define tcpBUFFER_LEN ( 4 * 1024 )
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194 #define tcpMAX_REGISTER_LEN ( 4 )
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195 #define tcpMAX_ATTEMPTS_TO_CHECK_BUFFER ( 6 )
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196 #define tcpMAX_NON_LISTEN_STAUS_READS ( 5 )
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198 /* Message definitions. The IP address, MAC address, gateway address, etc.
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200 const unsigned char const ucDataGAR[] = { 172, 25, 218, 3 }; /* Gateway address. */
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201 const unsigned char const ucDataMSR[] = { 255, 255, 255, 0 }; /* Subnet mask. */
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202 const unsigned char const ucDataSIPR[] = { 172, 25, 218, 201 };/* IP address. */
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203 const unsigned char const ucDataSHAR[] = { 00, 23, 30, 41, 15, 26 }; /* MAC address - DO NOT USE THIS ON A PUBLIC NETWORK! */
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205 /* Other fixed messages. */
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206 const unsigned char const ucDataReset[] = { tcpRESET_CMD };
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207 const unsigned char const ucDataInit[] = { tcpSYS_INIT_CMD };
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208 const unsigned char const ucDataProtocol[] = { tcpSOCK_STREAM };
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209 const unsigned char const ucDataPort[] = { 0xBA, 0xCC };
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210 const unsigned char const ucDataSockInit[] = { tcpSOCK_INIT };
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211 const unsigned char const ucDataTxWritePointer[] = { 0x11, 0x22, 0x00, 0x00 };
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212 const unsigned char const ucDataTxAckPointer[] = { 0x11, 0x22, 0x00, 0x00 };
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213 const unsigned char const ucDataTxReadPointer[] = { 0x11, 0x22, 0x00, 0x00 };
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214 const unsigned char const ucDataListen[] = { tcpLISTEN_CMD };
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215 const unsigned char const ucDataReceiveCmd[] = { tcpRECEIVE_CMD };
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216 const unsigned char const ucDataSetTxBufSize[] = { tcp8K_TX };
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217 const unsigned char const ucDataSetRxBufSize[] = { tcp8K_RX };
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218 const unsigned char const ucDataSend[] = { tcpSEND_CMD };
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219 const unsigned char const ucDataDisconnect[] = { tcpDISCONNECT_CMD };
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220 const unsigned char const ucDataEnableISR[] = { i2cCHANNEL_0_ISR_ENABLE };
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221 const unsigned char const ucDataDisableISR[] = { i2cCHANNEL_0_ISR_DISABLE };
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222 const unsigned char const ucDataClearInterrupt[] = { i2cCLEAR_ALL_INTERRUPTS };
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224 static xSemaphoreHandle xMessageComplete = NULL;
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225 xQueueHandle xTCPISRQueue = NULL;
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227 /* Dynamically generate and send an html page. */
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228 static void prvSendSamplePage( void );
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230 /* Read a register from the WIZnet device via the i2c interface. */
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231 static void prvReadRegister( unsigned char *pucDestination, unsigned short usAddress, unsigned long ulLength );
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233 /* Send the entire Tx buffer (the Tx buffer within the WIZnet device). */
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234 static void prvFlushBuffer( unsigned long ulTxAddress );
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236 /* Write a string to the WIZnet Tx buffer. */
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237 static void prvWriteString( const char * const pucTxBuffer, long lTxLen, unsigned long *pulTxAddress );
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239 /* Convert a number to a string. */
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240 void ultoa( unsigned long ulVal, char *pcBuffer, long lIgnore );
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242 /*-----------------------------------------------------------*/
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244 void ultoa( unsigned long ulVal, char *pcBuffer, long lIgnore )
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246 unsigned long lNibble;
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249 /* Simple routine to convert an unsigned long value into a string in hex
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252 /* For each nibble in the number we are converting. */
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253 for( lIndex = 0; lIndex < ( sizeof( ulVal ) * 2 ); lIndex++ )
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255 /* Take the top four bits of the number. */
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256 lNibble = ( ulVal >> 28 );
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258 /* We are converting it to a hex string, so is the number in the range
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262 pcBuffer[ lIndex ] = '0' + lNibble;
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267 pcBuffer[ lIndex ] = 'A' + lNibble;
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270 /* Shift off the top nibble so we use the next nibble next time around. */
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274 /* Mark the end of the string with a null terminator. */
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275 pcBuffer[ lIndex ] = 0x00;
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277 /*-----------------------------------------------------------*/
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279 static void prvReadRegister( unsigned char *pucDestination, unsigned short usAddress, unsigned long ulLength )
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281 unsigned char ucRxBuffer[ tcpMAX_REGISTER_LEN ];
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283 /* Read a register value from the WIZnet device. */
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285 /* First write out the address of the register we want to read. */
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286 i2cMessage( ucRxBuffer, i2cNO_DATA_REQUIRED, tcpDEVICE_ADDRESS, usAddress, i2cWRITE, NULL, portMAX_DELAY );
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288 /* Then read back from that address. */
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289 i2cMessage( ( unsigned char * ) pucDestination, ulLength, tcpDEVICE_ADDRESS, i2cNO_ADDR_REQUIRED, i2cREAD, xMessageComplete, portMAX_DELAY );
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291 /* I2C messages are queued so use the semaphore to wait for the read to
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292 complete - otherwise we will leave this function before the I2C
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293 transactions have completed. */
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294 xSemaphoreTake( xMessageComplete, tcpLONG_DELAY );
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296 /*-----------------------------------------------------------*/
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298 void vTCPHardReset( void )
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300 /* Physical reset of the WIZnet device by using the GPIO lines to hold the
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301 WIZnet reset lines active for a few milliseconds. */
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303 /* Make sure the interrupt from the WIZnet is disabled. */
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304 VICIntEnClear |= tcpEINT0_VIC_CHANNEL_BIT;
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306 /* If xMessageComplete is NULL then this is the first time that this
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307 function has been called and the queue and semaphore used in this file
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308 have not yet been created. */
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309 if( xMessageComplete == NULL )
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311 /* Create and obtain the semaphore used when we want to wait for an i2c
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312 message to be completed. */
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313 vSemaphoreCreateBinary( xMessageComplete );
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314 xSemaphoreTake( xMessageComplete, tcpNO_DELAY );
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316 /* Create the queue used to communicate between the WIZnet and TCP tasks. */
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317 xTCPISRQueue = xQueueCreate( tcpISR_QUEUE_LENGTH, tcpISR_QUEUE_ITEM_SIZE );
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320 /* Use the GPIO to reset the network hardware. */
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321 GPIO_IOCLR = tcpRESET_ACTIVE_LOW;
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322 GPIO_IOSET = tcpRESET_ACTIVE_HIGH;
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324 /* Delay with the network hardware in reset for a short while. */
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325 vTaskDelay( tcpRESET_DELAY );
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327 GPIO_IOCLR = tcpRESET_ACTIVE_HIGH;
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328 GPIO_IOSET = tcpRESET_ACTIVE_LOW;
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330 vTaskDelay( tcpINIT_DELAY );
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332 /* Setup the EINT0 to interrupt on required events from the WIZnet device.
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333 First enable the EINT0 function of the pin. */
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334 PCB_PINSEL1 |= tcpENABLE_EINT0_FUNCTION;
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336 /* We want the TCP comms to wake us from power save. */
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337 SCB_EXTWAKE = tcpWAKE_ON_EINT0;
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339 /* Install the ISR into the VIC - but don't enable it yet! */
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340 portENTER_CRITICAL();
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342 extern void ( vEINT0_ISR_Wrapper )( void );
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344 VICIntSelect &= ~( tcpEINT0_VIC_CHANNEL_BIT );
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345 VICVectAddr3 = ( long ) vEINT0_ISR_Wrapper;
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347 VICVectCntl3 = tcpEINT0_VIC_CHANNEL | tcpEINT0_VIC_ENABLE;
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349 portEXIT_CRITICAL();
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351 /* Enable interrupts in the WIZnet itself. */
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352 i2cMessage( ucDataEnableISR, sizeof( ucDataEnableISR ), tcpDEVICE_ADDRESS, tcpISR_MASK_REG, i2cWRITE, NULL, portMAX_DELAY );
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354 vTaskDelay( tcpLONG_DELAY );
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356 /*-----------------------------------------------------------*/
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358 long lTCPSoftReset( void )
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360 unsigned char ucStatus;
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361 extern volatile long lTransactionCompleted;
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363 /* Send a message to the WIZnet device to tell it set all it's registers
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364 back to their default states. Then setup the WIZnet device as required. */
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366 /* Reset the internal WIZnet registers. */
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367 i2cMessage( ucDataReset, sizeof( ucDataReset ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
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369 /* Now we can configure the protocol. Here the MAC address, gateway
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370 address, subnet mask and IP address are configured. */
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371 i2cMessage( ucDataSHAR, sizeof( ucDataSHAR ), tcpDEVICE_ADDRESS, tcpSOURCE_HA_REG, i2cWRITE, NULL, portMAX_DELAY );
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372 i2cMessage( ucDataGAR, sizeof( ucDataGAR ), tcpDEVICE_ADDRESS, tcpGATEWAY_ADDR_REG, i2cWRITE, NULL, portMAX_DELAY );
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373 i2cMessage( ucDataMSR, sizeof( ucDataMSR ), tcpDEVICE_ADDRESS, tcpSUBNET_MASK_REG, i2cWRITE, NULL, portMAX_DELAY );
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374 i2cMessage( ucDataSIPR, sizeof( ucDataSIPR ), tcpDEVICE_ADDRESS, tpcSOURCE_IP_REG, i2cWRITE, NULL, portMAX_DELAY );
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376 /* Next the memory buffers are configured to give all the WIZnet internal
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377 memory over to a single socket. This gives the socket the maximum internal
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378 Tx and Rx buffer space. */
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379 i2cMessage( ucDataSetTxBufSize, sizeof( ucDataSetTxBufSize ), tcpDEVICE_ADDRESS, tcpTX_MEM_SIZE_REG, i2cWRITE, NULL, portMAX_DELAY );
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380 i2cMessage( ucDataSetRxBufSize, sizeof( ucDataSetRxBufSize ), tcpDEVICE_ADDRESS, tcpRX_MEM_SIZE_REG, i2cWRITE, NULL, portMAX_DELAY );
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382 /* Send the sys init command so the above parameters take effect. */
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383 i2cMessage( ucDataInit, sizeof( ucDataInit ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
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385 /* Seems to like a little wait here. */
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386 vTaskDelay( tcpINIT_DELAY );
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388 /* Read back the status to ensure the system initialised ok. */
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389 prvReadRegister( &ucStatus, tcpINTERRUPT_STATUS_REG, tcpSTATUS_READ_LEN );
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391 /* We should find that the sys init was successful. */
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392 if( ucStatus != tcpISR_SYS_INIT )
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394 return ( long ) pdFAIL;
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397 /* No i2c errors yet. */
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398 portENTER_CRITICAL();
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399 lTransactionCompleted = pdTRUE;
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400 portEXIT_CRITICAL();
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402 return ( long ) pdPASS;
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404 /*-----------------------------------------------------------*/
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406 long lTCPCreateSocket( void )
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408 unsigned char ucStatus;
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410 /* Create and configure a socket. */
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412 /* Setup and init the socket. Here the port number is set and the socket
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414 i2cMessage( ucDataProtocol, sizeof( ucDataProtocol),tcpDEVICE_ADDRESS, tpcSOCKET_OPT_REG, i2cWRITE, NULL, portMAX_DELAY );
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415 i2cMessage( ucDataPort, sizeof( ucDataPort), tcpDEVICE_ADDRESS, tcpSOURCE_PORT_REG, i2cWRITE, NULL, portMAX_DELAY );
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416 i2cMessage( ucDataSockInit, sizeof( ucDataSockInit),tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, xMessageComplete, portMAX_DELAY );
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418 /* Wait for the Init command to be sent. */
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419 if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) )
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421 /* For some reason the message was not transmitted within our block
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423 return ( long ) pdFAIL;
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426 /* Allow the socket to initialise. */
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427 vTaskDelay( tcpINIT_DELAY );
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429 /* Read back the status to ensure the socket initialised ok. */
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430 prvReadRegister( &ucStatus, tcpINTERRUPT_STATUS_REG, tcpSTATUS_READ_LEN );
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432 /* We should find that the socket init was successful. */
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433 if( ucStatus != tcpISR_SOCKET_INIT )
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435 return ( long ) pdFAIL;
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439 /* Setup the Tx pointer registers to indicate that the Tx buffer is empty. */
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440 i2cMessage( ucDataTxReadPointer, sizeof( ucDataTxReadPointer ), tcpDEVICE_ADDRESS, tcpTX_READ_POINTER_REG, i2cWRITE, NULL, portMAX_DELAY );
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441 vTaskDelay( tcpSHORT_DELAY );
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442 i2cMessage( ucDataTxWritePointer, sizeof( ucDataTxWritePointer ), tcpDEVICE_ADDRESS, tcpTX_WRITE_POINTER_REG, i2cWRITE, NULL, portMAX_DELAY );
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443 vTaskDelay( tcpSHORT_DELAY );
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444 i2cMessage( ucDataTxAckPointer, sizeof( ucDataTxAckPointer ), tcpDEVICE_ADDRESS, tcpTX_ACK_POINTER_REG, i2cWRITE, NULL, portMAX_DELAY );
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445 vTaskDelay( tcpSHORT_DELAY );
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447 return ( long ) pdPASS;
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449 /*-----------------------------------------------------------*/
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451 void vTCPListen( void )
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453 unsigned char ucISR;
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455 /* Start a passive listen on the socket. */
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457 /* Enable interrupts in the WizNet device after ensuring none are
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458 currently pending. */
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459 while( SCB_EXTINT & tcpCLEAR_EINT0 )
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461 /* The WIZnet device is still asserting and interrupt so tell it to
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463 i2cMessage( ucDataClearInterrupt, sizeof( ucDataClearInterrupt ), tcpDEVICE_ADDRESS, tcpINTERRUPT_REG, i2cWRITE, xMessageComplete, portMAX_DELAY );
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464 xSemaphoreTake( xMessageComplete, tcpLONG_DELAY );
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467 SCB_EXTINT = tcpCLEAR_EINT0;
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470 while( xQueueReceive( xTCPISRQueue, &ucISR, tcpNO_DELAY ) )
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472 /* Just clearing the queue used by the ISR routine to tell this task
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473 that the WIZnet device needs attention. */
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476 /* Now all the pending interrupts have been cleared we can enable the
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477 processor interrupts. */
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478 VICIntEnable |= tcpEINT0_VIC_CHANNEL_BIT;
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480 /* Then start listening for incoming connections. */
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481 i2cMessage( ucDataListen, sizeof( ucDataListen ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
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483 /*-----------------------------------------------------------*/
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485 long lProcessConnection( void )
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487 unsigned char ucISR, ucState, ucLastState = 2, ucShadow;
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488 extern volatile long lTransactionCompleted;
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489 long lSameStateCount = 0, lDataSent = pdFALSE;
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490 unsigned long ulWritePointer, ulAckPointer;
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492 /* No I2C errors can yet have occurred. */
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493 portENTER_CRITICAL();
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494 lTransactionCompleted = pdTRUE;
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495 portEXIT_CRITICAL();
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497 /* Keep looping - processing interrupts, until we have completed a
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498 transaction. This uses the WIZnet in it's simplest form. The socket
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499 accepts a connection - we process the connection - then close the socket.
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500 We then go back to reinitialise everything and start again. */
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501 while( lTransactionCompleted == pdTRUE )
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503 /* Wait for a message on the queue from the WIZnet ISR. When the
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504 WIZnet device asserts an interrupt the ISR simply posts a message
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505 onto this queue to wake this task. */
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506 if( xQueueReceive( xTCPISRQueue, &ucISR, tcpCONNECTION_WAIT_DELAY ) )
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508 /* The ISR posted a message on this queue to tell us that the
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509 WIZnet device asserted an interrupt. The ISR cannot process
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510 an I2C message so cannot tell us what caused the interrupt so
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511 we have to query the device here. This task is the highest
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512 priority in the system so will run immediately following the ISR. */
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513 prvReadRegister( &ucISR, tcpINTERRUPT_STATUS_REG, tcpSTATUS_READ_LEN );
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515 /* Once we have read what caused the ISR we can clear the interrupt
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517 i2cMessage( ucDataClearInterrupt, sizeof( ucDataClearInterrupt ), tcpDEVICE_ADDRESS, tcpINTERRUPT_REG, i2cWRITE, NULL, portMAX_DELAY );
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519 /* Now we can clear the processor interrupt and re-enable ready for
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521 SCB_EXTINT = tcpCLEAR_EINT0;
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522 VICIntEnable |= tcpEINT0_VIC_CHANNEL_BIT;
\r
524 /* Process the interrupt ... */
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526 if( ucISR & tcpISR_ESTABLISHED )
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528 /* A connection has been established - respond by sending
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529 a receive command. */
\r
530 i2cMessage( ucDataReceiveCmd, sizeof( ucDataReceiveCmd ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
\r
533 if( ucISR & tcpISR_RX_COMPLETE )
\r
535 /* We message has been received. This will be an HTTP get
\r
536 command. We only have one page to send so just send it without
\r
537 regard to what the actual requested page was. */
\r
538 prvSendSamplePage();
\r
541 if( ucISR & tcpISR_TX_COMPLETE )
\r
543 /* We have a TX complete interrupt - which oddly does not
\r
544 indicate that the message being sent is complete so we cannot
\r
545 yet close the socket. Instead we read the position of the Tx
\r
546 pointer within the WIZnet device so we know how much data it
\r
547 has to send. Later we will read the ack pointer and compare
\r
548 this to the Tx pointer to ascertain whether the transmission
\r
551 /* First read the shadow register. */
\r
552 prvReadRegister( &ucShadow, tcpTX_WRITE_SHADOW_REG, tcpSHADOW_READ_LEN );
\r
554 /* Now a short delay is required. */
\r
555 vTaskDelay( tcpSHORT_DELAY );
\r
557 /* Then we can read the real register. */
\r
558 prvReadRegister( ( unsigned char * ) &ulWritePointer, tcpTX_WRITE_POINTER_REG, sizeof( ulWritePointer ) );
\r
560 /* We cannot do anything more here but need to remember that
\r
561 this interrupt has occurred. */
\r
562 lDataSent = pdTRUE;
\r
565 if( ucISR & tcpISR_CLOSED )
\r
567 /* The socket has been closed so we can leave this function. */
\r
568 lTransactionCompleted = pdFALSE;
\r
573 /* We have not received an interrupt from the WIZnet device for a
\r
574 while. Read the socket status and check that everything is as
\r
576 prvReadRegister( &ucState, tcpSOCKET_STATE_REG, tcpSTATUS_READ_LEN );
\r
578 if( ( ucState == tcpSTATUS_ESTABLISHED ) && ( lDataSent > 0 ) )
\r
580 /* The socket is established and we have already received a Tx
\r
581 end interrupt. We must therefore be waiting for the Tx buffer
\r
582 inside the WIZnet device to be empty before we can close the
\r
585 Read the Ack pointer register to see if it has caught up with
\r
586 the Tx pointer register. First we have to read the shadow
\r
588 prvReadRegister( &ucShadow, tcpTX_ACK_SHADOW_REG, tcpSHADOW_READ_LEN );
\r
589 vTaskDelay( tcpSHORT_DELAY );
\r
590 prvReadRegister( ( unsigned char * ) &ulAckPointer, tcpTX_ACK_POINTER_REG, sizeof( ulWritePointer ) );
\r
592 if( ulAckPointer == ulWritePointer )
\r
594 /* The Ack and write pointer are now equal and we can
\r
595 safely close the socket. */
\r
596 i2cMessage( ucDataDisconnect, sizeof( ucDataDisconnect ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
\r
600 /* Keep a count of how many times we encounter the Tx
\r
601 buffer still containing data. */
\r
603 if( lDataSent > tcpMAX_ATTEMPTS_TO_CHECK_BUFFER )
\r
605 /* Assume we cannot complete sending the data and
\r
606 therefore cannot safely close the socket. Start over. */
\r
608 lTransactionCompleted = pdFALSE;
\r
612 else if( ucState != tcpSTATUS_LISTEN )
\r
614 /* If we have not yet received a Tx end interrupt we would only
\r
615 ever expect to find the socket still listening for any
\r
616 sustained period. */
\r
617 if( ucState == ucLastState )
\r
620 if( lSameStateCount > tcpMAX_NON_LISTEN_STAUS_READS )
\r
622 /* We are persistently in an unexpected state. Assume
\r
623 we cannot safely close the socket and start over. */
\r
625 lTransactionCompleted = pdFALSE;
\r
631 /* We are in the listen state so are happy that everything
\r
633 lSameStateCount = 0;
\r
636 /* Remember what state we are in this time around so we can check
\r
637 for a persistence on an unexpected state. */
\r
638 ucLastState = ucState;
\r
642 /* We are going to reinitialise the WIZnet device so do not want our
\r
643 interrupts from the WIZnet to be processed. */
\r
644 VICIntEnClear |= tcpEINT0_VIC_CHANNEL_BIT;
\r
645 return lTransactionCompleted;
\r
647 /*-----------------------------------------------------------*/
\r
649 static void prvWriteString( const char * const pucTxBuffer, long lTxLen, unsigned long *pulTxAddress )
\r
651 unsigned long ulSendAddress;
\r
653 /* Send a string to the Tx buffer internal to the WIZnet device. */
\r
655 /* Calculate the address to which we are going to write in the buffer. */
\r
656 ulSendAddress = ( *pulTxAddress & tcpSINGLE_SOCKET_ADDR_MASK ) + tcpSINGLE_SOCKET_ADDR_OFFSET;
\r
658 /* Send the buffer to the calculated address. Use the semaphore so we
\r
659 can wait until the entire message has been transferred. */
\r
660 i2cMessage( ( unsigned char * ) pucTxBuffer, lTxLen, tcpDEVICE_ADDRESS, ( unsigned short ) ulSendAddress, i2cWRITE, xMessageComplete, portMAX_DELAY );
\r
662 /* Wait until the semaphore indicates that the message has been transferred. */
\r
663 if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) )
\r
668 /* Return the new address of the end of the buffer (within the WIZnet
\r
670 *pulTxAddress += ( unsigned long ) lTxLen;
\r
672 /*-----------------------------------------------------------*/
\r
674 static void prvFlushBuffer( unsigned long ulTxAddress )
\r
676 unsigned char ucTxBuffer[ tcpMAX_REGISTER_LEN ];
\r
678 /* We have written some data to the Tx buffer internal to the WIZnet
\r
679 device. Now we update the Tx pointer inside the WIZnet then send a
\r
680 Send command - which causes the data up to the new Tx pointer to be
\r
683 /* Make sure endieness is correct for transmission. */
\r
684 ulTxAddress = htonl( ulTxAddress );
\r
686 /* Place the new Tx pointer in the string to be transmitted. */
\r
687 ucTxBuffer[ 0 ] = ( unsigned char ) ( ulTxAddress & 0xff );
\r
689 ucTxBuffer[ 1 ] = ( unsigned char ) ( ulTxAddress & 0xff );
\r
691 ucTxBuffer[ 2 ] = ( unsigned char ) ( ulTxAddress & 0xff );
\r
693 ucTxBuffer[ 3 ] = ( unsigned char ) ( ulTxAddress & 0xff );
\r
696 /* And send it to the WIZnet device. */
\r
697 i2cMessage( ucTxBuffer, sizeof( ulTxAddress ), tcpDEVICE_ADDRESS, tcpTX_WRITE_POINTER_REG, i2cWRITE, xMessageComplete, portMAX_DELAY );
\r
699 if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) )
\r
704 vTaskDelay( tcpSHORT_DELAY );
\r
707 i2cMessage( ucDataSend, sizeof( ucDataSend ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, xMessageComplete, portMAX_DELAY );
\r
709 if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) )
\r
714 /*-----------------------------------------------------------*/
\r
716 static void prvSendSamplePage( void )
\r
718 extern long lErrorInTask;
\r
719 unsigned long ulTxAddress;
\r
720 unsigned char ucShadow;
\r
722 static unsigned long ulRefreshCount = 0x00;
\r
723 static char cPageBuffer[ tcpBUFFER_LEN ];
\r
726 /* This function just generates a sample page of HTML which gets
\r
727 sent each time a client attaches to the socket. The page is created
\r
728 from two fixed strings (cSamplePageFirstPart and cSamplePageSecondPart)
\r
729 with a bit of dynamically generated data in the middle. */
\r
731 /* We need to know the address to which the html string should be sent
\r
732 in the WIZnet Tx buffer. First read the shadow register. */
\r
733 prvReadRegister( &ucShadow, tcpTX_WRITE_SHADOW_REG, tcpSHADOW_READ_LEN );
\r
735 /* Now a short delay is required. */
\r
736 vTaskDelay( tcpSHORT_DELAY );
\r
738 /* Now we can read the real pointer value. */
\r
739 prvReadRegister( ( unsigned char * ) &ulTxAddress, tcpTX_WRITE_POINTER_REG, sizeof( ulTxAddress ) );
\r
741 /* Make sure endieness is correct. */
\r
742 ulTxAddress = htonl( ulTxAddress );
\r
744 /* Send the start of the page. */
\r
745 prvWriteString( cSamplePageFirstPart, strlen( cSamplePageFirstPart ), &ulTxAddress );
\r
747 /* Generate a bit of dynamic data and place it in the buffer ready to be
\r
749 strcpy( cPageBuffer, "<BR>Number of ticks since boot = 0x" );
\r
750 lIndex = strlen( cPageBuffer );
\r
751 ultoa( xTaskGetTickCount(), &( cPageBuffer[ lIndex ] ), 0 );
\r
752 strcat( cPageBuffer, "<br>Number of tasks executing = ");
\r
753 lIndex = strlen( cPageBuffer );
\r
754 ultoa( ( unsigned long ) uxTaskGetNumberOfTasks(), &( cPageBuffer[ lIndex ] ), 0 );
\r
755 strcat( cPageBuffer, "<br>IO port 0 state (used by flash tasks) = 0x" );
\r
756 lIndex = strlen( cPageBuffer );
\r
757 ultoa( ( unsigned long ) GPIO0_IOPIN, &( cPageBuffer[ lIndex ] ), 0 );
\r
758 strcat( cPageBuffer, "<br>Refresh = 0x" );
\r
759 lIndex = strlen( cPageBuffer );
\r
760 ultoa( ( unsigned long ) ulRefreshCount, &( cPageBuffer[ lIndex ] ), 0 );
\r
764 strcat( cPageBuffer, "<p>An error has occurred in at least one task." );
\r
768 strcat( cPageBuffer, "<p>All tasks executing without error." );
\r
773 /* Send the dynamically generated string. */
\r
774 prvWriteString( cPageBuffer, strlen( cPageBuffer ), &ulTxAddress );
\r
776 /* Finish the page. */
\r
777 prvWriteString( cSamplePageSecondPart, strlen( cSamplePageSecondPart ), &ulTxAddress );
\r
779 /* Tell the WIZnet to send the data we have just written to its Tx buffer. */
\r
780 prvFlushBuffer( ulTxAddress );
\r
projects / freertos / blob