2 FreeRTOS V7.3.0 - Copyright (C) 2012 Real Time Engineers Ltd.
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4 FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
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5 http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 ***************************************************************************
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9 * FreeRTOS tutorial books are available in pdf and paperback. *
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10 * Complete, revised, and edited pdf reference manuals are also *
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13 * Purchasing FreeRTOS documentation will not only help you, by *
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14 * ensuring you get running as quickly as possible and with an *
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15 * in-depth knowledge of how to use FreeRTOS, it will also help *
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16 * the FreeRTOS project to continue with its mission of providing *
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17 * professional grade, cross platform, de facto standard solutions *
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18 * for microcontrollers - completely free of charge! *
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20 * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
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22 * Thank you for using FreeRTOS, and thank you for your support! *
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24 ***************************************************************************
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27 This file is part of the FreeRTOS distribution.
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29 FreeRTOS is free software; you can redistribute it and/or modify it under
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30 the terms of the GNU General Public License (version 2) as published by the
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31 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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32 >>>NOTE<<< The modification to the GPL is included to allow you to
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33 distribute a combined work that includes FreeRTOS without being obliged to
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34 provide the source code for proprietary components outside of the FreeRTOS
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35 kernel. FreeRTOS is distributed in the hope that it will be useful, but
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36 WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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37 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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38 more details. You should have received a copy of the GNU General Public
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39 License and the FreeRTOS license exception along with FreeRTOS; if not it
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40 can be viewed here: http://www.freertos.org/a00114.html and also obtained
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41 by writing to Richard Barry, contact details for whom are available on the
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46 ***************************************************************************
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48 * Having a problem? Start by reading the FAQ "My application does *
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49 * not run, what could be wrong?" *
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51 * http://www.FreeRTOS.org/FAQHelp.html *
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53 ***************************************************************************
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56 http://www.FreeRTOS.org - Documentation, training, latest versions, license
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57 and contact details.
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59 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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60 including FreeRTOS+Trace - an indispensable productivity tool.
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62 Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
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63 the code with commercial support, indemnification, and middleware, under
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64 the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
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65 provide a safety engineered and independently SIL3 certified version under
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66 the SafeRTOS brand: http://www.SafeRTOS.com.
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72 + Modified char* types to compile without warning when using GCC V4.0.1.
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73 + Corrected the address to which the MAC address is written. Thanks to
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74 Bill Knight for this correction.
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78 + Changed the default MAC address to something more realistic.
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82 /* Standard includes. */
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86 /* Scheduler include files. */
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87 #include "FreeRTOS.h"
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93 /* Application includes. */
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95 #include "html_pages.h"
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97 /*-----------------------------------------------------------*/
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99 /* Hardwired i2c address of the WIZNet device. */
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100 #define tcpDEVICE_ADDRESS ( ( unsigned char ) 0x00 )
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102 /* Constants used to configure the Tx and Rx buffer sizes within the WIZnet
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104 #define tcp8K_RX ( ( unsigned char ) 0x03 )
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105 #define tcp8K_TX ( ( unsigned char ) 0x03 )
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107 /* Constants used to generate the WIZnet internal buffer addresses. */
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108 #define tcpSINGLE_SOCKET_ADDR_MASK ( ( unsigned long ) 0x1fff )
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109 #define tcpSINGLE_SOCKET_ADDR_OFFSET ( ( unsigned long ) 0x4000 )
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111 /* Bit definitions of the commands that can be sent to the command register. */
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112 #define tcpRESET_CMD ( ( unsigned char ) 0x80 )
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113 #define tcpSYS_INIT_CMD ( ( unsigned char ) 0x01 )
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114 #define tcpSOCK_STREAM ( ( unsigned char ) 0x01 )
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115 #define tcpSOCK_INIT ( ( unsigned char ) 0x02 )
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116 #define tcpLISTEN_CMD ( ( unsigned char ) 0x08 )
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117 #define tcpRECEIVE_CMD ( ( unsigned char ) 0x40 )
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118 #define tcpDISCONNECT_CMD ( ( unsigned char ) 0x10 )
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119 #define tcpSEND_CMD ( ( unsigned char ) 0x20 )
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121 /* Constants required to handle the interrupts. */
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122 #define tcpCLEAR_EINT0 ( 1 )
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123 #define i2cCLEAR_ALL_INTERRUPTS ( ( unsigned char ) 0xff )
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124 #define i2cCHANNEL_0_ISR_ENABLE ( ( unsigned char ) 0x01 )
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125 #define i2cCHANNEL_0_ISR_DISABLE ( ( unsigned char ) 0x00 )
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126 #define tcpWAKE_ON_EINT0 ( 1 )
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127 #define tcpENABLE_EINT0_FUNCTION ( ( unsigned long ) 0x01 )
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128 #define tcpEINT0_VIC_CHANNEL_BIT ( ( unsigned long ) 0x4000 )
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129 #define tcpEINT0_VIC_CHANNEL ( ( unsigned long ) 14 )
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130 #define tcpEINT0_VIC_ENABLE ( ( unsigned long ) 0x0020 )
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132 /* Various delays used in the driver. */
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133 #define tcpRESET_DELAY ( ( portTickType ) 16 / portTICK_RATE_MS )
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134 #define tcpINIT_DELAY ( ( portTickType ) 500 / portTICK_RATE_MS )
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135 #define tcpLONG_DELAY ( ( portTickType ) 500 / portTICK_RATE_MS )
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136 #define tcpSHORT_DELAY ( ( portTickType ) 5 / portTICK_RATE_MS )
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137 #define tcpCONNECTION_WAIT_DELAY ( ( portTickType ) 100 / portTICK_RATE_MS )
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138 #define tcpNO_DELAY ( ( portTickType ) 0 )
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140 /* Length of the data to read for various register reads. */
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141 #define tcpSTATUS_READ_LEN ( ( unsigned long ) 1 )
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142 #define tcpSHADOW_READ_LEN ( ( unsigned long ) 1 )
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144 /* Register addresses within the WIZnet device. */
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145 #define tcpCOMMAND_REG ( ( unsigned short ) 0x0000 )
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146 #define tcpGATEWAY_ADDR_REG ( ( unsigned short ) 0x0080 )
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147 #define tcpSUBNET_MASK_REG ( ( unsigned short ) 0x0084 )
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148 #define tcpSOURCE_HA_REG ( ( unsigned short ) 0x0088 )
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149 #define tpcSOURCE_IP_REG ( ( unsigned short ) 0x008E )
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150 #define tpcSOCKET_OPT_REG ( ( unsigned short ) 0x00A1 )
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151 #define tcpSOURCE_PORT_REG ( ( unsigned short ) 0x00AE )
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152 #define tcpTX_WRITE_POINTER_REG ( ( unsigned short ) 0x0040 )
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153 #define tcpTX_READ_POINTER_REG ( ( unsigned short ) 0x0044 )
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154 #define tcpTX_ACK_POINTER_REG ( ( unsigned short ) 0x0018 )
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155 #define tcpTX_MEM_SIZE_REG ( ( unsigned short ) 0x0096 )
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156 #define tcpRX_MEM_SIZE_REG ( ( unsigned short ) 0x0095 )
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157 #define tcpINTERRUPT_STATUS_REG ( ( unsigned short ) 0x0004 )
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158 #define tcpTX_WRITE_SHADOW_REG ( ( unsigned short ) 0x01F0 )
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159 #define tcpTX_ACK_SHADOW_REG ( ( unsigned short ) 0x01E2 )
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160 #define tcpISR_MASK_REG ( ( unsigned short ) 0x0009 )
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161 #define tcpINTERRUPT_REG ( ( unsigned short ) 0x0008 )
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162 #define tcpSOCKET_STATE_REG ( ( unsigned short ) 0x00a0 )
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164 /* Constants required for hardware setup. */
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165 #define tcpRESET_ACTIVE_LOW ( ( unsigned long ) 0x20 )
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166 #define tcpRESET_ACTIVE_HIGH ( ( unsigned long ) 0x10 )
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168 /* Constants defining the source of the WIZnet ISR. */
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169 #define tcpISR_SYS_INIT ( ( unsigned char ) 0x01 )
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170 #define tcpISR_SOCKET_INIT ( ( unsigned char ) 0x02 )
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171 #define tcpISR_ESTABLISHED ( ( unsigned char ) 0x04 )
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172 #define tcpISR_CLOSED ( ( unsigned char ) 0x08 )
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173 #define tcpISR_TIMEOUT ( ( unsigned char ) 0x10 )
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174 #define tcpISR_TX_COMPLETE ( ( unsigned char ) 0x20 )
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175 #define tcpISR_RX_COMPLETE ( ( unsigned char ) 0x40 )
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177 /* Constants defining the socket status bits. */
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178 #define tcpSTATUS_ESTABLISHED ( ( unsigned char ) 0x06 )
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179 #define tcpSTATUS_LISTEN ( ( unsigned char ) 0x02 )
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181 /* Misc constants. */
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182 #define tcpNO_STATUS_BITS ( ( unsigned char ) 0x00 )
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183 #define i2cNO_ADDR_REQUIRED ( ( unsigned short ) 0x0000 )
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184 #define i2cNO_DATA_REQUIRED ( 0x0000 )
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185 #define tcpISR_QUEUE_LENGTH ( ( unsigned portBASE_TYPE ) 10 )
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186 #define tcpISR_QUEUE_ITEM_SIZE ( ( unsigned portBASE_TYPE ) 0 )
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187 #define tcpBUFFER_LEN ( 4 * 1024 )
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188 #define tcpMAX_REGISTER_LEN ( 4 )
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189 #define tcpMAX_ATTEMPTS_TO_CHECK_BUFFER ( 6 )
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190 #define tcpMAX_NON_LISTEN_STAUS_READS ( 5 )
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192 /* Message definitions. The IP address, MAC address, gateway address, etc.
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194 const unsigned char const ucDataGAR[] = { 172, 25, 218, 3 }; /* Gateway address. */
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195 const unsigned char const ucDataMSR[] = { 255, 255, 255, 0 }; /* Subnet mask. */
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196 const unsigned char const ucDataSIPR[] = { 172, 25, 218, 201 };/* IP address. */
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197 const unsigned char const ucDataSHAR[] = { 00, 23, 30, 41, 15, 26 }; /* MAC address - DO NOT USE THIS ON A PUBLIC NETWORK! */
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199 /* Other fixed messages. */
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200 const unsigned char const ucDataReset[] = { tcpRESET_CMD };
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201 const unsigned char const ucDataInit[] = { tcpSYS_INIT_CMD };
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202 const unsigned char const ucDataProtocol[] = { tcpSOCK_STREAM };
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203 const unsigned char const ucDataPort[] = { 0xBA, 0xCC };
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204 const unsigned char const ucDataSockInit[] = { tcpSOCK_INIT };
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205 const unsigned char const ucDataTxWritePointer[] = { 0x11, 0x22, 0x00, 0x00 };
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206 const unsigned char const ucDataTxAckPointer[] = { 0x11, 0x22, 0x00, 0x00 };
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207 const unsigned char const ucDataTxReadPointer[] = { 0x11, 0x22, 0x00, 0x00 };
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208 const unsigned char const ucDataListen[] = { tcpLISTEN_CMD };
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209 const unsigned char const ucDataReceiveCmd[] = { tcpRECEIVE_CMD };
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210 const unsigned char const ucDataSetTxBufSize[] = { tcp8K_TX };
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211 const unsigned char const ucDataSetRxBufSize[] = { tcp8K_RX };
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212 const unsigned char const ucDataSend[] = { tcpSEND_CMD };
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213 const unsigned char const ucDataDisconnect[] = { tcpDISCONNECT_CMD };
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214 const unsigned char const ucDataEnableISR[] = { i2cCHANNEL_0_ISR_ENABLE };
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215 const unsigned char const ucDataDisableISR[] = { i2cCHANNEL_0_ISR_DISABLE };
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216 const unsigned char const ucDataClearInterrupt[] = { i2cCLEAR_ALL_INTERRUPTS };
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218 static xSemaphoreHandle xMessageComplete = NULL;
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219 xQueueHandle xTCPISRQueue = NULL;
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221 /* Dynamically generate and send an html page. */
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222 static void prvSendSamplePage( void );
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224 /* Read a register from the WIZnet device via the i2c interface. */
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225 static void prvReadRegister( unsigned char *pucDestination, unsigned short usAddress, unsigned long ulLength );
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227 /* Send the entire Tx buffer (the Tx buffer within the WIZnet device). */
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228 static void prvFlushBuffer( unsigned long ulTxAddress );
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230 /* Write a string to the WIZnet Tx buffer. */
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231 static void prvWriteString( const char * const pucTxBuffer, long lTxLen, unsigned long *pulTxAddress );
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233 /* Convert a number to a string. */
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234 void ultoa( unsigned long ulVal, char *pcBuffer, long lIgnore );
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236 /*-----------------------------------------------------------*/
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238 void ultoa( unsigned long ulVal, char *pcBuffer, long lIgnore )
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240 unsigned long lNibble;
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243 /* Simple routine to convert an unsigned long value into a string in hex
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246 /* For each nibble in the number we are converting. */
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247 for( lIndex = 0; lIndex < ( sizeof( ulVal ) * 2 ); lIndex++ )
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249 /* Take the top four bits of the number. */
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250 lNibble = ( ulVal >> 28 );
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252 /* We are converting it to a hex string, so is the number in the range
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256 pcBuffer[ lIndex ] = '0' + lNibble;
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261 pcBuffer[ lIndex ] = 'A' + lNibble;
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264 /* Shift off the top nibble so we use the next nibble next time around. */
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268 /* Mark the end of the string with a null terminator. */
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269 pcBuffer[ lIndex ] = 0x00;
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271 /*-----------------------------------------------------------*/
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273 static void prvReadRegister( unsigned char *pucDestination, unsigned short usAddress, unsigned long ulLength )
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275 unsigned char ucRxBuffer[ tcpMAX_REGISTER_LEN ];
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277 /* Read a register value from the WIZnet device. */
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279 /* First write out the address of the register we want to read. */
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280 i2cMessage( ucRxBuffer, i2cNO_DATA_REQUIRED, tcpDEVICE_ADDRESS, usAddress, i2cWRITE, NULL, portMAX_DELAY );
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282 /* Then read back from that address. */
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283 i2cMessage( ( unsigned char * ) pucDestination, ulLength, tcpDEVICE_ADDRESS, i2cNO_ADDR_REQUIRED, i2cREAD, xMessageComplete, portMAX_DELAY );
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285 /* I2C messages are queued so use the semaphore to wait for the read to
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286 complete - otherwise we will leave this function before the I2C
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287 transactions have completed. */
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288 xSemaphoreTake( xMessageComplete, tcpLONG_DELAY );
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290 /*-----------------------------------------------------------*/
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292 void vTCPHardReset( void )
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294 /* Physical reset of the WIZnet device by using the GPIO lines to hold the
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295 WIZnet reset lines active for a few milliseconds. */
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297 /* Make sure the interrupt from the WIZnet is disabled. */
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298 VICIntEnClear |= tcpEINT0_VIC_CHANNEL_BIT;
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300 /* If xMessageComplete is NULL then this is the first time that this
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301 function has been called and the queue and semaphore used in this file
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302 have not yet been created. */
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303 if( xMessageComplete == NULL )
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305 /* Create and obtain the semaphore used when we want to wait for an i2c
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306 message to be completed. */
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307 vSemaphoreCreateBinary( xMessageComplete );
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308 xSemaphoreTake( xMessageComplete, tcpNO_DELAY );
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310 /* Create the queue used to communicate between the WIZnet and TCP tasks. */
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311 xTCPISRQueue = xQueueCreate( tcpISR_QUEUE_LENGTH, tcpISR_QUEUE_ITEM_SIZE );
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314 /* Use the GPIO to reset the network hardware. */
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315 GPIO_IOCLR = tcpRESET_ACTIVE_LOW;
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316 GPIO_IOSET = tcpRESET_ACTIVE_HIGH;
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318 /* Delay with the network hardware in reset for a short while. */
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319 vTaskDelay( tcpRESET_DELAY );
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321 GPIO_IOCLR = tcpRESET_ACTIVE_HIGH;
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322 GPIO_IOSET = tcpRESET_ACTIVE_LOW;
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324 vTaskDelay( tcpINIT_DELAY );
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326 /* Setup the EINT0 to interrupt on required events from the WIZnet device.
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327 First enable the EINT0 function of the pin. */
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328 PCB_PINSEL1 |= tcpENABLE_EINT0_FUNCTION;
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330 /* We want the TCP comms to wake us from power save. */
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331 SCB_EXTWAKE = tcpWAKE_ON_EINT0;
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333 /* Install the ISR into the VIC - but don't enable it yet! */
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334 portENTER_CRITICAL();
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336 extern void ( vEINT0_ISR_Wrapper )( void );
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338 VICIntSelect &= ~( tcpEINT0_VIC_CHANNEL_BIT );
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339 VICVectAddr3 = ( long ) vEINT0_ISR_Wrapper;
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341 VICVectCntl3 = tcpEINT0_VIC_CHANNEL | tcpEINT0_VIC_ENABLE;
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343 portEXIT_CRITICAL();
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345 /* Enable interrupts in the WIZnet itself. */
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346 i2cMessage( ucDataEnableISR, sizeof( ucDataEnableISR ), tcpDEVICE_ADDRESS, tcpISR_MASK_REG, i2cWRITE, NULL, portMAX_DELAY );
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348 vTaskDelay( tcpLONG_DELAY );
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350 /*-----------------------------------------------------------*/
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352 long lTCPSoftReset( void )
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354 unsigned char ucStatus;
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355 extern volatile long lTransactionCompleted;
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357 /* Send a message to the WIZnet device to tell it set all it's registers
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358 back to their default states. Then setup the WIZnet device as required. */
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360 /* Reset the internal WIZnet registers. */
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361 i2cMessage( ucDataReset, sizeof( ucDataReset ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
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363 /* Now we can configure the protocol. Here the MAC address, gateway
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364 address, subnet mask and IP address are configured. */
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365 i2cMessage( ucDataSHAR, sizeof( ucDataSHAR ), tcpDEVICE_ADDRESS, tcpSOURCE_HA_REG, i2cWRITE, NULL, portMAX_DELAY );
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366 i2cMessage( ucDataGAR, sizeof( ucDataGAR ), tcpDEVICE_ADDRESS, tcpGATEWAY_ADDR_REG, i2cWRITE, NULL, portMAX_DELAY );
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367 i2cMessage( ucDataMSR, sizeof( ucDataMSR ), tcpDEVICE_ADDRESS, tcpSUBNET_MASK_REG, i2cWRITE, NULL, portMAX_DELAY );
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368 i2cMessage( ucDataSIPR, sizeof( ucDataSIPR ), tcpDEVICE_ADDRESS, tpcSOURCE_IP_REG, i2cWRITE, NULL, portMAX_DELAY );
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370 /* Next the memory buffers are configured to give all the WIZnet internal
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371 memory over to a single socket. This gives the socket the maximum internal
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372 Tx and Rx buffer space. */
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373 i2cMessage( ucDataSetTxBufSize, sizeof( ucDataSetTxBufSize ), tcpDEVICE_ADDRESS, tcpTX_MEM_SIZE_REG, i2cWRITE, NULL, portMAX_DELAY );
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374 i2cMessage( ucDataSetRxBufSize, sizeof( ucDataSetRxBufSize ), tcpDEVICE_ADDRESS, tcpRX_MEM_SIZE_REG, i2cWRITE, NULL, portMAX_DELAY );
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376 /* Send the sys init command so the above parameters take effect. */
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377 i2cMessage( ucDataInit, sizeof( ucDataInit ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
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379 /* Seems to like a little wait here. */
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380 vTaskDelay( tcpINIT_DELAY );
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382 /* Read back the status to ensure the system initialised ok. */
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383 prvReadRegister( &ucStatus, tcpINTERRUPT_STATUS_REG, tcpSTATUS_READ_LEN );
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385 /* We should find that the sys init was successful. */
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386 if( ucStatus != tcpISR_SYS_INIT )
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388 return ( long ) pdFAIL;
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391 /* No i2c errors yet. */
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392 portENTER_CRITICAL();
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393 lTransactionCompleted = pdTRUE;
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394 portEXIT_CRITICAL();
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396 return ( long ) pdPASS;
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398 /*-----------------------------------------------------------*/
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400 long lTCPCreateSocket( void )
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402 unsigned char ucStatus;
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404 /* Create and configure a socket. */
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406 /* Setup and init the socket. Here the port number is set and the socket
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408 i2cMessage( ucDataProtocol, sizeof( ucDataProtocol),tcpDEVICE_ADDRESS, tpcSOCKET_OPT_REG, i2cWRITE, NULL, portMAX_DELAY );
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409 i2cMessage( ucDataPort, sizeof( ucDataPort), tcpDEVICE_ADDRESS, tcpSOURCE_PORT_REG, i2cWRITE, NULL, portMAX_DELAY );
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410 i2cMessage( ucDataSockInit, sizeof( ucDataSockInit),tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, xMessageComplete, portMAX_DELAY );
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412 /* Wait for the Init command to be sent. */
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413 if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) )
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415 /* For some reason the message was not transmitted within our block
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417 return ( long ) pdFAIL;
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420 /* Allow the socket to initialise. */
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421 vTaskDelay( tcpINIT_DELAY );
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423 /* Read back the status to ensure the socket initialised ok. */
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424 prvReadRegister( &ucStatus, tcpINTERRUPT_STATUS_REG, tcpSTATUS_READ_LEN );
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426 /* We should find that the socket init was successful. */
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427 if( ucStatus != tcpISR_SOCKET_INIT )
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429 return ( long ) pdFAIL;
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433 /* Setup the Tx pointer registers to indicate that the Tx buffer is empty. */
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434 i2cMessage( ucDataTxReadPointer, sizeof( ucDataTxReadPointer ), tcpDEVICE_ADDRESS, tcpTX_READ_POINTER_REG, i2cWRITE, NULL, portMAX_DELAY );
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435 vTaskDelay( tcpSHORT_DELAY );
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436 i2cMessage( ucDataTxWritePointer, sizeof( ucDataTxWritePointer ), tcpDEVICE_ADDRESS, tcpTX_WRITE_POINTER_REG, i2cWRITE, NULL, portMAX_DELAY );
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437 vTaskDelay( tcpSHORT_DELAY );
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438 i2cMessage( ucDataTxAckPointer, sizeof( ucDataTxAckPointer ), tcpDEVICE_ADDRESS, tcpTX_ACK_POINTER_REG, i2cWRITE, NULL, portMAX_DELAY );
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439 vTaskDelay( tcpSHORT_DELAY );
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441 return ( long ) pdPASS;
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443 /*-----------------------------------------------------------*/
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445 void vTCPListen( void )
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447 unsigned char ucISR;
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449 /* Start a passive listen on the socket. */
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451 /* Enable interrupts in the WizNet device after ensuring none are
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452 currently pending. */
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453 while( SCB_EXTINT & tcpCLEAR_EINT0 )
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455 /* The WIZnet device is still asserting and interrupt so tell it to
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457 i2cMessage( ucDataClearInterrupt, sizeof( ucDataClearInterrupt ), tcpDEVICE_ADDRESS, tcpINTERRUPT_REG, i2cWRITE, xMessageComplete, portMAX_DELAY );
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458 xSemaphoreTake( xMessageComplete, tcpLONG_DELAY );
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461 SCB_EXTINT = tcpCLEAR_EINT0;
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464 while( xQueueReceive( xTCPISRQueue, &ucISR, tcpNO_DELAY ) )
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466 /* Just clearing the queue used by the ISR routine to tell this task
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467 that the WIZnet device needs attention. */
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470 /* Now all the pending interrupts have been cleared we can enable the
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471 processor interrupts. */
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472 VICIntEnable |= tcpEINT0_VIC_CHANNEL_BIT;
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474 /* Then start listening for incoming connections. */
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475 i2cMessage( ucDataListen, sizeof( ucDataListen ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
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477 /*-----------------------------------------------------------*/
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479 long lProcessConnection( void )
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481 unsigned char ucISR, ucState, ucLastState = 2, ucShadow;
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482 extern volatile long lTransactionCompleted;
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483 long lSameStateCount = 0, lDataSent = pdFALSE;
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484 unsigned long ulWritePointer, ulAckPointer;
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486 /* No I2C errors can yet have occurred. */
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487 portENTER_CRITICAL();
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488 lTransactionCompleted = pdTRUE;
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489 portEXIT_CRITICAL();
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491 /* Keep looping - processing interrupts, until we have completed a
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492 transaction. This uses the WIZnet in it's simplest form. The socket
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493 accepts a connection - we process the connection - then close the socket.
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494 We then go back to reinitialise everything and start again. */
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495 while( lTransactionCompleted == pdTRUE )
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497 /* Wait for a message on the queue from the WIZnet ISR. When the
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498 WIZnet device asserts an interrupt the ISR simply posts a message
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499 onto this queue to wake this task. */
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500 if( xQueueReceive( xTCPISRQueue, &ucISR, tcpCONNECTION_WAIT_DELAY ) )
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502 /* The ISR posted a message on this queue to tell us that the
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503 WIZnet device asserted an interrupt. The ISR cannot process
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504 an I2C message so cannot tell us what caused the interrupt so
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505 we have to query the device here. This task is the highest
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506 priority in the system so will run immediately following the ISR. */
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507 prvReadRegister( &ucISR, tcpINTERRUPT_STATUS_REG, tcpSTATUS_READ_LEN );
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509 /* Once we have read what caused the ISR we can clear the interrupt
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511 i2cMessage( ucDataClearInterrupt, sizeof( ucDataClearInterrupt ), tcpDEVICE_ADDRESS, tcpINTERRUPT_REG, i2cWRITE, NULL, portMAX_DELAY );
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513 /* Now we can clear the processor interrupt and re-enable ready for
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515 SCB_EXTINT = tcpCLEAR_EINT0;
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516 VICIntEnable |= tcpEINT0_VIC_CHANNEL_BIT;
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518 /* Process the interrupt ... */
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520 if( ucISR & tcpISR_ESTABLISHED )
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522 /* A connection has been established - respond by sending
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523 a receive command. */
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524 i2cMessage( ucDataReceiveCmd, sizeof( ucDataReceiveCmd ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
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527 if( ucISR & tcpISR_RX_COMPLETE )
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529 /* We message has been received. This will be an HTTP get
\r
530 command. We only have one page to send so just send it without
\r
531 regard to what the actual requested page was. */
\r
532 prvSendSamplePage();
\r
535 if( ucISR & tcpISR_TX_COMPLETE )
\r
537 /* We have a TX complete interrupt - which oddly does not
\r
538 indicate that the message being sent is complete so we cannot
\r
539 yet close the socket. Instead we read the position of the Tx
\r
540 pointer within the WIZnet device so we know how much data it
\r
541 has to send. Later we will read the ack pointer and compare
\r
542 this to the Tx pointer to ascertain whether the transmission
\r
545 /* First read the shadow register. */
\r
546 prvReadRegister( &ucShadow, tcpTX_WRITE_SHADOW_REG, tcpSHADOW_READ_LEN );
\r
548 /* Now a short delay is required. */
\r
549 vTaskDelay( tcpSHORT_DELAY );
\r
551 /* Then we can read the real register. */
\r
552 prvReadRegister( ( unsigned char * ) &ulWritePointer, tcpTX_WRITE_POINTER_REG, sizeof( ulWritePointer ) );
\r
554 /* We cannot do anything more here but need to remember that
\r
555 this interrupt has occurred. */
\r
556 lDataSent = pdTRUE;
\r
559 if( ucISR & tcpISR_CLOSED )
\r
561 /* The socket has been closed so we can leave this function. */
\r
562 lTransactionCompleted = pdFALSE;
\r
567 /* We have not received an interrupt from the WIZnet device for a
\r
568 while. Read the socket status and check that everything is as
\r
570 prvReadRegister( &ucState, tcpSOCKET_STATE_REG, tcpSTATUS_READ_LEN );
\r
572 if( ( ucState == tcpSTATUS_ESTABLISHED ) && ( lDataSent > 0 ) )
\r
574 /* The socket is established and we have already received a Tx
\r
575 end interrupt. We must therefore be waiting for the Tx buffer
\r
576 inside the WIZnet device to be empty before we can close the
\r
579 Read the Ack pointer register to see if it has caught up with
\r
580 the Tx pointer register. First we have to read the shadow
\r
582 prvReadRegister( &ucShadow, tcpTX_ACK_SHADOW_REG, tcpSHADOW_READ_LEN );
\r
583 vTaskDelay( tcpSHORT_DELAY );
\r
584 prvReadRegister( ( unsigned char * ) &ulAckPointer, tcpTX_ACK_POINTER_REG, sizeof( ulWritePointer ) );
\r
586 if( ulAckPointer == ulWritePointer )
\r
588 /* The Ack and write pointer are now equal and we can
\r
589 safely close the socket. */
\r
590 i2cMessage( ucDataDisconnect, sizeof( ucDataDisconnect ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
\r
594 /* Keep a count of how many times we encounter the Tx
\r
595 buffer still containing data. */
\r
597 if( lDataSent > tcpMAX_ATTEMPTS_TO_CHECK_BUFFER )
\r
599 /* Assume we cannot complete sending the data and
\r
600 therefore cannot safely close the socket. Start over. */
\r
602 lTransactionCompleted = pdFALSE;
\r
606 else if( ucState != tcpSTATUS_LISTEN )
\r
608 /* If we have not yet received a Tx end interrupt we would only
\r
609 ever expect to find the socket still listening for any
\r
610 sustained period. */
\r
611 if( ucState == ucLastState )
\r
614 if( lSameStateCount > tcpMAX_NON_LISTEN_STAUS_READS )
\r
616 /* We are persistently in an unexpected state. Assume
\r
617 we cannot safely close the socket and start over. */
\r
619 lTransactionCompleted = pdFALSE;
\r
625 /* We are in the listen state so are happy that everything
\r
627 lSameStateCount = 0;
\r
630 /* Remember what state we are in this time around so we can check
\r
631 for a persistence on an unexpected state. */
\r
632 ucLastState = ucState;
\r
636 /* We are going to reinitialise the WIZnet device so do not want our
\r
637 interrupts from the WIZnet to be processed. */
\r
638 VICIntEnClear |= tcpEINT0_VIC_CHANNEL_BIT;
\r
639 return lTransactionCompleted;
\r
641 /*-----------------------------------------------------------*/
\r
643 static void prvWriteString( const char * const pucTxBuffer, long lTxLen, unsigned long *pulTxAddress )
\r
645 unsigned long ulSendAddress;
\r
647 /* Send a string to the Tx buffer internal to the WIZnet device. */
\r
649 /* Calculate the address to which we are going to write in the buffer. */
\r
650 ulSendAddress = ( *pulTxAddress & tcpSINGLE_SOCKET_ADDR_MASK ) + tcpSINGLE_SOCKET_ADDR_OFFSET;
\r
652 /* Send the buffer to the calculated address. Use the semaphore so we
\r
653 can wait until the entire message has been transferred. */
\r
654 i2cMessage( ( unsigned char * ) pucTxBuffer, lTxLen, tcpDEVICE_ADDRESS, ( unsigned short ) ulSendAddress, i2cWRITE, xMessageComplete, portMAX_DELAY );
\r
656 /* Wait until the semaphore indicates that the message has been transferred. */
\r
657 if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) )
\r
662 /* Return the new address of the end of the buffer (within the WIZnet
\r
664 *pulTxAddress += ( unsigned long ) lTxLen;
\r
666 /*-----------------------------------------------------------*/
\r
668 static void prvFlushBuffer( unsigned long ulTxAddress )
\r
670 unsigned char ucTxBuffer[ tcpMAX_REGISTER_LEN ];
\r
672 /* We have written some data to the Tx buffer internal to the WIZnet
\r
673 device. Now we update the Tx pointer inside the WIZnet then send a
\r
674 Send command - which causes the data up to the new Tx pointer to be
\r
677 /* Make sure endieness is correct for transmission. */
\r
678 ulTxAddress = htonl( ulTxAddress );
\r
680 /* Place the new Tx pointer in the string to be transmitted. */
\r
681 ucTxBuffer[ 0 ] = ( unsigned char ) ( ulTxAddress & 0xff );
\r
683 ucTxBuffer[ 1 ] = ( unsigned char ) ( ulTxAddress & 0xff );
\r
685 ucTxBuffer[ 2 ] = ( unsigned char ) ( ulTxAddress & 0xff );
\r
687 ucTxBuffer[ 3 ] = ( unsigned char ) ( ulTxAddress & 0xff );
\r
690 /* And send it to the WIZnet device. */
\r
691 i2cMessage( ucTxBuffer, sizeof( ulTxAddress ), tcpDEVICE_ADDRESS, tcpTX_WRITE_POINTER_REG, i2cWRITE, xMessageComplete, portMAX_DELAY );
\r
693 if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) )
\r
698 vTaskDelay( tcpSHORT_DELAY );
\r
701 i2cMessage( ucDataSend, sizeof( ucDataSend ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, xMessageComplete, portMAX_DELAY );
\r
703 if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) )
\r
708 /*-----------------------------------------------------------*/
\r
710 static void prvSendSamplePage( void )
\r
712 extern long lErrorInTask;
\r
713 unsigned long ulTxAddress;
\r
714 unsigned char ucShadow;
\r
716 static unsigned long ulRefreshCount = 0x00;
\r
717 static char cPageBuffer[ tcpBUFFER_LEN ];
\r
720 /* This function just generates a sample page of HTML which gets
\r
721 sent each time a client attaches to the socket. The page is created
\r
722 from two fixed strings (cSamplePageFirstPart and cSamplePageSecondPart)
\r
723 with a bit of dynamically generated data in the middle. */
\r
725 /* We need to know the address to which the html string should be sent
\r
726 in the WIZnet Tx buffer. First read the shadow register. */
\r
727 prvReadRegister( &ucShadow, tcpTX_WRITE_SHADOW_REG, tcpSHADOW_READ_LEN );
\r
729 /* Now a short delay is required. */
\r
730 vTaskDelay( tcpSHORT_DELAY );
\r
732 /* Now we can read the real pointer value. */
\r
733 prvReadRegister( ( unsigned char * ) &ulTxAddress, tcpTX_WRITE_POINTER_REG, sizeof( ulTxAddress ) );
\r
735 /* Make sure endieness is correct. */
\r
736 ulTxAddress = htonl( ulTxAddress );
\r
738 /* Send the start of the page. */
\r
739 prvWriteString( cSamplePageFirstPart, strlen( cSamplePageFirstPart ), &ulTxAddress );
\r
741 /* Generate a bit of dynamic data and place it in the buffer ready to be
\r
743 strcpy( cPageBuffer, "<BR>Number of ticks since boot = 0x" );
\r
744 lIndex = strlen( cPageBuffer );
\r
745 ultoa( xTaskGetTickCount(), &( cPageBuffer[ lIndex ] ), 0 );
\r
746 strcat( cPageBuffer, "<br>Number of tasks executing = ");
\r
747 lIndex = strlen( cPageBuffer );
\r
748 ultoa( ( unsigned long ) uxTaskGetNumberOfTasks(), &( cPageBuffer[ lIndex ] ), 0 );
\r
749 strcat( cPageBuffer, "<br>IO port 0 state (used by flash tasks) = 0x" );
\r
750 lIndex = strlen( cPageBuffer );
\r
751 ultoa( ( unsigned long ) GPIO0_IOPIN, &( cPageBuffer[ lIndex ] ), 0 );
\r
752 strcat( cPageBuffer, "<br>Refresh = 0x" );
\r
753 lIndex = strlen( cPageBuffer );
\r
754 ultoa( ( unsigned long ) ulRefreshCount, &( cPageBuffer[ lIndex ] ), 0 );
\r
758 strcat( cPageBuffer, "<p>An error has occurred in at least one task." );
\r
762 strcat( cPageBuffer, "<p>All tasks executing without error." );
\r
767 /* Send the dynamically generated string. */
\r
768 prvWriteString( cPageBuffer, strlen( cPageBuffer ), &ulTxAddress );
\r
770 /* Finish the page. */
\r
771 prvWriteString( cSamplePageSecondPart, strlen( cSamplePageSecondPart ), &ulTxAddress );
\r
773 /* Tell the WIZnet to send the data we have just written to its Tx buffer. */
\r
774 prvFlushBuffer( ulTxAddress );
\r