2 * FreeRTOS Kernel V10.1.0
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3 * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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29 * Interrupt driven driver for the EMAC peripheral. This driver is not
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30 * reentrant, re-entrancy is handled by a semaphore at the network interface
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38 + Corrected the byte order when writing the MAC address to the MAC.
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39 + Support added for MII interfaces. Previously only RMII was supported.
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43 + The MII interface is now the default.
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44 + Modified the initialisation sequence slightly to allow auto init more
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49 + Made the function vClearEMACTxBuffer() more robust by moving the index
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50 manipulation into the if() statement. This allows the tx interrupt to
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51 execute even when there is no data to handle.
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55 + Corrected the Rx frame length mask when obtaining the length from the
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60 /* Standard includes. */
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63 /* Scheduler includes. */
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64 #include "FreeRTOS.h"
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68 /* Demo app includes. */
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69 #include "SAM7_EMAC.h"
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71 /* Hardware specific includes. */
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74 #include "AT91SAM7X256.h"
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77 /* USE_RMII_INTERFACE must be defined as 1 to use an RMII interface, or 0
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78 to use an MII interface. */
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79 #define USE_RMII_INTERFACE 0
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82 /* The buffer addresses written into the descriptors must be aligned so the
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83 last few bits are zero. These bits have special meaning for the EMAC
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84 peripheral and cannot be used as part of the address. */
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85 #define emacADDRESS_MASK ( ( unsigned long ) 0xFFFFFFFC )
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87 /* Bit used within the address stored in the descriptor to mark the last
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88 descriptor in the array. */
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89 #define emacRX_WRAP_BIT ( ( unsigned long ) 0x02 )
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91 /* Bit used within the Tx descriptor status to indicate whether the
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92 descriptor is under the control of the EMAC or the software. */
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93 #define emacTX_BUF_USED ( ( unsigned long ) 0x80000000 )
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95 /* A short delay is used to wait for a buffer to become available, should
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96 one not be immediately available when trying to transmit a frame. */
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97 #define emacBUFFER_WAIT_DELAY ( 2 )
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98 #define emacMAX_WAIT_CYCLES ( ( portBASE_TYPE ) ( configTICK_RATE_HZ / 40 ) )
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100 /* The time to block waiting for input. */
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101 #define emacBLOCK_TIME_WAITING_FOR_INPUT ( ( TickType_t ) 100 )
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103 /* Peripheral setup for the EMAC. */
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104 #define emacPERIPHERAL_A_SETUP ( ( unsigned long ) AT91C_PB2_ETX0 ) | \
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105 ( ( unsigned long ) AT91C_PB12_ETXER ) | \
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106 ( ( unsigned long ) AT91C_PB16_ECOL ) | \
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107 ( ( unsigned long ) AT91C_PB11_ETX3 ) | \
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108 ( ( unsigned long ) AT91C_PB6_ERX1 ) | \
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109 ( ( unsigned long ) AT91C_PB15_ERXDV ) | \
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110 ( ( unsigned long ) AT91C_PB13_ERX2 ) | \
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111 ( ( unsigned long ) AT91C_PB3_ETX1 ) | \
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112 ( ( unsigned long ) AT91C_PB8_EMDC ) | \
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113 ( ( unsigned long ) AT91C_PB5_ERX0 ) | \
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114 ( ( unsigned long ) AT91C_PB14_ERX3 ) | \
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115 ( ( unsigned long ) AT91C_PB4_ECRS_ECRSDV ) | \
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116 ( ( unsigned long ) AT91C_PB1_ETXEN ) | \
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117 ( ( unsigned long ) AT91C_PB10_ETX2 ) | \
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118 ( ( unsigned long ) AT91C_PB0_ETXCK_EREFCK ) | \
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119 ( ( unsigned long ) AT91C_PB9_EMDIO ) | \
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120 ( ( unsigned long ) AT91C_PB7_ERXER ) | \
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121 ( ( unsigned long ) AT91C_PB17_ERXCK );
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123 /* Misc defines. */
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124 #define emacINTERRUPT_LEVEL ( 5 )
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125 #define emacNO_DELAY ( 0 )
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126 #define emacTOTAL_FRAME_HEADER_SIZE ( 54 )
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127 #define emacPHY_INIT_DELAY ( 5000 / portTICK_PERIOD_MS )
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128 #define emacRESET_KEY ( ( unsigned long ) 0xA5000000 )
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129 #define emacRESET_LENGTH ( ( unsigned long ) ( 0x01 << 8 ) )
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131 /* The Atmel header file only defines the TX frame length mask. */
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132 #define emacRX_LENGTH_FRAME ( 0xfff )
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134 /*-----------------------------------------------------------*/
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136 /* Buffer written to by the EMAC DMA. Must be aligned as described by the
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137 comment above the emacADDRESS_MASK definition. */
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138 static volatile char pcRxBuffer[ NB_RX_BUFFERS * ETH_RX_BUFFER_SIZE ] __attribute__ ((aligned (8)));
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140 /* Buffer read by the EMAC DMA. Must be aligned as described by the comment
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141 above the emacADDRESS_MASK definition. */
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142 static char pcTxBuffer[ NB_TX_BUFFERS * ETH_TX_BUFFER_SIZE ] __attribute__ ((aligned (8)));
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144 /* Descriptors used to communicate between the program and the EMAC peripheral.
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145 These descriptors hold the locations and state of the Rx and Tx buffers. */
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146 static volatile AT91S_TxTdDescriptor xTxDescriptors[ NB_TX_BUFFERS ];
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147 static volatile AT91S_RxTdDescriptor xRxDescriptors[ NB_RX_BUFFERS ];
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149 /* The IP and Ethernet addresses are read from the header files. */
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150 const char cMACAddress[ 6 ] = { emacETHADDR0, emacETHADDR1, emacETHADDR2, emacETHADDR3, emacETHADDR4, emacETHADDR5 };
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151 const unsigned char ucIPAddress[ 4 ] = { emacIPADDR0, emacIPADDR1, emacIPADDR2, emacIPADDR3 };
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153 /*-----------------------------------------------------------*/
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155 /* See the header file for descriptions of public functions. */
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158 * Prototype for the EMAC interrupt function.
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160 void vEMACISR_Wrapper( void ) __attribute__ ((naked));
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163 * Initialise both the Tx and Rx descriptors used by the EMAC.
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165 static void prvSetupDescriptors(void);
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168 * Write our MAC address into the EMAC.
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170 static void prvSetupMACAddress( void );
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173 * Configure the EMAC and AIC for EMAC interrupts.
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175 static void prvSetupEMACInterrupt( void );
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178 * Some initialisation functions taken from the Atmel EMAC sample code.
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180 static void vReadPHY( unsigned char ucPHYAddress, unsigned char ucAddress, unsigned long *pulValue );
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181 static portBASE_TYPE xGetLinkSpeed( void );
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182 static portBASE_TYPE prvProbePHY( void );
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183 #if USE_RMII_INTERFACE != 1
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184 static void vWritePHY( unsigned char ucPHYAddress, unsigned char ucAddress, unsigned long ulValue);
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188 /* The semaphore used by the EMAC ISR to wake the EMAC task. */
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189 static SemaphoreHandle_t xSemaphore = NULL;
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191 /* Holds the index to the next buffer from which data will be read. */
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192 static volatile unsigned long ulNextRxBuffer = 0;
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194 /*-----------------------------------------------------------*/
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196 /* See the header file for descriptions of public functions. */
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197 long lEMACSend( char *pcFrom, unsigned long ulLength, long lEndOfFrame )
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199 static unsigned portBASE_TYPE uxTxBufferIndex = 0;
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200 portBASE_TYPE xWaitCycles = 0;
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201 long lReturn = pdPASS;
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203 unsigned long ulLastBuffer, ulDataBuffered = 0, ulDataRemainingToSend, ulLengthToSend;
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205 /* If the length of data to be transmitted is greater than each individual
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206 transmit buffer then the data will be split into more than one buffer.
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207 Loop until the entire length has been buffered. */
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208 while( ulDataBuffered < ulLength )
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210 /* Is a buffer available? */
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211 while( !( xTxDescriptors[ uxTxBufferIndex ].U_Status.status & AT91C_TRANSMIT_OK ) )
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213 /* There is no room to write the Tx data to the Tx buffer. Wait a
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214 short while, then try again. */
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216 if( xWaitCycles > emacMAX_WAIT_CYCLES )
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224 vTaskDelay( emacBUFFER_WAIT_DELAY );
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228 /* lReturn will only be pdPASS if a buffer is available. */
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229 if( lReturn == pdPASS )
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231 portENTER_CRITICAL();
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233 /* Get the address of the buffer from the descriptor, then copy
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234 the data into the buffer. */
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235 pcBuffer = ( char * ) xTxDescriptors[ uxTxBufferIndex ].addr;
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237 /* How much can we write to the buffer? */
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238 ulDataRemainingToSend = ulLength - ulDataBuffered;
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239 if( ulDataRemainingToSend <= ETH_TX_BUFFER_SIZE )
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241 /* We can write all the remaining bytes. */
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242 ulLengthToSend = ulDataRemainingToSend;
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246 /* We can not write more than ETH_TX_BUFFER_SIZE in one go. */
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247 ulLengthToSend = ETH_TX_BUFFER_SIZE;
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250 /* Copy the data into the buffer. */
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251 memcpy( ( void * ) pcBuffer, ( void * ) &( pcFrom[ ulDataBuffered ] ), ulLengthToSend );
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252 ulDataBuffered += ulLengthToSend;
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254 /* Is this the last data for the frame? */
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255 if( lEndOfFrame && ( ulDataBuffered >= ulLength ) )
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257 /* No more data remains for this frame so we can start the
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259 ulLastBuffer = AT91C_LAST_BUFFER;
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263 /* More data to come for this frame. */
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267 /* Fill out the necessary in the descriptor to get the data sent,
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268 then move to the next descriptor, wrapping if necessary. */
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269 if( uxTxBufferIndex >= ( NB_TX_BUFFERS - 1 ) )
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271 xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( ulLengthToSend & ( unsigned long ) AT91C_LENGTH_FRAME )
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273 | AT91C_TRANSMIT_WRAP;
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274 uxTxBufferIndex = 0;
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278 xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( ulLengthToSend & ( unsigned long ) AT91C_LENGTH_FRAME )
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283 /* If this is the last buffer to be sent for this frame we can
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284 start the transmission. */
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287 AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TSTART;
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290 portEXIT_CRITICAL();
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300 /*-----------------------------------------------------------*/
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302 /* See the header file for descriptions of public functions. */
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303 unsigned long ulEMACInputLength( void )
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305 register unsigned long ulIndex, ulLength = 0;
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307 /* Skip any fragments. We are looking for the first buffer that contains
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308 data and has the SOF (start of frame) bit set. */
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309 while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AT91C_OWNERSHIP_BIT ) && !( xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AT91C_SOF ) )
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311 /* Ignoring this buffer. Mark it as free again. */
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312 xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );
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314 if( ulNextRxBuffer >= NB_RX_BUFFERS )
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316 ulNextRxBuffer = 0;
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320 /* We are going to walk through the descriptors that make up this frame,
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321 but don't want to alter ulNextRxBuffer as this would prevent vEMACRead()
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322 from finding the data. Therefore use a copy of ulNextRxBuffer instead. */
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323 ulIndex = ulNextRxBuffer;
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325 /* Walk through the descriptors until we find the last buffer for this
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326 frame. The last buffer will give us the length of the entire frame. */
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327 while( ( xRxDescriptors[ ulIndex ].addr & AT91C_OWNERSHIP_BIT ) && !ulLength )
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329 ulLength = xRxDescriptors[ ulIndex ].U_Status.status & emacRX_LENGTH_FRAME;
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331 /* Increment to the next buffer, wrapping if necessary. */
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333 if( ulIndex >= NB_RX_BUFFERS )
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341 /*-----------------------------------------------------------*/
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343 /* See the header file for descriptions of public functions. */
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344 void vEMACRead( char *pcTo, unsigned long ulSectionLength, unsigned long ulTotalFrameLength )
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346 static unsigned long ulSectionBytesReadSoFar = 0, ulBufferPosition = 0, ulFameBytesReadSoFar = 0;
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347 static char *pcSource;
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348 register unsigned long ulBytesRemainingInBuffer, ulRemainingSectionBytes;
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350 /* Read ulSectionLength bytes from the Rx buffers. This is not necessarily any
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351 correspondence between the length of our Rx buffers, and the length of the
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352 data we are returning or the length of the data being requested. Therefore,
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353 between calls we have to remember not only which buffer we are currently
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354 processing, but our position within that buffer. This would be greatly
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355 simplified if PBUF_POOL_BUFSIZE could be guaranteed to be greater than
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356 the size of each Rx buffer, and that memory fragmentation did not occur.
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358 This function should only be called after a call to ulEMACInputLength().
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359 This will ensure ulNextRxBuffer is set to the correct buffer. */
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363 /* vEMACRead is called with pcTo set to NULL to indicate that we are about
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364 to read a new frame. Any fragments remaining in the frame we were
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365 processing during the last call should be dropped. */
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368 /* How many bytes are indicated as being in this buffer? If none then
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369 the buffer is completely full and the frame is contained within more
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370 than one buffer. */
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372 /* Reset our state variables ready for the next read from this buffer. */
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373 pcSource = ( char * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );
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374 ulFameBytesReadSoFar = ( unsigned long ) 0;
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375 ulBufferPosition = ( unsigned long ) 0;
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379 /* Loop until we have obtained the required amount of data. */
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380 ulSectionBytesReadSoFar = 0;
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381 while( ulSectionBytesReadSoFar < ulSectionLength )
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383 /* We may have already read some data from this buffer. How much
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384 data remains in the buffer? */
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385 ulBytesRemainingInBuffer = ( ETH_RX_BUFFER_SIZE - ulBufferPosition );
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387 /* How many more bytes do we need to read before we have the
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388 required amount of data? */
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389 ulRemainingSectionBytes = ulSectionLength - ulSectionBytesReadSoFar;
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391 /* Do we want more data than remains in the buffer? */
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392 if( ulRemainingSectionBytes > ulBytesRemainingInBuffer )
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394 /* We want more data than remains in the buffer so we can
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395 write the remains of the buffer to the destination, then move
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396 onto the next buffer to get the rest. */
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397 memcpy( &( pcTo[ ulSectionBytesReadSoFar ] ), &( pcSource[ ulBufferPosition ] ), ulBytesRemainingInBuffer );
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398 ulSectionBytesReadSoFar += ulBytesRemainingInBuffer;
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399 ulFameBytesReadSoFar += ulBytesRemainingInBuffer;
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401 /* Mark the buffer as free again. */
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402 xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );
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404 /* Move onto the next buffer. */
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406 if( ulNextRxBuffer >= NB_RX_BUFFERS )
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408 ulNextRxBuffer = ( unsigned long ) 0;
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411 /* Reset the variables for the new buffer. */
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412 pcSource = ( char * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );
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413 ulBufferPosition = ( unsigned long ) 0;
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417 /* We have enough data in this buffer to send back. Read out
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418 enough data and remember how far we read up to. */
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419 memcpy( &( pcTo[ ulSectionBytesReadSoFar ] ), &( pcSource[ ulBufferPosition ] ), ulRemainingSectionBytes );
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421 /* There may be more data in this buffer yet. Increment our
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422 position in this buffer past the data we have just read. */
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423 ulBufferPosition += ulRemainingSectionBytes;
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424 ulSectionBytesReadSoFar += ulRemainingSectionBytes;
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425 ulFameBytesReadSoFar += ulRemainingSectionBytes;
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427 /* Have we now finished with this buffer? */
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428 if( ( ulBufferPosition >= ETH_RX_BUFFER_SIZE ) || ( ulFameBytesReadSoFar >= ulTotalFrameLength ) )
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430 /* Mark the buffer as free again. */
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431 xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );
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433 /* Move onto the next buffer. */
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435 if( ulNextRxBuffer >= NB_RX_BUFFERS )
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437 ulNextRxBuffer = 0;
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440 pcSource = ( char * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );
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441 ulBufferPosition = 0;
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447 /*-----------------------------------------------------------*/
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449 /* See the header file for descriptions of public functions. */
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450 SemaphoreHandle_t xEMACInit( void )
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452 /* Code supplied by Atmel -------------------------------*/
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454 /* Disable pull up on RXDV => PHY normal mode (not in test mode),
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455 PHY has internal pull down. */
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456 AT91C_BASE_PIOB->PIO_PPUDR = 1 << 15;
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458 #if USE_RMII_INTERFACE != 1
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459 /* PHY has internal pull down : set MII mode. */
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460 AT91C_BASE_PIOB->PIO_PPUDR = 1 << 16;
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463 /* Clear PB18 <=> PHY powerdown. */
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464 AT91C_BASE_PIOB->PIO_PER = 1 << 18;
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465 AT91C_BASE_PIOB->PIO_OER = 1 << 18;
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466 AT91C_BASE_PIOB->PIO_CODR = 1 << 18;
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468 /* After PHY power up, hardware reset. */
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469 AT91C_BASE_RSTC->RSTC_RMR = emacRESET_KEY | emacRESET_LENGTH;
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470 AT91C_BASE_RSTC->RSTC_RCR = emacRESET_KEY | AT91C_RSTC_EXTRST;
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472 /* Wait for hardware reset end. */
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473 while( !( AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL ) )
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475 __asm volatile ( "NOP" );
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477 __asm volatile ( "NOP" );
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479 /* Setup the pins. */
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480 AT91C_BASE_PIOB->PIO_ASR = emacPERIPHERAL_A_SETUP;
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481 AT91C_BASE_PIOB->PIO_PDR = emacPERIPHERAL_A_SETUP;
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483 /* Enable com between EMAC PHY.
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485 Enable management port. */
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486 AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;
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488 /* MDC = MCK/32. */
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489 AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10;
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491 /* Wait for PHY auto init end (rather crude delay!). */
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492 vTaskDelay( emacPHY_INIT_DELAY );
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494 /* PHY configuration. */
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495 #if USE_RMII_INTERFACE != 1
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497 unsigned long ulControl;
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499 /* PHY has internal pull down : disable MII isolate. */
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500 vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl );
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501 vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl );
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502 ulControl &= ~BMCR_ISOLATE;
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503 vWritePHY( AT91C_PHY_ADDR, MII_BMCR, ulControl );
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507 /* Disable management port again. */
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508 AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
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510 #if USE_RMII_INTERFACE != 1
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511 /* Enable EMAC in MII mode, enable clock ERXCK and ETXCK. */
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512 AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_CLKEN ;
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514 /* Enable EMAC in RMII mode, enable RMII clock (50MHz from oscillator
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516 AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_RMII | AT91C_EMAC_CLKEN ;
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519 /* End of code supplied by Atmel ------------------------*/
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521 /* Setup the buffers and descriptors. */
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522 prvSetupDescriptors();
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524 /* Load our MAC address into the EMAC. */
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525 prvSetupMACAddress();
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527 /* Are we connected? */
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528 if( prvProbePHY() )
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530 /* Enable the interrupt! */
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531 portENTER_CRITICAL();
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533 prvSetupEMACInterrupt();
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534 vPassEMACSemaphore( xSemaphore );
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536 portEXIT_CRITICAL();
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541 /*-----------------------------------------------------------*/
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543 /* See the header file for descriptions of public functions. */
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544 void vClearEMACTxBuffer( void )
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546 static unsigned portBASE_TYPE uxNextBufferToClear = 0;
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548 /* Called on Tx interrupt events to reset the AT91C_TRANSMIT_OK bit in each
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549 Tx buffer within the frame just transmitted. This marks all the buffers
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550 as available again.
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552 The first buffer in the frame should have the bit set automatically. */
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553 if( xTxDescriptors[ uxNextBufferToClear ].U_Status.status & AT91C_TRANSMIT_OK )
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555 /* Loop through the other buffers in the frame. */
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556 while( !( xTxDescriptors[ uxNextBufferToClear ].U_Status.status & AT91C_LAST_BUFFER ) )
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558 uxNextBufferToClear++;
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560 if( uxNextBufferToClear >= NB_TX_BUFFERS )
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562 uxNextBufferToClear = 0;
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565 xTxDescriptors[ uxNextBufferToClear ].U_Status.status |= AT91C_TRANSMIT_OK;
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568 /* Start with the next buffer the next time a Tx interrupt is called. */
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569 uxNextBufferToClear++;
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571 /* Do we need to wrap back to the first buffer? */
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572 if( uxNextBufferToClear >= NB_TX_BUFFERS )
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574 uxNextBufferToClear = 0;
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578 /*-----------------------------------------------------------*/
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580 static void prvSetupDescriptors(void)
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582 unsigned portBASE_TYPE xIndex;
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583 unsigned long ulAddress;
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585 /* Initialise xRxDescriptors descriptor. */
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586 for( xIndex = 0; xIndex < NB_RX_BUFFERS; ++xIndex )
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588 /* Calculate the address of the nth buffer within the array. */
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589 ulAddress = ( unsigned long )( pcRxBuffer + ( xIndex * ETH_RX_BUFFER_SIZE ) );
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591 /* Write the buffer address into the descriptor. The DMA will place
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592 the data at this address when this descriptor is being used. Mask off
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593 the bottom bits of the address as these have special meaning. */
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594 xRxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;
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597 /* The last buffer has the wrap bit set so the EMAC knows to wrap back
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598 to the first buffer. */
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599 xRxDescriptors[ NB_RX_BUFFERS - 1 ].addr |= emacRX_WRAP_BIT;
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601 /* Initialise xTxDescriptors. */
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602 for( xIndex = 0; xIndex < NB_TX_BUFFERS; ++xIndex )
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604 /* Calculate the address of the nth buffer within the array. */
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605 ulAddress = ( unsigned long )( pcTxBuffer + ( xIndex * ETH_TX_BUFFER_SIZE ) );
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607 /* Write the buffer address into the descriptor. The DMA will read
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608 data from here when the descriptor is being used. */
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609 xTxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;
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610 xTxDescriptors[ xIndex ].U_Status.status = AT91C_TRANSMIT_OK;
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613 /* The last buffer has the wrap bit set so the EMAC knows to wrap back
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614 to the first buffer. */
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615 xTxDescriptors[ NB_TX_BUFFERS - 1 ].U_Status.status = AT91C_TRANSMIT_WRAP | AT91C_TRANSMIT_OK;
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617 /* Tell the EMAC where to find the descriptors. */
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618 AT91C_BASE_EMAC->EMAC_RBQP = ( unsigned long ) xRxDescriptors;
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619 AT91C_BASE_EMAC->EMAC_TBQP = ( unsigned long ) xTxDescriptors;
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621 /* Clear all the bits in the receive status register. */
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622 AT91C_BASE_EMAC->EMAC_RSR = ( AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA );
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624 /* Enable the copy of data into the buffers, ignore broadcasts,
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625 and don't copy FCS. */
\r
626 AT91C_BASE_EMAC->EMAC_NCFGR |= ( AT91C_EMAC_CAF | AT91C_EMAC_NBC | AT91C_EMAC_DRFCS);
\r
628 /* Enable Rx and Tx, plus the stats register. */
\r
629 AT91C_BASE_EMAC->EMAC_NCR |= ( AT91C_EMAC_TE | AT91C_EMAC_RE | AT91C_EMAC_WESTAT );
\r
631 /*-----------------------------------------------------------*/
\r
633 static void prvSetupMACAddress( void )
\r
635 /* Must be written SA1L then SA1H. */
\r
636 AT91C_BASE_EMAC->EMAC_SA1L = ( ( unsigned long ) cMACAddress[ 3 ] << 24 ) |
\r
637 ( ( unsigned long ) cMACAddress[ 2 ] << 16 ) |
\r
638 ( ( unsigned long ) cMACAddress[ 1 ] << 8 ) |
\r
641 AT91C_BASE_EMAC->EMAC_SA1H = ( ( unsigned long ) cMACAddress[ 5 ] << 8 ) |
\r
644 /*-----------------------------------------------------------*/
\r
646 static void prvSetupEMACInterrupt( void )
\r
648 /* Create the semaphore used to trigger the EMAC task. */
\r
649 vSemaphoreCreateBinary( xSemaphore );
\r
652 /* We start by 'taking' the semaphore so the ISR can 'give' it when the
\r
653 first interrupt occurs. */
\r
654 xSemaphoreTake( xSemaphore, emacNO_DELAY );
\r
655 portENTER_CRITICAL();
\r
657 /* We want to interrupt on Rx and Tx events. */
\r
658 AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_RCOMP | AT91C_EMAC_TCOMP;
\r
660 /* Enable the interrupts in the AIC. */
\r
661 AT91F_AIC_ConfigureIt( AT91C_ID_EMAC, emacINTERRUPT_LEVEL, AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, ( void (*)( void ) ) vEMACISR_Wrapper );
\r
662 AT91C_BASE_AIC->AIC_IECR = 0x1 << AT91C_ID_EMAC;
\r
664 portEXIT_CRITICAL();
\r
673 * The following functions are initialisation functions taken from the Atmel
\r
674 * EMAC sample code.
\r
678 static portBASE_TYPE prvProbePHY( void )
\r
680 unsigned long ulPHYId1, ulPHYId2, ulStatus;
\r
681 portBASE_TYPE xReturn = pdPASS;
\r
683 /* Code supplied by Atmel (reformatted) -----------------*/
\r
685 /* Enable management port */
\r
686 AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;
\r
687 AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10;
\r
689 /* Read the PHY ID. */
\r
690 vReadPHY( AT91C_PHY_ADDR, MII_PHYSID1, &ulPHYId1 );
\r
691 vReadPHY(AT91C_PHY_ADDR, MII_PHYSID2, &ulPHYId2 );
\r
696 Bits 3:0 Revision Number Four bit manufacturer?s revision number.
\r
697 0001 stands for Rev. A, etc.
\r
699 if( ( ( ulPHYId1 << 16 ) | ( ulPHYId2 & 0xfff0 ) ) != MII_DM9161_ID )
\r
701 /* Did not expect this ID. */
\r
706 ulStatus = xGetLinkSpeed();
\r
708 if( ulStatus != pdPASS )
\r
714 /* Disable management port */
\r
715 AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
\r
717 /* End of code supplied by Atmel ------------------------*/
\r
721 /*-----------------------------------------------------------*/
\r
723 static void vReadPHY( unsigned char ucPHYAddress, unsigned char ucAddress, unsigned long *pulValue )
\r
725 /* Code supplied by Atmel (reformatted) ----------------------*/
\r
727 AT91C_BASE_EMAC->EMAC_MAN = (AT91C_EMAC_SOF & (0x01<<30))
\r
728 | (2 << 16) | (2 << 28)
\r
729 | ((ucPHYAddress & 0x1f) << 23)
\r
730 | (ucAddress << 18);
\r
732 /* Wait until IDLE bit in Network Status register is cleared. */
\r
733 while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) )
\r
738 *pulValue = ( AT91C_BASE_EMAC->EMAC_MAN & 0x0000ffff );
\r
740 /* End of code supplied by Atmel ------------------------*/
\r
742 /*-----------------------------------------------------------*/
\r
744 #if USE_RMII_INTERFACE != 1
\r
745 static void vWritePHY( unsigned char ucPHYAddress, unsigned char ucAddress, unsigned long ulValue )
\r
747 /* Code supplied by Atmel (reformatted) ----------------------*/
\r
749 AT91C_BASE_EMAC->EMAC_MAN = (( AT91C_EMAC_SOF & (0x01<<30))
\r
750 | (2 << 16) | (1 << 28)
\r
751 | ((ucPHYAddress & 0x1f) << 23)
\r
752 | (ucAddress << 18))
\r
753 | (ulValue & 0xffff);
\r
755 /* Wait until IDLE bit in Network Status register is cleared */
\r
756 while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) )
\r
761 /* End of code supplied by Atmel ------------------------*/
\r
764 /*-----------------------------------------------------------*/
\r
766 static portBASE_TYPE xGetLinkSpeed( void )
\r
768 unsigned long ulBMSR, ulBMCR, ulLPA, ulMACCfg, ulSpeed, ulDuplex;
\r
770 /* Code supplied by Atmel (reformatted) -----------------*/
\r
772 /* Link status is latched, so read twice to get current value */
\r
773 vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR);
\r
774 vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR);
\r
776 if( !( ulBMSR & BMSR_LSTATUS ) )
\r
782 vReadPHY(AT91C_PHY_ADDR, MII_BMCR, &ulBMCR);
\r
783 if (ulBMCR & BMCR_ANENABLE)
\r
785 /* AutoNegotiation is enabled. */
\r
786 if (!(ulBMSR & BMSR_ANEGCOMPLETE))
\r
788 /* Auto-negotitation in progress. */
\r
792 vReadPHY(AT91C_PHY_ADDR, MII_LPA, &ulLPA);
\r
793 if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_100HALF ) )
\r
795 ulSpeed = SPEED_100;
\r
799 ulSpeed = SPEED_10;
\r
802 if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_10FULL ) )
\r
804 ulDuplex = DUPLEX_FULL;
\r
808 ulDuplex = DUPLEX_HALF;
\r
813 ulSpeed = ( ulBMCR & BMCR_SPEED100 ) ? SPEED_100 : SPEED_10;
\r
814 ulDuplex = ( ulBMCR & BMCR_FULLDPLX ) ? DUPLEX_FULL : DUPLEX_HALF;
\r
817 /* Update the MAC */
\r
818 ulMACCfg = AT91C_BASE_EMAC->EMAC_NCFGR & ~( AT91C_EMAC_SPD | AT91C_EMAC_FD );
\r
819 if( ulSpeed == SPEED_100 )
\r
821 if( ulDuplex == DUPLEX_FULL )
\r
823 /* 100 Full Duplex */
\r
824 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD | AT91C_EMAC_FD;
\r
828 /* 100 Half Duplex */
\r
829 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD;
\r
834 if (ulDuplex == DUPLEX_FULL)
\r
836 /* 10 Full Duplex */
\r
837 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_FD;
\r
840 { /* 10 Half Duplex */
\r
841 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg;
\r
845 /* End of code supplied by Atmel ------------------------*/
\r
849 /*-----------------------------------------------------------*/
\r
851 void vEMACWaitForInput( void )
\r
853 /* Just wait until we are signled from an ISR that data is available, or
\r
854 we simply time out. */
\r
855 xSemaphoreTake( xSemaphore, emacBLOCK_TIME_WAITING_FOR_INPUT );
\r