2 FreeRTOS V7.2.0 - Copyright (C) 2012 Real Time Engineers Ltd.
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5 ***************************************************************************
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7 * FreeRTOS tutorial books are available in pdf and paperback. *
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8 * Complete, revised, and edited pdf reference manuals are also *
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11 * Purchasing FreeRTOS documentation will not only help you, by *
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12 * ensuring you get running as quickly as possible and with an *
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13 * in-depth knowledge of how to use FreeRTOS, it will also help *
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14 * the FreeRTOS project to continue with its mission of providing *
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15 * professional grade, cross platform, de facto standard solutions *
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16 * for microcontrollers - completely free of charge! *
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18 * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
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20 * Thank you for using FreeRTOS, and thank you for your support! *
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22 ***************************************************************************
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25 This file is part of the FreeRTOS distribution.
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27 FreeRTOS is free software; you can redistribute it and/or modify it under
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28 the terms of the GNU General Public License (version 2) as published by the
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29 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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30 >>>NOTE<<< The modification to the GPL is included to allow you to
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31 distribute a combined work that includes FreeRTOS without being obliged to
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32 provide the source code for proprietary components outside of the FreeRTOS
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33 kernel. FreeRTOS is distributed in the hope that it will be useful, but
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34 WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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35 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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36 more details. You should have received a copy of the GNU General Public
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37 License and the FreeRTOS license exception along with FreeRTOS; if not it
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38 can be viewed here: http://www.freertos.org/a00114.html and also obtained
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39 by writing to Richard Barry, contact details for whom are available on the
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44 ***************************************************************************
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46 * Having a problem? Start by reading the FAQ "My application does *
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47 * not run, what could be wrong? *
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49 * http://www.FreeRTOS.org/FAQHelp.html *
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51 ***************************************************************************
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54 http://www.FreeRTOS.org - Documentation, training, latest information,
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55 license and contact details.
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57 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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58 including FreeRTOS+Trace - an indispensable productivity tool.
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60 Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
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61 the code with commercial support, indemnification, and middleware, under
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62 the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
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63 provide a safety engineered and independently SIL3 certified version under
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64 the SafeRTOS brand: http://www.SafeRTOS.com.
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68 * Interrupt driven driver for the EMAC peripheral. This driver is not
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69 * reentrant, re-entrancy is handled by a semaphore at the network interface
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77 + Corrected the byte order when writing the MAC address to the MAC.
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78 + Support added for MII interfaces. Previously only RMII was supported.
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82 + The MII interface is now the default.
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83 + Modified the initialisation sequence slightly to allow auto init more
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88 + Made the function vClearEMACTxBuffer() more robust by moving the index
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89 manipulation into the if() statement. This allows the tx interrupt to
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90 execute even when there is no data to handle.
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94 + Corrected the Rx frame length mask when obtaining the length from the
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99 /* Standard includes. */
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100 #include <string.h>
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102 /* Scheduler includes. */
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103 #include "FreeRTOS.h"
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104 #include "semphr.h"
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107 /* Demo app includes. */
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108 #include "SAM7_EMAC.h"
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110 /* Hardware specific includes. */
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113 #include "AT91SAM7X256.h"
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116 /* USE_RMII_INTERFACE must be defined as 1 to use an RMII interface, or 0
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117 to use an MII interface. */
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118 #define USE_RMII_INTERFACE 0
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121 /* The buffer addresses written into the descriptors must be aligned so the
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122 last few bits are zero. These bits have special meaning for the EMAC
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123 peripheral and cannot be used as part of the address. */
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124 #define emacADDRESS_MASK ( ( unsigned long ) 0xFFFFFFFC )
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126 /* Bit used within the address stored in the descriptor to mark the last
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127 descriptor in the array. */
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128 #define emacRX_WRAP_BIT ( ( unsigned long ) 0x02 )
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130 /* Bit used within the Tx descriptor status to indicate whether the
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131 descriptor is under the control of the EMAC or the software. */
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132 #define emacTX_BUF_USED ( ( unsigned long ) 0x80000000 )
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134 /* A short delay is used to wait for a buffer to become available, should
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135 one not be immediately available when trying to transmit a frame. */
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136 #define emacBUFFER_WAIT_DELAY ( 2 )
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137 #define emacMAX_WAIT_CYCLES ( ( portBASE_TYPE ) ( configTICK_RATE_HZ / 40 ) )
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139 /* The time to block waiting for input. */
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140 #define emacBLOCK_TIME_WAITING_FOR_INPUT ( ( portTickType ) 100 )
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142 /* Peripheral setup for the EMAC. */
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143 #define emacPERIPHERAL_A_SETUP ( ( unsigned long ) AT91C_PB2_ETX0 ) | \
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144 ( ( unsigned long ) AT91C_PB12_ETXER ) | \
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145 ( ( unsigned long ) AT91C_PB16_ECOL ) | \
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146 ( ( unsigned long ) AT91C_PB11_ETX3 ) | \
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147 ( ( unsigned long ) AT91C_PB6_ERX1 ) | \
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148 ( ( unsigned long ) AT91C_PB15_ERXDV ) | \
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149 ( ( unsigned long ) AT91C_PB13_ERX2 ) | \
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150 ( ( unsigned long ) AT91C_PB3_ETX1 ) | \
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151 ( ( unsigned long ) AT91C_PB8_EMDC ) | \
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152 ( ( unsigned long ) AT91C_PB5_ERX0 ) | \
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153 ( ( unsigned long ) AT91C_PB14_ERX3 ) | \
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154 ( ( unsigned long ) AT91C_PB4_ECRS_ECRSDV ) | \
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155 ( ( unsigned long ) AT91C_PB1_ETXEN ) | \
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156 ( ( unsigned long ) AT91C_PB10_ETX2 ) | \
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157 ( ( unsigned long ) AT91C_PB0_ETXCK_EREFCK ) | \
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158 ( ( unsigned long ) AT91C_PB9_EMDIO ) | \
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159 ( ( unsigned long ) AT91C_PB7_ERXER ) | \
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160 ( ( unsigned long ) AT91C_PB17_ERXCK );
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162 /* Misc defines. */
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163 #define emacINTERRUPT_LEVEL ( 5 )
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164 #define emacNO_DELAY ( 0 )
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165 #define emacTOTAL_FRAME_HEADER_SIZE ( 54 )
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166 #define emacPHY_INIT_DELAY ( 5000 / portTICK_RATE_MS )
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167 #define emacRESET_KEY ( ( unsigned long ) 0xA5000000 )
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168 #define emacRESET_LENGTH ( ( unsigned long ) ( 0x01 << 8 ) )
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170 /* The Atmel header file only defines the TX frame length mask. */
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171 #define emacRX_LENGTH_FRAME ( 0xfff )
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173 /*-----------------------------------------------------------*/
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175 /* Buffer written to by the EMAC DMA. Must be aligned as described by the
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176 comment above the emacADDRESS_MASK definition. */
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177 static volatile char pcRxBuffer[ NB_RX_BUFFERS * ETH_RX_BUFFER_SIZE ] __attribute__ ((aligned (8)));
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179 /* Buffer read by the EMAC DMA. Must be aligned as described by the comment
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180 above the emacADDRESS_MASK definition. */
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181 static char pcTxBuffer[ NB_TX_BUFFERS * ETH_TX_BUFFER_SIZE ] __attribute__ ((aligned (8)));
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183 /* Descriptors used to communicate between the program and the EMAC peripheral.
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184 These descriptors hold the locations and state of the Rx and Tx buffers. */
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185 static volatile AT91S_TxTdDescriptor xTxDescriptors[ NB_TX_BUFFERS ];
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186 static volatile AT91S_RxTdDescriptor xRxDescriptors[ NB_RX_BUFFERS ];
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188 /* The IP and Ethernet addresses are read from the header files. */
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189 const char cMACAddress[ 6 ] = { emacETHADDR0, emacETHADDR1, emacETHADDR2, emacETHADDR3, emacETHADDR4, emacETHADDR5 };
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190 const unsigned char ucIPAddress[ 4 ] = { emacIPADDR0, emacIPADDR1, emacIPADDR2, emacIPADDR3 };
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192 /*-----------------------------------------------------------*/
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194 /* See the header file for descriptions of public functions. */
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197 * Prototype for the EMAC interrupt function.
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199 void vEMACISR_Wrapper( void ) __attribute__ ((naked));
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202 * Initialise both the Tx and Rx descriptors used by the EMAC.
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204 static void prvSetupDescriptors(void);
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207 * Write our MAC address into the EMAC.
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209 static void prvSetupMACAddress( void );
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212 * Configure the EMAC and AIC for EMAC interrupts.
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214 static void prvSetupEMACInterrupt( void );
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217 * Some initialisation functions taken from the Atmel EMAC sample code.
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219 static void vReadPHY( unsigned char ucPHYAddress, unsigned char ucAddress, unsigned long *pulValue );
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220 static portBASE_TYPE xGetLinkSpeed( void );
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221 static portBASE_TYPE prvProbePHY( void );
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222 #if USE_RMII_INTERFACE != 1
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223 static void vWritePHY( unsigned char ucPHYAddress, unsigned char ucAddress, unsigned long ulValue);
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227 /* The semaphore used by the EMAC ISR to wake the EMAC task. */
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228 static xSemaphoreHandle xSemaphore = NULL;
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230 /* Holds the index to the next buffer from which data will be read. */
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231 static volatile unsigned long ulNextRxBuffer = 0;
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233 /*-----------------------------------------------------------*/
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235 /* See the header file for descriptions of public functions. */
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236 long lEMACSend( char *pcFrom, unsigned long ulLength, long lEndOfFrame )
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238 static unsigned portBASE_TYPE uxTxBufferIndex = 0;
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239 portBASE_TYPE xWaitCycles = 0;
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240 long lReturn = pdPASS;
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242 unsigned long ulLastBuffer, ulDataBuffered = 0, ulDataRemainingToSend, ulLengthToSend;
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244 /* If the length of data to be transmitted is greater than each individual
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245 transmit buffer then the data will be split into more than one buffer.
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246 Loop until the entire length has been buffered. */
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247 while( ulDataBuffered < ulLength )
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249 /* Is a buffer available? */
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250 while( !( xTxDescriptors[ uxTxBufferIndex ].U_Status.status & AT91C_TRANSMIT_OK ) )
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252 /* There is no room to write the Tx data to the Tx buffer. Wait a
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253 short while, then try again. */
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255 if( xWaitCycles > emacMAX_WAIT_CYCLES )
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263 vTaskDelay( emacBUFFER_WAIT_DELAY );
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267 /* lReturn will only be pdPASS if a buffer is available. */
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268 if( lReturn == pdPASS )
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270 portENTER_CRITICAL();
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272 /* Get the address of the buffer from the descriptor, then copy
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273 the data into the buffer. */
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274 pcBuffer = ( char * ) xTxDescriptors[ uxTxBufferIndex ].addr;
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276 /* How much can we write to the buffer? */
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277 ulDataRemainingToSend = ulLength - ulDataBuffered;
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278 if( ulDataRemainingToSend <= ETH_TX_BUFFER_SIZE )
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280 /* We can write all the remaining bytes. */
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281 ulLengthToSend = ulDataRemainingToSend;
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285 /* We can not write more than ETH_TX_BUFFER_SIZE in one go. */
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286 ulLengthToSend = ETH_TX_BUFFER_SIZE;
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289 /* Copy the data into the buffer. */
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290 memcpy( ( void * ) pcBuffer, ( void * ) &( pcFrom[ ulDataBuffered ] ), ulLengthToSend );
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291 ulDataBuffered += ulLengthToSend;
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293 /* Is this the last data for the frame? */
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294 if( lEndOfFrame && ( ulDataBuffered >= ulLength ) )
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296 /* No more data remains for this frame so we can start the
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298 ulLastBuffer = AT91C_LAST_BUFFER;
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302 /* More data to come for this frame. */
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306 /* Fill out the necessary in the descriptor to get the data sent,
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307 then move to the next descriptor, wrapping if necessary. */
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308 if( uxTxBufferIndex >= ( NB_TX_BUFFERS - 1 ) )
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310 xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( ulLengthToSend & ( unsigned long ) AT91C_LENGTH_FRAME )
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312 | AT91C_TRANSMIT_WRAP;
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313 uxTxBufferIndex = 0;
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317 xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( ulLengthToSend & ( unsigned long ) AT91C_LENGTH_FRAME )
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322 /* If this is the last buffer to be sent for this frame we can
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323 start the transmission. */
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326 AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TSTART;
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329 portEXIT_CRITICAL();
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339 /*-----------------------------------------------------------*/
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341 /* See the header file for descriptions of public functions. */
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342 unsigned long ulEMACInputLength( void )
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344 register unsigned long ulIndex, ulLength = 0;
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346 /* Skip any fragments. We are looking for the first buffer that contains
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347 data and has the SOF (start of frame) bit set. */
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348 while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AT91C_OWNERSHIP_BIT ) && !( xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AT91C_SOF ) )
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350 /* Ignoring this buffer. Mark it as free again. */
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351 xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );
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353 if( ulNextRxBuffer >= NB_RX_BUFFERS )
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355 ulNextRxBuffer = 0;
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359 /* We are going to walk through the descriptors that make up this frame,
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360 but don't want to alter ulNextRxBuffer as this would prevent vEMACRead()
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361 from finding the data. Therefore use a copy of ulNextRxBuffer instead. */
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362 ulIndex = ulNextRxBuffer;
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364 /* Walk through the descriptors until we find the last buffer for this
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365 frame. The last buffer will give us the length of the entire frame. */
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366 while( ( xRxDescriptors[ ulIndex ].addr & AT91C_OWNERSHIP_BIT ) && !ulLength )
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368 ulLength = xRxDescriptors[ ulIndex ].U_Status.status & emacRX_LENGTH_FRAME;
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370 /* Increment to the next buffer, wrapping if necessary. */
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372 if( ulIndex >= NB_RX_BUFFERS )
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380 /*-----------------------------------------------------------*/
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382 /* See the header file for descriptions of public functions. */
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383 void vEMACRead( char *pcTo, unsigned long ulSectionLength, unsigned long ulTotalFrameLength )
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385 static unsigned long ulSectionBytesReadSoFar = 0, ulBufferPosition = 0, ulFameBytesReadSoFar = 0;
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386 static char *pcSource;
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387 register unsigned long ulBytesRemainingInBuffer, ulRemainingSectionBytes;
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389 /* Read ulSectionLength bytes from the Rx buffers. This is not necessarily any
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390 correspondence between the length of our Rx buffers, and the length of the
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391 data we are returning or the length of the data being requested. Therefore,
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392 between calls we have to remember not only which buffer we are currently
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393 processing, but our position within that buffer. This would be greatly
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394 simplified if PBUF_POOL_BUFSIZE could be guaranteed to be greater than
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395 the size of each Rx buffer, and that memory fragmentation did not occur.
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397 This function should only be called after a call to ulEMACInputLength().
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398 This will ensure ulNextRxBuffer is set to the correct buffer. */
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402 /* vEMACRead is called with pcTo set to NULL to indicate that we are about
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403 to read a new frame. Any fragments remaining in the frame we were
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404 processing during the last call should be dropped. */
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407 /* How many bytes are indicated as being in this buffer? If none then
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408 the buffer is completely full and the frame is contained within more
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409 than one buffer. */
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411 /* Reset our state variables ready for the next read from this buffer. */
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412 pcSource = ( char * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );
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413 ulFameBytesReadSoFar = ( unsigned long ) 0;
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414 ulBufferPosition = ( unsigned long ) 0;
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418 /* Loop until we have obtained the required amount of data. */
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419 ulSectionBytesReadSoFar = 0;
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420 while( ulSectionBytesReadSoFar < ulSectionLength )
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422 /* We may have already read some data from this buffer. How much
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423 data remains in the buffer? */
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424 ulBytesRemainingInBuffer = ( ETH_RX_BUFFER_SIZE - ulBufferPosition );
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426 /* How many more bytes do we need to read before we have the
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427 required amount of data? */
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428 ulRemainingSectionBytes = ulSectionLength - ulSectionBytesReadSoFar;
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430 /* Do we want more data than remains in the buffer? */
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431 if( ulRemainingSectionBytes > ulBytesRemainingInBuffer )
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433 /* We want more data than remains in the buffer so we can
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434 write the remains of the buffer to the destination, then move
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435 onto the next buffer to get the rest. */
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436 memcpy( &( pcTo[ ulSectionBytesReadSoFar ] ), &( pcSource[ ulBufferPosition ] ), ulBytesRemainingInBuffer );
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437 ulSectionBytesReadSoFar += ulBytesRemainingInBuffer;
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438 ulFameBytesReadSoFar += ulBytesRemainingInBuffer;
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440 /* Mark the buffer as free again. */
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441 xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );
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443 /* Move onto the next buffer. */
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445 if( ulNextRxBuffer >= NB_RX_BUFFERS )
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447 ulNextRxBuffer = ( unsigned long ) 0;
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450 /* Reset the variables for the new buffer. */
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451 pcSource = ( char * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );
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452 ulBufferPosition = ( unsigned long ) 0;
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456 /* We have enough data in this buffer to send back. Read out
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457 enough data and remember how far we read up to. */
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458 memcpy( &( pcTo[ ulSectionBytesReadSoFar ] ), &( pcSource[ ulBufferPosition ] ), ulRemainingSectionBytes );
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460 /* There may be more data in this buffer yet. Increment our
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461 position in this buffer past the data we have just read. */
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462 ulBufferPosition += ulRemainingSectionBytes;
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463 ulSectionBytesReadSoFar += ulRemainingSectionBytes;
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464 ulFameBytesReadSoFar += ulRemainingSectionBytes;
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466 /* Have we now finished with this buffer? */
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467 if( ( ulBufferPosition >= ETH_RX_BUFFER_SIZE ) || ( ulFameBytesReadSoFar >= ulTotalFrameLength ) )
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469 /* Mark the buffer as free again. */
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470 xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );
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472 /* Move onto the next buffer. */
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474 if( ulNextRxBuffer >= NB_RX_BUFFERS )
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476 ulNextRxBuffer = 0;
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479 pcSource = ( char * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );
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480 ulBufferPosition = 0;
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486 /*-----------------------------------------------------------*/
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488 /* See the header file for descriptions of public functions. */
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489 xSemaphoreHandle xEMACInit( void )
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491 /* Code supplied by Atmel -------------------------------*/
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493 /* Disable pull up on RXDV => PHY normal mode (not in test mode),
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494 PHY has internal pull down. */
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495 AT91C_BASE_PIOB->PIO_PPUDR = 1 << 15;
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497 #if USE_RMII_INTERFACE != 1
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498 /* PHY has internal pull down : set MII mode. */
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499 AT91C_BASE_PIOB->PIO_PPUDR = 1 << 16;
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502 /* Clear PB18 <=> PHY powerdown. */
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503 AT91C_BASE_PIOB->PIO_PER = 1 << 18;
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504 AT91C_BASE_PIOB->PIO_OER = 1 << 18;
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505 AT91C_BASE_PIOB->PIO_CODR = 1 << 18;
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507 /* After PHY power up, hardware reset. */
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508 AT91C_BASE_RSTC->RSTC_RMR = emacRESET_KEY | emacRESET_LENGTH;
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509 AT91C_BASE_RSTC->RSTC_RCR = emacRESET_KEY | AT91C_RSTC_EXTRST;
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511 /* Wait for hardware reset end. */
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512 while( !( AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL ) )
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514 __asm volatile ( "NOP" );
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516 __asm volatile ( "NOP" );
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518 /* Setup the pins. */
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519 AT91C_BASE_PIOB->PIO_ASR = emacPERIPHERAL_A_SETUP;
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520 AT91C_BASE_PIOB->PIO_PDR = emacPERIPHERAL_A_SETUP;
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522 /* Enable com between EMAC PHY.
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524 Enable management port. */
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525 AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;
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527 /* MDC = MCK/32. */
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528 AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10;
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530 /* Wait for PHY auto init end (rather crude delay!). */
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531 vTaskDelay( emacPHY_INIT_DELAY );
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533 /* PHY configuration. */
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534 #if USE_RMII_INTERFACE != 1
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536 unsigned long ulControl;
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538 /* PHY has internal pull down : disable MII isolate. */
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539 vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl );
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540 vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl );
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541 ulControl &= ~BMCR_ISOLATE;
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542 vWritePHY( AT91C_PHY_ADDR, MII_BMCR, ulControl );
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546 /* Disable management port again. */
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547 AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
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549 #if USE_RMII_INTERFACE != 1
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550 /* Enable EMAC in MII mode, enable clock ERXCK and ETXCK. */
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551 AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_CLKEN ;
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553 /* Enable EMAC in RMII mode, enable RMII clock (50MHz from oscillator
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555 AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_RMII | AT91C_EMAC_CLKEN ;
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558 /* End of code supplied by Atmel ------------------------*/
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560 /* Setup the buffers and descriptors. */
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561 prvSetupDescriptors();
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563 /* Load our MAC address into the EMAC. */
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564 prvSetupMACAddress();
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566 /* Are we connected? */
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567 if( prvProbePHY() )
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569 /* Enable the interrupt! */
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570 portENTER_CRITICAL();
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572 prvSetupEMACInterrupt();
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573 vPassEMACSemaphore( xSemaphore );
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575 portEXIT_CRITICAL();
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580 /*-----------------------------------------------------------*/
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582 /* See the header file for descriptions of public functions. */
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583 void vClearEMACTxBuffer( void )
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585 static unsigned portBASE_TYPE uxNextBufferToClear = 0;
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587 /* Called on Tx interrupt events to reset the AT91C_TRANSMIT_OK bit in each
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588 Tx buffer within the frame just transmitted. This marks all the buffers
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589 as available again.
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591 The first buffer in the frame should have the bit set automatically. */
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592 if( xTxDescriptors[ uxNextBufferToClear ].U_Status.status & AT91C_TRANSMIT_OK )
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594 /* Loop through the other buffers in the frame. */
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595 while( !( xTxDescriptors[ uxNextBufferToClear ].U_Status.status & AT91C_LAST_BUFFER ) )
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597 uxNextBufferToClear++;
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599 if( uxNextBufferToClear >= NB_TX_BUFFERS )
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601 uxNextBufferToClear = 0;
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604 xTxDescriptors[ uxNextBufferToClear ].U_Status.status |= AT91C_TRANSMIT_OK;
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607 /* Start with the next buffer the next time a Tx interrupt is called. */
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608 uxNextBufferToClear++;
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610 /* Do we need to wrap back to the first buffer? */
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611 if( uxNextBufferToClear >= NB_TX_BUFFERS )
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613 uxNextBufferToClear = 0;
\r
617 /*-----------------------------------------------------------*/
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619 static void prvSetupDescriptors(void)
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621 unsigned portBASE_TYPE xIndex;
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622 unsigned long ulAddress;
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624 /* Initialise xRxDescriptors descriptor. */
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625 for( xIndex = 0; xIndex < NB_RX_BUFFERS; ++xIndex )
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627 /* Calculate the address of the nth buffer within the array. */
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628 ulAddress = ( unsigned long )( pcRxBuffer + ( xIndex * ETH_RX_BUFFER_SIZE ) );
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630 /* Write the buffer address into the descriptor. The DMA will place
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631 the data at this address when this descriptor is being used. Mask off
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632 the bottom bits of the address as these have special meaning. */
\r
633 xRxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;
\r
636 /* The last buffer has the wrap bit set so the EMAC knows to wrap back
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637 to the first buffer. */
\r
638 xRxDescriptors[ NB_RX_BUFFERS - 1 ].addr |= emacRX_WRAP_BIT;
\r
640 /* Initialise xTxDescriptors. */
\r
641 for( xIndex = 0; xIndex < NB_TX_BUFFERS; ++xIndex )
\r
643 /* Calculate the address of the nth buffer within the array. */
\r
644 ulAddress = ( unsigned long )( pcTxBuffer + ( xIndex * ETH_TX_BUFFER_SIZE ) );
\r
646 /* Write the buffer address into the descriptor. The DMA will read
\r
647 data from here when the descriptor is being used. */
\r
648 xTxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;
\r
649 xTxDescriptors[ xIndex ].U_Status.status = AT91C_TRANSMIT_OK;
\r
652 /* The last buffer has the wrap bit set so the EMAC knows to wrap back
\r
653 to the first buffer. */
\r
654 xTxDescriptors[ NB_TX_BUFFERS - 1 ].U_Status.status = AT91C_TRANSMIT_WRAP | AT91C_TRANSMIT_OK;
\r
656 /* Tell the EMAC where to find the descriptors. */
\r
657 AT91C_BASE_EMAC->EMAC_RBQP = ( unsigned long ) xRxDescriptors;
\r
658 AT91C_BASE_EMAC->EMAC_TBQP = ( unsigned long ) xTxDescriptors;
\r
660 /* Clear all the bits in the receive status register. */
\r
661 AT91C_BASE_EMAC->EMAC_RSR = ( AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA );
\r
663 /* Enable the copy of data into the buffers, ignore broadcasts,
\r
664 and don't copy FCS. */
\r
665 AT91C_BASE_EMAC->EMAC_NCFGR |= ( AT91C_EMAC_CAF | AT91C_EMAC_NBC | AT91C_EMAC_DRFCS);
\r
667 /* Enable Rx and Tx, plus the stats register. */
\r
668 AT91C_BASE_EMAC->EMAC_NCR |= ( AT91C_EMAC_TE | AT91C_EMAC_RE | AT91C_EMAC_WESTAT );
\r
670 /*-----------------------------------------------------------*/
\r
672 static void prvSetupMACAddress( void )
\r
674 /* Must be written SA1L then SA1H. */
\r
675 AT91C_BASE_EMAC->EMAC_SA1L = ( ( unsigned long ) cMACAddress[ 3 ] << 24 ) |
\r
676 ( ( unsigned long ) cMACAddress[ 2 ] << 16 ) |
\r
677 ( ( unsigned long ) cMACAddress[ 1 ] << 8 ) |
\r
680 AT91C_BASE_EMAC->EMAC_SA1H = ( ( unsigned long ) cMACAddress[ 5 ] << 8 ) |
\r
683 /*-----------------------------------------------------------*/
\r
685 static void prvSetupEMACInterrupt( void )
\r
687 /* Create the semaphore used to trigger the EMAC task. */
\r
688 vSemaphoreCreateBinary( xSemaphore );
\r
691 /* We start by 'taking' the semaphore so the ISR can 'give' it when the
\r
692 first interrupt occurs. */
\r
693 xSemaphoreTake( xSemaphore, emacNO_DELAY );
\r
694 portENTER_CRITICAL();
\r
696 /* We want to interrupt on Rx and Tx events. */
\r
697 AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_RCOMP | AT91C_EMAC_TCOMP;
\r
699 /* Enable the interrupts in the AIC. */
\r
700 AT91F_AIC_ConfigureIt( AT91C_ID_EMAC, emacINTERRUPT_LEVEL, AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, ( void (*)( void ) ) vEMACISR_Wrapper );
\r
701 AT91C_BASE_AIC->AIC_IECR = 0x1 << AT91C_ID_EMAC;
\r
703 portEXIT_CRITICAL();
\r
712 * The following functions are initialisation functions taken from the Atmel
\r
713 * EMAC sample code.
\r
717 static portBASE_TYPE prvProbePHY( void )
\r
719 unsigned long ulPHYId1, ulPHYId2, ulStatus;
\r
720 portBASE_TYPE xReturn = pdPASS;
\r
722 /* Code supplied by Atmel (reformatted) -----------------*/
\r
724 /* Enable management port */
\r
725 AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;
\r
726 AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10;
\r
728 /* Read the PHY ID. */
\r
729 vReadPHY( AT91C_PHY_ADDR, MII_PHYSID1, &ulPHYId1 );
\r
730 vReadPHY(AT91C_PHY_ADDR, MII_PHYSID2, &ulPHYId2 );
\r
735 Bits 3:0 Revision Number Four bit manufacturer?s revision number.
\r
736 0001 stands for Rev. A, etc.
\r
738 if( ( ( ulPHYId1 << 16 ) | ( ulPHYId2 & 0xfff0 ) ) != MII_DM9161_ID )
\r
740 /* Did not expect this ID. */
\r
745 ulStatus = xGetLinkSpeed();
\r
747 if( ulStatus != pdPASS )
\r
753 /* Disable management port */
\r
754 AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
\r
756 /* End of code supplied by Atmel ------------------------*/
\r
760 /*-----------------------------------------------------------*/
\r
762 static void vReadPHY( unsigned char ucPHYAddress, unsigned char ucAddress, unsigned long *pulValue )
\r
764 /* Code supplied by Atmel (reformatted) ----------------------*/
\r
766 AT91C_BASE_EMAC->EMAC_MAN = (AT91C_EMAC_SOF & (0x01<<30))
\r
767 | (2 << 16) | (2 << 28)
\r
768 | ((ucPHYAddress & 0x1f) << 23)
\r
769 | (ucAddress << 18);
\r
771 /* Wait until IDLE bit in Network Status register is cleared. */
\r
772 while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) )
\r
777 *pulValue = ( AT91C_BASE_EMAC->EMAC_MAN & 0x0000ffff );
\r
779 /* End of code supplied by Atmel ------------------------*/
\r
781 /*-----------------------------------------------------------*/
\r
783 #if USE_RMII_INTERFACE != 1
\r
784 static void vWritePHY( unsigned char ucPHYAddress, unsigned char ucAddress, unsigned long ulValue )
\r
786 /* Code supplied by Atmel (reformatted) ----------------------*/
\r
788 AT91C_BASE_EMAC->EMAC_MAN = (( AT91C_EMAC_SOF & (0x01<<30))
\r
789 | (2 << 16) | (1 << 28)
\r
790 | ((ucPHYAddress & 0x1f) << 23)
\r
791 | (ucAddress << 18))
\r
792 | (ulValue & 0xffff);
\r
794 /* Wait until IDLE bit in Network Status register is cleared */
\r
795 while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) )
\r
800 /* End of code supplied by Atmel ------------------------*/
\r
803 /*-----------------------------------------------------------*/
\r
805 static portBASE_TYPE xGetLinkSpeed( void )
\r
807 unsigned long ulBMSR, ulBMCR, ulLPA, ulMACCfg, ulSpeed, ulDuplex;
\r
809 /* Code supplied by Atmel (reformatted) -----------------*/
\r
811 /* Link status is latched, so read twice to get current value */
\r
812 vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR);
\r
813 vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR);
\r
815 if( !( ulBMSR & BMSR_LSTATUS ) )
\r
821 vReadPHY(AT91C_PHY_ADDR, MII_BMCR, &ulBMCR);
\r
822 if (ulBMCR & BMCR_ANENABLE)
\r
824 /* AutoNegotiation is enabled. */
\r
825 if (!(ulBMSR & BMSR_ANEGCOMPLETE))
\r
827 /* Auto-negotitation in progress. */
\r
831 vReadPHY(AT91C_PHY_ADDR, MII_LPA, &ulLPA);
\r
832 if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_100HALF ) )
\r
834 ulSpeed = SPEED_100;
\r
838 ulSpeed = SPEED_10;
\r
841 if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_10FULL ) )
\r
843 ulDuplex = DUPLEX_FULL;
\r
847 ulDuplex = DUPLEX_HALF;
\r
852 ulSpeed = ( ulBMCR & BMCR_SPEED100 ) ? SPEED_100 : SPEED_10;
\r
853 ulDuplex = ( ulBMCR & BMCR_FULLDPLX ) ? DUPLEX_FULL : DUPLEX_HALF;
\r
856 /* Update the MAC */
\r
857 ulMACCfg = AT91C_BASE_EMAC->EMAC_NCFGR & ~( AT91C_EMAC_SPD | AT91C_EMAC_FD );
\r
858 if( ulSpeed == SPEED_100 )
\r
860 if( ulDuplex == DUPLEX_FULL )
\r
862 /* 100 Full Duplex */
\r
863 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD | AT91C_EMAC_FD;
\r
867 /* 100 Half Duplex */
\r
868 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD;
\r
873 if (ulDuplex == DUPLEX_FULL)
\r
875 /* 10 Full Duplex */
\r
876 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_FD;
\r
879 { /* 10 Half Duplex */
\r
880 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg;
\r
884 /* End of code supplied by Atmel ------------------------*/
\r
888 /*-----------------------------------------------------------*/
\r
890 void vEMACWaitForInput( void )
\r
892 /* Just wait until we are signled from an ISR that data is available, or
\r
893 we simply time out. */
\r
894 xSemaphoreTake( xSemaphore, emacBLOCK_TIME_WAITING_FOR_INPUT );
\r
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