2 FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.
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5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 This file is part of the FreeRTOS distribution.
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9 FreeRTOS is free software; you can redistribute it and/or modify it under
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10 the terms of the GNU General Public License (version 2) as published by the
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11 Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
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13 ***************************************************************************
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14 >>! NOTE: The modification to the GPL is included to allow you to !<<
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15 >>! distribute a combined work that includes FreeRTOS without being !<<
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16 >>! obliged to provide the source code for proprietary components !<<
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17 >>! outside of the FreeRTOS kernel. !<<
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18 ***************************************************************************
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20 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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21 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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22 FOR A PARTICULAR PURPOSE. Full license text is available on the following
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23 link: http://www.freertos.org/a00114.html
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25 ***************************************************************************
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27 * FreeRTOS provides completely free yet professionally developed, *
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28 * robust, strictly quality controlled, supported, and cross *
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29 * platform software that is more than just the market leader, it *
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30 * is the industry's de facto standard. *
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32 * Help yourself get started quickly while simultaneously helping *
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33 * to support the FreeRTOS project by purchasing a FreeRTOS *
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34 * tutorial book, reference manual, or both: *
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35 * http://www.FreeRTOS.org/Documentation *
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37 ***************************************************************************
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39 http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
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40 the FAQ page "My application does not run, what could be wrong?". Have you
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41 defined configASSERT()?
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43 http://www.FreeRTOS.org/support - In return for receiving this top quality
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44 embedded software for free we request you assist our global community by
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45 participating in the support forum.
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47 http://www.FreeRTOS.org/training - Investing in training allows your team to
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48 be as productive as possible as early as possible. Now you can receive
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49 FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
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50 Ltd, and the world's leading authority on the world's leading RTOS.
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52 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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53 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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54 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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56 http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
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57 Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
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59 http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
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60 Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
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61 licenses offer ticketed support, indemnification and commercial middleware.
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63 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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64 engineered and independently SIL3 certified version for use in safety and
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65 mission critical applications that require provable dependability.
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71 * Interrupt driven driver for the EMAC peripheral. This driver is not
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72 * reentrant, re-entrancy is handled by a semaphore at the network interface
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80 + Corrected the byte order when writing the MAC address to the MAC.
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81 + Support added for MII interfaces. Previously only RMII was supported.
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85 + The MII interface is now the default.
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86 + Modified the initialisation sequence slightly to allow auto init more
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91 + Made the function vClearEMACTxBuffer() more robust by moving the index
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92 manipulation into the if() statement. This allows the tx interrupt to
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93 execute even when there is no data to handle.
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97 + Corrected the Rx frame length mask when obtaining the length from the
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102 /* Standard includes. */
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103 #include <string.h>
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105 /* Scheduler includes. */
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106 #include "FreeRTOS.h"
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107 #include "semphr.h"
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110 /* Demo app includes. */
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111 #include "SAM7_EMAC.h"
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113 /* Hardware specific includes. */
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116 #include "AT91SAM7X256.h"
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119 /* USE_RMII_INTERFACE must be defined as 1 to use an RMII interface, or 0
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120 to use an MII interface. */
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121 #define USE_RMII_INTERFACE 0
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124 /* The buffer addresses written into the descriptors must be aligned so the
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125 last few bits are zero. These bits have special meaning for the EMAC
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126 peripheral and cannot be used as part of the address. */
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127 #define emacADDRESS_MASK ( ( unsigned long ) 0xFFFFFFFC )
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129 /* Bit used within the address stored in the descriptor to mark the last
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130 descriptor in the array. */
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131 #define emacRX_WRAP_BIT ( ( unsigned long ) 0x02 )
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133 /* Bit used within the Tx descriptor status to indicate whether the
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134 descriptor is under the control of the EMAC or the software. */
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135 #define emacTX_BUF_USED ( ( unsigned long ) 0x80000000 )
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137 /* A short delay is used to wait for a buffer to become available, should
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138 one not be immediately available when trying to transmit a frame. */
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139 #define emacBUFFER_WAIT_DELAY ( 2 )
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140 #define emacMAX_WAIT_CYCLES ( ( portBASE_TYPE ) ( configTICK_RATE_HZ / 40 ) )
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142 /* The time to block waiting for input. */
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143 #define emacBLOCK_TIME_WAITING_FOR_INPUT ( ( TickType_t ) 100 )
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145 /* Peripheral setup for the EMAC. */
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146 #define emacPERIPHERAL_A_SETUP ( ( unsigned long ) AT91C_PB2_ETX0 ) | \
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147 ( ( unsigned long ) AT91C_PB12_ETXER ) | \
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148 ( ( unsigned long ) AT91C_PB16_ECOL ) | \
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149 ( ( unsigned long ) AT91C_PB11_ETX3 ) | \
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150 ( ( unsigned long ) AT91C_PB6_ERX1 ) | \
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151 ( ( unsigned long ) AT91C_PB15_ERXDV ) | \
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152 ( ( unsigned long ) AT91C_PB13_ERX2 ) | \
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153 ( ( unsigned long ) AT91C_PB3_ETX1 ) | \
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154 ( ( unsigned long ) AT91C_PB8_EMDC ) | \
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155 ( ( unsigned long ) AT91C_PB5_ERX0 ) | \
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156 ( ( unsigned long ) AT91C_PB14_ERX3 ) | \
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157 ( ( unsigned long ) AT91C_PB4_ECRS_ECRSDV ) | \
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158 ( ( unsigned long ) AT91C_PB1_ETXEN ) | \
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159 ( ( unsigned long ) AT91C_PB10_ETX2 ) | \
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160 ( ( unsigned long ) AT91C_PB0_ETXCK_EREFCK ) | \
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161 ( ( unsigned long ) AT91C_PB9_EMDIO ) | \
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162 ( ( unsigned long ) AT91C_PB7_ERXER ) | \
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163 ( ( unsigned long ) AT91C_PB17_ERXCK );
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165 /* Misc defines. */
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166 #define emacINTERRUPT_LEVEL ( 5 )
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167 #define emacNO_DELAY ( 0 )
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168 #define emacTOTAL_FRAME_HEADER_SIZE ( 54 )
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169 #define emacPHY_INIT_DELAY ( 5000 / portTICK_PERIOD_MS )
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170 #define emacRESET_KEY ( ( unsigned long ) 0xA5000000 )
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171 #define emacRESET_LENGTH ( ( unsigned long ) ( 0x01 << 8 ) )
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173 /* The Atmel header file only defines the TX frame length mask. */
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174 #define emacRX_LENGTH_FRAME ( 0xfff )
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176 /*-----------------------------------------------------------*/
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178 /* Buffer written to by the EMAC DMA. Must be aligned as described by the
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179 comment above the emacADDRESS_MASK definition. */
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180 static volatile char pcRxBuffer[ NB_RX_BUFFERS * ETH_RX_BUFFER_SIZE ] __attribute__ ((aligned (8)));
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182 /* Buffer read by the EMAC DMA. Must be aligned as described by the comment
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183 above the emacADDRESS_MASK definition. */
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184 static char pcTxBuffer[ NB_TX_BUFFERS * ETH_TX_BUFFER_SIZE ] __attribute__ ((aligned (8)));
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186 /* Descriptors used to communicate between the program and the EMAC peripheral.
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187 These descriptors hold the locations and state of the Rx and Tx buffers. */
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188 static volatile AT91S_TxTdDescriptor xTxDescriptors[ NB_TX_BUFFERS ];
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189 static volatile AT91S_RxTdDescriptor xRxDescriptors[ NB_RX_BUFFERS ];
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191 /* The IP and Ethernet addresses are read from the header files. */
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192 const char cMACAddress[ 6 ] = { emacETHADDR0, emacETHADDR1, emacETHADDR2, emacETHADDR3, emacETHADDR4, emacETHADDR5 };
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193 const unsigned char ucIPAddress[ 4 ] = { emacIPADDR0, emacIPADDR1, emacIPADDR2, emacIPADDR3 };
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195 /*-----------------------------------------------------------*/
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197 /* See the header file for descriptions of public functions. */
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200 * Prototype for the EMAC interrupt function.
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202 void vEMACISR_Wrapper( void ) __attribute__ ((naked));
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205 * Initialise both the Tx and Rx descriptors used by the EMAC.
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207 static void prvSetupDescriptors(void);
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210 * Write our MAC address into the EMAC.
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212 static void prvSetupMACAddress( void );
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215 * Configure the EMAC and AIC for EMAC interrupts.
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217 static void prvSetupEMACInterrupt( void );
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220 * Some initialisation functions taken from the Atmel EMAC sample code.
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222 static void vReadPHY( unsigned char ucPHYAddress, unsigned char ucAddress, unsigned long *pulValue );
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223 static portBASE_TYPE xGetLinkSpeed( void );
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224 static portBASE_TYPE prvProbePHY( void );
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225 #if USE_RMII_INTERFACE != 1
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226 static void vWritePHY( unsigned char ucPHYAddress, unsigned char ucAddress, unsigned long ulValue);
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230 /* The semaphore used by the EMAC ISR to wake the EMAC task. */
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231 static SemaphoreHandle_t xSemaphore = NULL;
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233 /* Holds the index to the next buffer from which data will be read. */
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234 static volatile unsigned long ulNextRxBuffer = 0;
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236 /*-----------------------------------------------------------*/
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238 /* See the header file for descriptions of public functions. */
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239 long lEMACSend( char *pcFrom, unsigned long ulLength, long lEndOfFrame )
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241 static unsigned portBASE_TYPE uxTxBufferIndex = 0;
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242 portBASE_TYPE xWaitCycles = 0;
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243 long lReturn = pdPASS;
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245 unsigned long ulLastBuffer, ulDataBuffered = 0, ulDataRemainingToSend, ulLengthToSend;
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247 /* If the length of data to be transmitted is greater than each individual
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248 transmit buffer then the data will be split into more than one buffer.
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249 Loop until the entire length has been buffered. */
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250 while( ulDataBuffered < ulLength )
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252 /* Is a buffer available? */
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253 while( !( xTxDescriptors[ uxTxBufferIndex ].U_Status.status & AT91C_TRANSMIT_OK ) )
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255 /* There is no room to write the Tx data to the Tx buffer. Wait a
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256 short while, then try again. */
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258 if( xWaitCycles > emacMAX_WAIT_CYCLES )
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266 vTaskDelay( emacBUFFER_WAIT_DELAY );
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270 /* lReturn will only be pdPASS if a buffer is available. */
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271 if( lReturn == pdPASS )
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273 portENTER_CRITICAL();
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275 /* Get the address of the buffer from the descriptor, then copy
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276 the data into the buffer. */
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277 pcBuffer = ( char * ) xTxDescriptors[ uxTxBufferIndex ].addr;
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279 /* How much can we write to the buffer? */
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280 ulDataRemainingToSend = ulLength - ulDataBuffered;
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281 if( ulDataRemainingToSend <= ETH_TX_BUFFER_SIZE )
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283 /* We can write all the remaining bytes. */
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284 ulLengthToSend = ulDataRemainingToSend;
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288 /* We can not write more than ETH_TX_BUFFER_SIZE in one go. */
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289 ulLengthToSend = ETH_TX_BUFFER_SIZE;
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292 /* Copy the data into the buffer. */
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293 memcpy( ( void * ) pcBuffer, ( void * ) &( pcFrom[ ulDataBuffered ] ), ulLengthToSend );
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294 ulDataBuffered += ulLengthToSend;
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296 /* Is this the last data for the frame? */
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297 if( lEndOfFrame && ( ulDataBuffered >= ulLength ) )
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299 /* No more data remains for this frame so we can start the
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301 ulLastBuffer = AT91C_LAST_BUFFER;
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305 /* More data to come for this frame. */
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309 /* Fill out the necessary in the descriptor to get the data sent,
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310 then move to the next descriptor, wrapping if necessary. */
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311 if( uxTxBufferIndex >= ( NB_TX_BUFFERS - 1 ) )
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313 xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( ulLengthToSend & ( unsigned long ) AT91C_LENGTH_FRAME )
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315 | AT91C_TRANSMIT_WRAP;
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316 uxTxBufferIndex = 0;
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320 xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( ulLengthToSend & ( unsigned long ) AT91C_LENGTH_FRAME )
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325 /* If this is the last buffer to be sent for this frame we can
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326 start the transmission. */
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329 AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TSTART;
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332 portEXIT_CRITICAL();
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342 /*-----------------------------------------------------------*/
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344 /* See the header file for descriptions of public functions. */
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345 unsigned long ulEMACInputLength( void )
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347 register unsigned long ulIndex, ulLength = 0;
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349 /* Skip any fragments. We are looking for the first buffer that contains
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350 data and has the SOF (start of frame) bit set. */
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351 while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AT91C_OWNERSHIP_BIT ) && !( xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AT91C_SOF ) )
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353 /* Ignoring this buffer. Mark it as free again. */
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354 xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );
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356 if( ulNextRxBuffer >= NB_RX_BUFFERS )
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358 ulNextRxBuffer = 0;
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362 /* We are going to walk through the descriptors that make up this frame,
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363 but don't want to alter ulNextRxBuffer as this would prevent vEMACRead()
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364 from finding the data. Therefore use a copy of ulNextRxBuffer instead. */
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365 ulIndex = ulNextRxBuffer;
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367 /* Walk through the descriptors until we find the last buffer for this
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368 frame. The last buffer will give us the length of the entire frame. */
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369 while( ( xRxDescriptors[ ulIndex ].addr & AT91C_OWNERSHIP_BIT ) && !ulLength )
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371 ulLength = xRxDescriptors[ ulIndex ].U_Status.status & emacRX_LENGTH_FRAME;
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373 /* Increment to the next buffer, wrapping if necessary. */
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375 if( ulIndex >= NB_RX_BUFFERS )
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383 /*-----------------------------------------------------------*/
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385 /* See the header file for descriptions of public functions. */
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386 void vEMACRead( char *pcTo, unsigned long ulSectionLength, unsigned long ulTotalFrameLength )
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388 static unsigned long ulSectionBytesReadSoFar = 0, ulBufferPosition = 0, ulFameBytesReadSoFar = 0;
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389 static char *pcSource;
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390 register unsigned long ulBytesRemainingInBuffer, ulRemainingSectionBytes;
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392 /* Read ulSectionLength bytes from the Rx buffers. This is not necessarily any
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393 correspondence between the length of our Rx buffers, and the length of the
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394 data we are returning or the length of the data being requested. Therefore,
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395 between calls we have to remember not only which buffer we are currently
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396 processing, but our position within that buffer. This would be greatly
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397 simplified if PBUF_POOL_BUFSIZE could be guaranteed to be greater than
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398 the size of each Rx buffer, and that memory fragmentation did not occur.
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400 This function should only be called after a call to ulEMACInputLength().
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401 This will ensure ulNextRxBuffer is set to the correct buffer. */
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405 /* vEMACRead is called with pcTo set to NULL to indicate that we are about
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406 to read a new frame. Any fragments remaining in the frame we were
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407 processing during the last call should be dropped. */
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410 /* How many bytes are indicated as being in this buffer? If none then
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411 the buffer is completely full and the frame is contained within more
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412 than one buffer. */
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414 /* Reset our state variables ready for the next read from this buffer. */
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415 pcSource = ( char * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );
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416 ulFameBytesReadSoFar = ( unsigned long ) 0;
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417 ulBufferPosition = ( unsigned long ) 0;
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421 /* Loop until we have obtained the required amount of data. */
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422 ulSectionBytesReadSoFar = 0;
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423 while( ulSectionBytesReadSoFar < ulSectionLength )
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425 /* We may have already read some data from this buffer. How much
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426 data remains in the buffer? */
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427 ulBytesRemainingInBuffer = ( ETH_RX_BUFFER_SIZE - ulBufferPosition );
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429 /* How many more bytes do we need to read before we have the
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430 required amount of data? */
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431 ulRemainingSectionBytes = ulSectionLength - ulSectionBytesReadSoFar;
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433 /* Do we want more data than remains in the buffer? */
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434 if( ulRemainingSectionBytes > ulBytesRemainingInBuffer )
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436 /* We want more data than remains in the buffer so we can
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437 write the remains of the buffer to the destination, then move
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438 onto the next buffer to get the rest. */
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439 memcpy( &( pcTo[ ulSectionBytesReadSoFar ] ), &( pcSource[ ulBufferPosition ] ), ulBytesRemainingInBuffer );
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440 ulSectionBytesReadSoFar += ulBytesRemainingInBuffer;
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441 ulFameBytesReadSoFar += ulBytesRemainingInBuffer;
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443 /* Mark the buffer as free again. */
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444 xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );
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446 /* Move onto the next buffer. */
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448 if( ulNextRxBuffer >= NB_RX_BUFFERS )
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450 ulNextRxBuffer = ( unsigned long ) 0;
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453 /* Reset the variables for the new buffer. */
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454 pcSource = ( char * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );
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455 ulBufferPosition = ( unsigned long ) 0;
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459 /* We have enough data in this buffer to send back. Read out
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460 enough data and remember how far we read up to. */
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461 memcpy( &( pcTo[ ulSectionBytesReadSoFar ] ), &( pcSource[ ulBufferPosition ] ), ulRemainingSectionBytes );
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463 /* There may be more data in this buffer yet. Increment our
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464 position in this buffer past the data we have just read. */
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465 ulBufferPosition += ulRemainingSectionBytes;
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466 ulSectionBytesReadSoFar += ulRemainingSectionBytes;
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467 ulFameBytesReadSoFar += ulRemainingSectionBytes;
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469 /* Have we now finished with this buffer? */
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470 if( ( ulBufferPosition >= ETH_RX_BUFFER_SIZE ) || ( ulFameBytesReadSoFar >= ulTotalFrameLength ) )
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472 /* Mark the buffer as free again. */
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473 xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );
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475 /* Move onto the next buffer. */
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477 if( ulNextRxBuffer >= NB_RX_BUFFERS )
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479 ulNextRxBuffer = 0;
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482 pcSource = ( char * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );
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483 ulBufferPosition = 0;
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489 /*-----------------------------------------------------------*/
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491 /* See the header file for descriptions of public functions. */
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492 SemaphoreHandle_t xEMACInit( void )
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494 /* Code supplied by Atmel -------------------------------*/
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496 /* Disable pull up on RXDV => PHY normal mode (not in test mode),
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497 PHY has internal pull down. */
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498 AT91C_BASE_PIOB->PIO_PPUDR = 1 << 15;
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500 #if USE_RMII_INTERFACE != 1
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501 /* PHY has internal pull down : set MII mode. */
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502 AT91C_BASE_PIOB->PIO_PPUDR = 1 << 16;
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505 /* Clear PB18 <=> PHY powerdown. */
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506 AT91C_BASE_PIOB->PIO_PER = 1 << 18;
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507 AT91C_BASE_PIOB->PIO_OER = 1 << 18;
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508 AT91C_BASE_PIOB->PIO_CODR = 1 << 18;
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510 /* After PHY power up, hardware reset. */
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511 AT91C_BASE_RSTC->RSTC_RMR = emacRESET_KEY | emacRESET_LENGTH;
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512 AT91C_BASE_RSTC->RSTC_RCR = emacRESET_KEY | AT91C_RSTC_EXTRST;
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514 /* Wait for hardware reset end. */
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515 while( !( AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL ) )
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517 __asm volatile ( "NOP" );
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519 __asm volatile ( "NOP" );
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521 /* Setup the pins. */
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522 AT91C_BASE_PIOB->PIO_ASR = emacPERIPHERAL_A_SETUP;
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523 AT91C_BASE_PIOB->PIO_PDR = emacPERIPHERAL_A_SETUP;
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525 /* Enable com between EMAC PHY.
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527 Enable management port. */
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528 AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;
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530 /* MDC = MCK/32. */
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531 AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10;
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533 /* Wait for PHY auto init end (rather crude delay!). */
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534 vTaskDelay( emacPHY_INIT_DELAY );
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536 /* PHY configuration. */
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537 #if USE_RMII_INTERFACE != 1
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539 unsigned long ulControl;
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541 /* PHY has internal pull down : disable MII isolate. */
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542 vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl );
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543 vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl );
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544 ulControl &= ~BMCR_ISOLATE;
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545 vWritePHY( AT91C_PHY_ADDR, MII_BMCR, ulControl );
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549 /* Disable management port again. */
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550 AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
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552 #if USE_RMII_INTERFACE != 1
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553 /* Enable EMAC in MII mode, enable clock ERXCK and ETXCK. */
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554 AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_CLKEN ;
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556 /* Enable EMAC in RMII mode, enable RMII clock (50MHz from oscillator
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558 AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_RMII | AT91C_EMAC_CLKEN ;
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561 /* End of code supplied by Atmel ------------------------*/
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563 /* Setup the buffers and descriptors. */
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564 prvSetupDescriptors();
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566 /* Load our MAC address into the EMAC. */
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567 prvSetupMACAddress();
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569 /* Are we connected? */
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570 if( prvProbePHY() )
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572 /* Enable the interrupt! */
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573 portENTER_CRITICAL();
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575 prvSetupEMACInterrupt();
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576 vPassEMACSemaphore( xSemaphore );
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578 portEXIT_CRITICAL();
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583 /*-----------------------------------------------------------*/
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585 /* See the header file for descriptions of public functions. */
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586 void vClearEMACTxBuffer( void )
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588 static unsigned portBASE_TYPE uxNextBufferToClear = 0;
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590 /* Called on Tx interrupt events to reset the AT91C_TRANSMIT_OK bit in each
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591 Tx buffer within the frame just transmitted. This marks all the buffers
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592 as available again.
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594 The first buffer in the frame should have the bit set automatically. */
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595 if( xTxDescriptors[ uxNextBufferToClear ].U_Status.status & AT91C_TRANSMIT_OK )
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597 /* Loop through the other buffers in the frame. */
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598 while( !( xTxDescriptors[ uxNextBufferToClear ].U_Status.status & AT91C_LAST_BUFFER ) )
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600 uxNextBufferToClear++;
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602 if( uxNextBufferToClear >= NB_TX_BUFFERS )
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604 uxNextBufferToClear = 0;
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607 xTxDescriptors[ uxNextBufferToClear ].U_Status.status |= AT91C_TRANSMIT_OK;
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610 /* Start with the next buffer the next time a Tx interrupt is called. */
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611 uxNextBufferToClear++;
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613 /* Do we need to wrap back to the first buffer? */
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614 if( uxNextBufferToClear >= NB_TX_BUFFERS )
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616 uxNextBufferToClear = 0;
\r
620 /*-----------------------------------------------------------*/
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622 static void prvSetupDescriptors(void)
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624 unsigned portBASE_TYPE xIndex;
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625 unsigned long ulAddress;
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627 /* Initialise xRxDescriptors descriptor. */
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628 for( xIndex = 0; xIndex < NB_RX_BUFFERS; ++xIndex )
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630 /* Calculate the address of the nth buffer within the array. */
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631 ulAddress = ( unsigned long )( pcRxBuffer + ( xIndex * ETH_RX_BUFFER_SIZE ) );
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633 /* Write the buffer address into the descriptor. The DMA will place
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634 the data at this address when this descriptor is being used. Mask off
\r
635 the bottom bits of the address as these have special meaning. */
\r
636 xRxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;
\r
639 /* The last buffer has the wrap bit set so the EMAC knows to wrap back
\r
640 to the first buffer. */
\r
641 xRxDescriptors[ NB_RX_BUFFERS - 1 ].addr |= emacRX_WRAP_BIT;
\r
643 /* Initialise xTxDescriptors. */
\r
644 for( xIndex = 0; xIndex < NB_TX_BUFFERS; ++xIndex )
\r
646 /* Calculate the address of the nth buffer within the array. */
\r
647 ulAddress = ( unsigned long )( pcTxBuffer + ( xIndex * ETH_TX_BUFFER_SIZE ) );
\r
649 /* Write the buffer address into the descriptor. The DMA will read
\r
650 data from here when the descriptor is being used. */
\r
651 xTxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;
\r
652 xTxDescriptors[ xIndex ].U_Status.status = AT91C_TRANSMIT_OK;
\r
655 /* The last buffer has the wrap bit set so the EMAC knows to wrap back
\r
656 to the first buffer. */
\r
657 xTxDescriptors[ NB_TX_BUFFERS - 1 ].U_Status.status = AT91C_TRANSMIT_WRAP | AT91C_TRANSMIT_OK;
\r
659 /* Tell the EMAC where to find the descriptors. */
\r
660 AT91C_BASE_EMAC->EMAC_RBQP = ( unsigned long ) xRxDescriptors;
\r
661 AT91C_BASE_EMAC->EMAC_TBQP = ( unsigned long ) xTxDescriptors;
\r
663 /* Clear all the bits in the receive status register. */
\r
664 AT91C_BASE_EMAC->EMAC_RSR = ( AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA );
\r
666 /* Enable the copy of data into the buffers, ignore broadcasts,
\r
667 and don't copy FCS. */
\r
668 AT91C_BASE_EMAC->EMAC_NCFGR |= ( AT91C_EMAC_CAF | AT91C_EMAC_NBC | AT91C_EMAC_DRFCS);
\r
670 /* Enable Rx and Tx, plus the stats register. */
\r
671 AT91C_BASE_EMAC->EMAC_NCR |= ( AT91C_EMAC_TE | AT91C_EMAC_RE | AT91C_EMAC_WESTAT );
\r
673 /*-----------------------------------------------------------*/
\r
675 static void prvSetupMACAddress( void )
\r
677 /* Must be written SA1L then SA1H. */
\r
678 AT91C_BASE_EMAC->EMAC_SA1L = ( ( unsigned long ) cMACAddress[ 3 ] << 24 ) |
\r
679 ( ( unsigned long ) cMACAddress[ 2 ] << 16 ) |
\r
680 ( ( unsigned long ) cMACAddress[ 1 ] << 8 ) |
\r
683 AT91C_BASE_EMAC->EMAC_SA1H = ( ( unsigned long ) cMACAddress[ 5 ] << 8 ) |
\r
686 /*-----------------------------------------------------------*/
\r
688 static void prvSetupEMACInterrupt( void )
\r
690 /* Create the semaphore used to trigger the EMAC task. */
\r
691 vSemaphoreCreateBinary( xSemaphore );
\r
694 /* We start by 'taking' the semaphore so the ISR can 'give' it when the
\r
695 first interrupt occurs. */
\r
696 xSemaphoreTake( xSemaphore, emacNO_DELAY );
\r
697 portENTER_CRITICAL();
\r
699 /* We want to interrupt on Rx and Tx events. */
\r
700 AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_RCOMP | AT91C_EMAC_TCOMP;
\r
702 /* Enable the interrupts in the AIC. */
\r
703 AT91F_AIC_ConfigureIt( AT91C_ID_EMAC, emacINTERRUPT_LEVEL, AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, ( void (*)( void ) ) vEMACISR_Wrapper );
\r
704 AT91C_BASE_AIC->AIC_IECR = 0x1 << AT91C_ID_EMAC;
\r
706 portEXIT_CRITICAL();
\r
715 * The following functions are initialisation functions taken from the Atmel
\r
716 * EMAC sample code.
\r
720 static portBASE_TYPE prvProbePHY( void )
\r
722 unsigned long ulPHYId1, ulPHYId2, ulStatus;
\r
723 portBASE_TYPE xReturn = pdPASS;
\r
725 /* Code supplied by Atmel (reformatted) -----------------*/
\r
727 /* Enable management port */
\r
728 AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;
\r
729 AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10;
\r
731 /* Read the PHY ID. */
\r
732 vReadPHY( AT91C_PHY_ADDR, MII_PHYSID1, &ulPHYId1 );
\r
733 vReadPHY(AT91C_PHY_ADDR, MII_PHYSID2, &ulPHYId2 );
\r
738 Bits 3:0 Revision Number Four bit manufacturer?s revision number.
\r
739 0001 stands for Rev. A, etc.
\r
741 if( ( ( ulPHYId1 << 16 ) | ( ulPHYId2 & 0xfff0 ) ) != MII_DM9161_ID )
\r
743 /* Did not expect this ID. */
\r
748 ulStatus = xGetLinkSpeed();
\r
750 if( ulStatus != pdPASS )
\r
756 /* Disable management port */
\r
757 AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
\r
759 /* End of code supplied by Atmel ------------------------*/
\r
763 /*-----------------------------------------------------------*/
\r
765 static void vReadPHY( unsigned char ucPHYAddress, unsigned char ucAddress, unsigned long *pulValue )
\r
767 /* Code supplied by Atmel (reformatted) ----------------------*/
\r
769 AT91C_BASE_EMAC->EMAC_MAN = (AT91C_EMAC_SOF & (0x01<<30))
\r
770 | (2 << 16) | (2 << 28)
\r
771 | ((ucPHYAddress & 0x1f) << 23)
\r
772 | (ucAddress << 18);
\r
774 /* Wait until IDLE bit in Network Status register is cleared. */
\r
775 while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) )
\r
780 *pulValue = ( AT91C_BASE_EMAC->EMAC_MAN & 0x0000ffff );
\r
782 /* End of code supplied by Atmel ------------------------*/
\r
784 /*-----------------------------------------------------------*/
\r
786 #if USE_RMII_INTERFACE != 1
\r
787 static void vWritePHY( unsigned char ucPHYAddress, unsigned char ucAddress, unsigned long ulValue )
\r
789 /* Code supplied by Atmel (reformatted) ----------------------*/
\r
791 AT91C_BASE_EMAC->EMAC_MAN = (( AT91C_EMAC_SOF & (0x01<<30))
\r
792 | (2 << 16) | (1 << 28)
\r
793 | ((ucPHYAddress & 0x1f) << 23)
\r
794 | (ucAddress << 18))
\r
795 | (ulValue & 0xffff);
\r
797 /* Wait until IDLE bit in Network Status register is cleared */
\r
798 while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) )
\r
803 /* End of code supplied by Atmel ------------------------*/
\r
806 /*-----------------------------------------------------------*/
\r
808 static portBASE_TYPE xGetLinkSpeed( void )
\r
810 unsigned long ulBMSR, ulBMCR, ulLPA, ulMACCfg, ulSpeed, ulDuplex;
\r
812 /* Code supplied by Atmel (reformatted) -----------------*/
\r
814 /* Link status is latched, so read twice to get current value */
\r
815 vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR);
\r
816 vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR);
\r
818 if( !( ulBMSR & BMSR_LSTATUS ) )
\r
824 vReadPHY(AT91C_PHY_ADDR, MII_BMCR, &ulBMCR);
\r
825 if (ulBMCR & BMCR_ANENABLE)
\r
827 /* AutoNegotiation is enabled. */
\r
828 if (!(ulBMSR & BMSR_ANEGCOMPLETE))
\r
830 /* Auto-negotitation in progress. */
\r
834 vReadPHY(AT91C_PHY_ADDR, MII_LPA, &ulLPA);
\r
835 if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_100HALF ) )
\r
837 ulSpeed = SPEED_100;
\r
841 ulSpeed = SPEED_10;
\r
844 if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_10FULL ) )
\r
846 ulDuplex = DUPLEX_FULL;
\r
850 ulDuplex = DUPLEX_HALF;
\r
855 ulSpeed = ( ulBMCR & BMCR_SPEED100 ) ? SPEED_100 : SPEED_10;
\r
856 ulDuplex = ( ulBMCR & BMCR_FULLDPLX ) ? DUPLEX_FULL : DUPLEX_HALF;
\r
859 /* Update the MAC */
\r
860 ulMACCfg = AT91C_BASE_EMAC->EMAC_NCFGR & ~( AT91C_EMAC_SPD | AT91C_EMAC_FD );
\r
861 if( ulSpeed == SPEED_100 )
\r
863 if( ulDuplex == DUPLEX_FULL )
\r
865 /* 100 Full Duplex */
\r
866 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD | AT91C_EMAC_FD;
\r
870 /* 100 Half Duplex */
\r
871 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD;
\r
876 if (ulDuplex == DUPLEX_FULL)
\r
878 /* 10 Full Duplex */
\r
879 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_FD;
\r
882 { /* 10 Half Duplex */
\r
883 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg;
\r
887 /* End of code supplied by Atmel ------------------------*/
\r
891 /*-----------------------------------------------------------*/
\r
893 void vEMACWaitForInput( void )
\r
895 /* Just wait until we are signled from an ISR that data is available, or
\r
896 we simply time out. */
\r
897 xSemaphoreTake( xSemaphore, emacBLOCK_TIME_WAITING_FOR_INPUT );
\r
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