2 FreeRTOS V7.5.3 - Copyright (C) 2013 Real Time Engineers Ltd.
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5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 ***************************************************************************
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9 * FreeRTOS provides completely free yet professionally developed, *
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10 * robust, strictly quality controlled, supported, and cross *
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11 * platform software that has become a de facto standard. *
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13 * Help yourself get started quickly and support the FreeRTOS *
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14 * project by purchasing a FreeRTOS tutorial book, reference *
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15 * manual, or both from: http://www.FreeRTOS.org/Documentation *
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19 ***************************************************************************
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21 This file is part of the FreeRTOS distribution.
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23 FreeRTOS is free software; you can redistribute it and/or modify it under
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24 the terms of the GNU General Public License (version 2) as published by the
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25 Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
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27 >>! NOTE: The modification to the GPL is included to allow you to distribute
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28 >>! a combined work that includes FreeRTOS without being obliged to provide
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29 >>! the source code for proprietary components outside of the FreeRTOS
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32 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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33 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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34 FOR A PARTICULAR PURPOSE. Full license text is available from the following
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35 link: http://www.freertos.org/a00114.html
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39 ***************************************************************************
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41 * Having a problem? Start by reading the FAQ "My application does *
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42 * not run, what could be wrong?" *
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44 * http://www.FreeRTOS.org/FAQHelp.html *
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46 ***************************************************************************
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48 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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49 license and Real Time Engineers Ltd. contact details.
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51 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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52 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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53 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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55 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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56 Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
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57 licenses offer ticketed support, indemnification and middleware.
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59 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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60 engineered and independently SIL3 certified version for use in safety and
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61 mission critical applications that require provable dependability.
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67 * Basic interrupt driven driver for the EMAC peripheral. This driver is not
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68 * reentrant as with uIP the buffers are only ever accessed from a single task.
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70 * The simple buffer management used within uIP allows the EMAC driver to also
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71 * be simplistic. The driver contained within the lwIP demo is more
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79 + Corrected the byte order when writing the MAC address to the MAC.
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80 + Support added for MII interfaces. Previously only RMII was supported.
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84 + The MII interface is now the default.
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85 + Modified the initialisation sequence slightly to allow auto init more
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90 + Also read the EMAC_RSR register in the EMAC ISR as a work around the
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91 the EMAC bug that can reset the RX bit in EMAC_ISR register before the
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96 + Corrected the Rx frame length mask when obtaining the length from the
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101 /* Standard includes. */
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102 #include <string.h>
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104 /* Scheduler includes. */
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105 #include "FreeRTOS.h"
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106 #include "semphr.h"
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109 /* uIP includes. */
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112 /* Hardware specific includes. */
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117 /* USE_RMII_INTERFACE must be defined as 1 to use an RMII interface, or 0
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118 to use an MII interface. */
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119 #define USE_RMII_INTERFACE 0
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121 /* The buffer addresses written into the descriptors must be aligned so the
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122 last few bits are zero. These bits have special meaning for the EMAC
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123 peripheral and cannot be used as part of the address. */
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124 #define emacADDRESS_MASK ( ( unsigned long ) 0xFFFFFFFC )
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126 /* Bit used within the address stored in the descriptor to mark the last
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127 descriptor in the array. */
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128 #define emacRX_WRAP_BIT ( ( unsigned long ) 0x02 )
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130 /* Bit used within the Tx descriptor status to indicate whether the
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131 descriptor is under the control of the EMAC or the software. */
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132 #define emacTX_BUF_USED ( ( unsigned long ) 0x80000000 )
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134 /* A short delay is used to wait for a buffer to become available, should
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135 one not be immediately available when trying to transmit a frame. */
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136 #define emacBUFFER_WAIT_DELAY ( 2 )
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137 #define emacMAX_WAIT_CYCLES ( configTICK_RATE_HZ / 40 )
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139 /* Misc defines. */
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140 #define emacINTERRUPT_LEVEL ( 5 )
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141 #define emacNO_DELAY ( 0 )
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142 #define emacTOTAL_FRAME_HEADER_SIZE ( 54 )
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143 #define emacPHY_INIT_DELAY ( 5000 / portTICK_RATE_MS )
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144 #define emacRESET_KEY ( ( unsigned long ) 0xA5000000 )
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145 #define emacRESET_LENGTH ( ( unsigned long ) ( 0x01 << 8 ) )
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147 /* The Atmel header file only defines the TX frame length mask. */
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148 #define emacRX_LENGTH_FRAME ( 0xfff )
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150 /*-----------------------------------------------------------*/
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153 * Prototype for the EMAC interrupt asm wrapper.
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155 extern void vEMACISREntry( void );
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158 * Prototype for the EMAC interrupt function - called by the asm wrapper.
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160 __arm void vEMACISR( void );
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163 * Initialise both the Tx and Rx descriptors used by the EMAC.
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165 static void prvSetupDescriptors(void);
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168 * Write our MAC address into the EMAC. The MAC address is set as one of the
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171 static void prvSetupMACAddress( void );
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174 * Configure the EMAC and AIC for EMAC interrupts.
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176 static void prvSetupEMACInterrupt( void );
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179 * Some initialisation functions taken from the Atmel EMAC sample code.
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181 static void vReadPHY( unsigned char ucPHYAddress, unsigned char ucAddress, unsigned long *pulValue );
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182 #if USE_RMII_INTERFACE != 1
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183 static void vWritePHY( unsigned char ucPHYAddress, unsigned char ucAddress, unsigned long ulValue);
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185 static portBASE_TYPE xGetLinkSpeed( void );
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186 static portBASE_TYPE prvProbePHY( void );
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188 /*-----------------------------------------------------------*/
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190 /* Buffer written to by the EMAC DMA. Must be aligned as described by the
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191 comment above the emacADDRESS_MASK definition. */
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192 #pragma data_alignment=8
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193 static volatile char pcRxBuffer[ NB_RX_BUFFERS * ETH_RX_BUFFER_SIZE ];
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195 /* Buffer read by the EMAC DMA. Must be aligned as described by he comment
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196 above the emacADDRESS_MASK definition. */
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197 #pragma data_alignment=8
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198 static char pcTxBuffer[ NB_TX_BUFFERS * ETH_TX_BUFFER_SIZE ];
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200 /* Descriptors used to communicate between the program and the EMAC peripheral.
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201 These descriptors hold the locations and state of the Rx and Tx buffers. */
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202 static volatile AT91S_TxTdDescriptor xTxDescriptors[ NB_TX_BUFFERS ];
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203 static volatile AT91S_RxTdDescriptor xRxDescriptors[ NB_RX_BUFFERS ];
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205 /* The IP and Ethernet addresses are read from the uIP setup. */
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206 const char cMACAddress[ 6 ] = { UIP_ETHADDR0, UIP_ETHADDR1, UIP_ETHADDR2, UIP_ETHADDR3, UIP_ETHADDR4, UIP_ETHADDR5 };
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207 const unsigned char ucIPAddress[ 4 ] = { UIP_IPADDR0, UIP_IPADDR1, UIP_IPADDR2, UIP_IPADDR3 };
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209 /* The semaphore used by the EMAC ISR to wake the EMAC task. */
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210 static xSemaphoreHandle xSemaphore = NULL;
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212 /*-----------------------------------------------------------*/
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214 xSemaphoreHandle xEMACInit( void )
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216 /* Code supplied by Atmel (modified) --------------------*/
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218 /* disable pull up on RXDV => PHY normal mode (not in test mode),
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219 PHY has internal pull down. */
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220 AT91C_BASE_PIOB->PIO_PPUDR = 1 << 15;
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222 #if USE_RMII_INTERFACE != 1
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223 /* PHY has internal pull down : set MII mode. */
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224 AT91C_BASE_PIOB->PIO_PPUDR= 1 << 16;
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227 /* clear PB18 <=> PHY powerdown. */
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228 AT91F_PIO_CfgOutput( AT91C_BASE_PIOB, 1 << 18 ) ;
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229 AT91F_PIO_ClearOutput( AT91C_BASE_PIOB, 1 << 18) ;
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231 /* After PHY power up, hardware reset. */
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232 AT91C_BASE_RSTC->RSTC_RMR = emacRESET_KEY | emacRESET_LENGTH;
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233 AT91C_BASE_RSTC->RSTC_RCR = emacRESET_KEY | AT91C_RSTC_EXTRST;
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235 /* Wait for hardware reset end. */
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236 while( !( AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL ) )
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242 /* EMAC IO init for EMAC-PHY com. Remove EF100 config. */
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243 AT91F_EMAC_CfgPIO();
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245 /* Enable com between EMAC PHY.
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247 Enable management port. */
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248 AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;
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250 /* MDC = MCK/32. */
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251 AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10;
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253 /* Wait for PHY auto init end (rather crude delay!). */
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254 vTaskDelay( emacPHY_INIT_DELAY );
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256 /* PHY configuration. */
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257 #if USE_RMII_INTERFACE != 1
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259 unsigned long ulControl;
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261 /* PHY has internal pull down : disable MII isolate. */
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262 vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl );
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263 vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl );
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264 ulControl &= ~BMCR_ISOLATE;
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265 vWritePHY( AT91C_PHY_ADDR, MII_BMCR, ulControl );
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269 /* Disable management port again. */
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270 AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
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272 #if USE_RMII_INTERFACE != 1
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273 /* Enable EMAC in MII mode, enable clock ERXCK and ETXCK. */
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274 AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_CLKEN ;
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276 /* Enable EMAC in RMII mode, enable RMII clock (50MHz from oscillator
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278 AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_RMII | AT91C_EMAC_CLKEN ;
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281 /* End of code supplied by Atmel ------------------------*/
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283 /* Setup the buffers and descriptors. */
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284 prvSetupDescriptors();
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286 /* Load our MAC address into the EMAC. */
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287 prvSetupMACAddress();
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289 /* Try to connect. */
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290 if( prvProbePHY() )
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292 /* Enable the interrupt! */
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293 prvSetupEMACInterrupt();
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298 /*-----------------------------------------------------------*/
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300 long lEMACSend( void )
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302 static unsigned portBASE_TYPE uxTxBufferIndex = 0;
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303 portBASE_TYPE xWaitCycles = 0;
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304 long lReturn = pdPASS;
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307 /* Is a buffer available? */
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308 while( !( xTxDescriptors[ uxTxBufferIndex ].U_Status.status & AT91C_TRANSMIT_OK ) )
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310 /* There is no room to write the Tx data to the Tx buffer. Wait a
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311 short while, then try again. */
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313 if( xWaitCycles > emacMAX_WAIT_CYCLES )
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321 vTaskDelay( emacBUFFER_WAIT_DELAY );
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325 /* lReturn will only be pdPASS if a buffer is available. */
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326 if( lReturn == pdPASS )
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328 /* Copy the headers into the Tx buffer. These will be in the uIP buffer. */
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329 pcBuffer = ( char * ) xTxDescriptors[ uxTxBufferIndex ].addr;
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330 memcpy( ( void * ) pcBuffer, ( void * ) uip_buf, emacTOTAL_FRAME_HEADER_SIZE );
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331 if( uip_len > emacTOTAL_FRAME_HEADER_SIZE )
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333 memcpy( ( void * ) &( pcBuffer[ emacTOTAL_FRAME_HEADER_SIZE ] ), ( void * ) uip_appdata, ( uip_len - emacTOTAL_FRAME_HEADER_SIZE ) );
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337 portENTER_CRITICAL();
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339 if( uxTxBufferIndex >= ( NB_TX_BUFFERS - 1 ) )
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341 /* Fill out the necessary in the descriptor to get the data sent. */
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342 xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( uip_len & ( unsigned long ) AT91C_LENGTH_FRAME )
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343 | AT91C_LAST_BUFFER
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344 | AT91C_TRANSMIT_WRAP;
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345 uxTxBufferIndex = 0;
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349 /* Fill out the necessary in the descriptor to get the data sent. */
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350 xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( uip_len & ( unsigned long ) AT91C_LENGTH_FRAME )
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351 | AT91C_LAST_BUFFER;
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355 AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TSTART;
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357 portEXIT_CRITICAL();
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362 /*-----------------------------------------------------------*/
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364 unsigned long ulEMACPoll( void )
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366 static unsigned portBASE_TYPE ulNextRxBuffer = 0;
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367 unsigned long ulSectionLength = 0, ulLengthSoFar = 0, ulEOF = pdFALSE;
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370 /* Skip any fragments. */
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371 while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AT91C_OWNERSHIP_BIT ) && !( xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AT91C_SOF ) )
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373 /* Mark the buffer as free again. */
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374 xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );
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376 if( ulNextRxBuffer >= NB_RX_BUFFERS )
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378 ulNextRxBuffer = 0;
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382 /* Is there a packet ready? */
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384 while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AT91C_OWNERSHIP_BIT ) && !ulSectionLength )
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386 pcSource = ( char * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );
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387 ulSectionLength = xRxDescriptors[ ulNextRxBuffer ].U_Status.status & emacRX_LENGTH_FRAME;
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389 if( ulSectionLength == 0 )
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391 /* The frame is longer than the buffer pointed to by this
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392 descriptor so copy the entire buffer to uIP - then move onto
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393 the next descriptor to get the rest of the frame. */
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394 if( ( ulLengthSoFar + ETH_RX_BUFFER_SIZE ) <= UIP_BUFSIZE )
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396 memcpy( &( uip_buf[ ulLengthSoFar ] ), pcSource, ETH_RX_BUFFER_SIZE );
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397 ulLengthSoFar += ETH_RX_BUFFER_SIZE;
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402 /* This is the last section of the frame. Copy the section to
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404 if( ulSectionLength < UIP_BUFSIZE )
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406 /* The section length holds the length of the entire frame.
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407 ulLengthSoFar holds the length of the frame sections already
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408 copied to uIP, so the length of the final section is
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409 ulSectionLength - ulLengthSoFar; */
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410 if( ulSectionLength > ulLengthSoFar )
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412 memcpy( &( uip_buf[ ulLengthSoFar ] ), pcSource, ( ulSectionLength - ulLengthSoFar ) );
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416 /* Is this the last buffer for the frame? If not why? */
\r
417 ulEOF = xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AT91C_EOF;
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420 /* Mark the buffer as free again. */
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421 xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );
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423 /* Increment to the next buffer, wrapping if necessary. */
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425 if( ulNextRxBuffer >= NB_RX_BUFFERS )
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427 ulNextRxBuffer = 0;
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431 /* If we obtained data but for some reason did not find the end of the
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432 frame then discard the data as it must contain an error. */
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435 ulSectionLength = 0;
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438 return ulSectionLength;
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440 /*-----------------------------------------------------------*/
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442 static void prvSetupDescriptors(void)
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444 unsigned portBASE_TYPE xIndex;
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445 unsigned long ulAddress;
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447 /* Initialise xRxDescriptors descriptor. */
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448 for( xIndex = 0; xIndex < NB_RX_BUFFERS; ++xIndex )
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450 /* Calculate the address of the nth buffer within the array. */
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451 ulAddress = ( unsigned long )( pcRxBuffer + ( xIndex * ETH_RX_BUFFER_SIZE ) );
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453 /* Write the buffer address into the descriptor. The DMA will place
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454 the data at this address when this descriptor is being used. Mask off
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455 the bottom bits of the address as these have special meaning. */
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456 xRxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;
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459 /* The last buffer has the wrap bit set so the EMAC knows to wrap back
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460 to the first buffer. */
\r
461 xRxDescriptors[ NB_RX_BUFFERS - 1 ].addr |= emacRX_WRAP_BIT;
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463 /* Initialise xTxDescriptors. */
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464 for( xIndex = 0; xIndex < NB_TX_BUFFERS; ++xIndex )
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466 /* Calculate the address of the nth buffer within the array. */
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467 ulAddress = ( unsigned long )( pcTxBuffer + ( xIndex * ETH_TX_BUFFER_SIZE ) );
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469 /* Write the buffer address into the descriptor. The DMA will read
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470 data from here when the descriptor is being used. */
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471 xTxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;
\r
472 xTxDescriptors[ xIndex ].U_Status.status = AT91C_TRANSMIT_OK;
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475 /* The last buffer has the wrap bit set so the EMAC knows to wrap back
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476 to the first buffer. */
\r
477 xTxDescriptors[ NB_TX_BUFFERS - 1 ].U_Status.status = AT91C_TRANSMIT_WRAP | AT91C_TRANSMIT_OK;
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479 /* Tell the EMAC where to find the descriptors. */
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480 AT91C_BASE_EMAC->EMAC_RBQP = ( unsigned long ) xRxDescriptors;
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481 AT91C_BASE_EMAC->EMAC_TBQP = ( unsigned long ) xTxDescriptors;
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483 /* Clear all the bits in the receive status register. */
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484 AT91C_BASE_EMAC->EMAC_RSR = ( AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA );
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486 /* Enable the copy of data into the buffers, ignore broadcasts,
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487 and don't copy FCS. */
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488 AT91C_BASE_EMAC->EMAC_NCFGR |= ( AT91C_EMAC_CAF | AT91C_EMAC_NBC | AT91C_EMAC_DRFCS);
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490 /* Enable Rx and Tx, plus the stats register. */
\r
491 AT91C_BASE_EMAC->EMAC_NCR |= ( AT91C_EMAC_TE | AT91C_EMAC_RE | AT91C_EMAC_WESTAT );
\r
493 /*-----------------------------------------------------------*/
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495 static void prvSetupMACAddress( void )
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497 /* Must be written SA1L then SA1H. */
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498 AT91C_BASE_EMAC->EMAC_SA1L = ( ( unsigned long ) cMACAddress[ 3 ] << 24 ) |
\r
499 ( ( unsigned long ) cMACAddress[ 2 ] << 16 ) |
\r
500 ( ( unsigned long ) cMACAddress[ 1 ] << 8 ) |
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503 AT91C_BASE_EMAC->EMAC_SA1H = ( ( unsigned long ) cMACAddress[ 5 ] << 8 ) |
\r
506 /*-----------------------------------------------------------*/
\r
508 static void prvSetupEMACInterrupt( void )
\r
510 /* Create the semaphore used to trigger the EMAC task. */
\r
511 vSemaphoreCreateBinary( xSemaphore );
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514 /* We start by 'taking' the semaphore so the ISR can 'give' it when the
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515 first interrupt occurs. */
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516 xSemaphoreTake( xSemaphore, emacNO_DELAY );
\r
517 portENTER_CRITICAL();
\r
519 /* We want to interrupt on Rx events. */
\r
520 AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_RCOMP;
\r
522 /* Enable the interrupts in the AIC. */
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523 AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_EMAC, emacINTERRUPT_LEVEL, AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, ( void (*)( void ) ) vEMACISREntry );
\r
524 AT91F_AIC_EnableIt( AT91C_BASE_AIC, AT91C_ID_EMAC );
\r
526 portEXIT_CRITICAL();
\r
529 /*-----------------------------------------------------------*/
\r
531 __arm void vEMACISR( void )
\r
533 volatile unsigned long ulIntStatus, ulRxStatus;
\r
534 portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
\r
536 ulIntStatus = AT91C_BASE_EMAC->EMAC_ISR;
\r
537 ulRxStatus = AT91C_BASE_EMAC->EMAC_RSR;
\r
539 if( ( ulIntStatus & AT91C_EMAC_RCOMP ) || ( ulRxStatus & AT91C_EMAC_REC ) )
\r
541 /* A frame has been received, signal the uIP task so it can process
\r
542 the Rx descriptors. */
\r
543 xSemaphoreGiveFromISR( xSemaphore, &xHigherPriorityTaskWoken );
\r
544 AT91C_BASE_EMAC->EMAC_RSR = AT91C_EMAC_REC;
\r
547 /* If a task was woken by either a character being received or a character
\r
548 being transmitted then we may need to switch to another task. */
\r
549 portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );
\r
551 /* Clear the interrupt. */
\r
552 AT91C_BASE_AIC->AIC_EOICR = 0;
\r
554 /*-----------------------------------------------------------*/
\r
559 * The following functions are initialisation functions taken from the Atmel
\r
560 * EMAC sample code.
\r
563 static portBASE_TYPE prvProbePHY( void )
\r
565 unsigned long ulPHYId1, ulPHYId2, ulStatus;
\r
566 portBASE_TYPE xReturn = pdPASS;
\r
568 /* Code supplied by Atmel (reformatted) -----------------*/
\r
570 /* Enable management port */
\r
571 AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;
\r
572 AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10;
\r
574 /* Read the PHY ID. */
\r
575 vReadPHY( AT91C_PHY_ADDR, MII_PHYSID1, &ulPHYId1 );
\r
576 vReadPHY( AT91C_PHY_ADDR, MII_PHYSID2, &ulPHYId2 );
\r
581 Bits 3:0 Revision Number Four bit manufacturer
\92s revision number.
\r
582 0001 stands for Rev. A, etc.
\r
584 if( ( ( ulPHYId1 << 16 ) | ( ulPHYId2 & 0xfff0 ) ) != MII_DM9161_ID )
\r
586 /* Did not expect this ID. */
\r
591 ulStatus = xGetLinkSpeed();
\r
593 if( ulStatus != pdPASS )
\r
599 /* Disable management port */
\r
600 AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
\r
602 /* End of code supplied by Atmel ------------------------*/
\r
606 /*-----------------------------------------------------------*/
\r
608 static void vReadPHY( unsigned char ucPHYAddress, unsigned char ucAddress, unsigned long *pulValue )
\r
610 /* Code supplied by Atmel (reformatted) ----------------------*/
\r
612 AT91C_BASE_EMAC->EMAC_MAN = (AT91C_EMAC_SOF & (0x01<<30))
\r
613 | (2 << 16) | (2 << 28)
\r
614 | ((ucPHYAddress & 0x1f) << 23)
\r
615 | (ucAddress << 18);
\r
617 /* Wait until IDLE bit in Network Status register is cleared. */
\r
618 while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) )
\r
623 *pulValue = ( AT91C_BASE_EMAC->EMAC_MAN & 0x0000ffff );
\r
625 /* End of code supplied by Atmel ------------------------*/
\r
627 /*-----------------------------------------------------------*/
\r
629 #if USE_RMII_INTERFACE != 1
\r
630 static void vWritePHY( unsigned char ucPHYAddress, unsigned char ucAddress, unsigned long ulValue )
\r
632 /* Code supplied by Atmel (reformatted) ----------------------*/
\r
634 AT91C_BASE_EMAC->EMAC_MAN = (( AT91C_EMAC_SOF & (0x01<<30))
\r
635 | (2 << 16) | (1 << 28)
\r
636 | ((ucPHYAddress & 0x1f) << 23)
\r
637 | (ucAddress << 18))
\r
638 | (ulValue & 0xffff);
\r
640 /* Wait until IDLE bit in Network Status register is cleared */
\r
641 while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) )
\r
646 /* End of code supplied by Atmel ------------------------*/
\r
649 /*-----------------------------------------------------------*/
\r
651 static portBASE_TYPE xGetLinkSpeed( void )
\r
653 unsigned long ulBMSR, ulBMCR, ulLPA, ulMACCfg, ulSpeed, ulDuplex;
\r
655 /* Code supplied by Atmel (reformatted) -----------------*/
\r
657 /* Link status is latched, so read twice to get current value */
\r
658 vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR);
\r
659 vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR);
\r
661 if( !( ulBMSR & BMSR_LSTATUS ) )
\r
667 vReadPHY(AT91C_PHY_ADDR, MII_BMCR, &ulBMCR);
\r
668 if (ulBMCR & BMCR_ANENABLE)
\r
670 /* AutoNegotiation is enabled. */
\r
671 if (!(ulBMSR & BMSR_ANEGCOMPLETE))
\r
673 /* Auto-negotiation in progress. */
\r
677 vReadPHY(AT91C_PHY_ADDR, MII_LPA, &ulLPA);
\r
678 if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_100HALF ) )
\r
680 ulSpeed = SPEED_100;
\r
684 ulSpeed = SPEED_10;
\r
687 if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_10FULL ) )
\r
689 ulDuplex = DUPLEX_FULL;
\r
693 ulDuplex = DUPLEX_HALF;
\r
698 ulSpeed = ( ulBMCR & BMCR_SPEED100 ) ? SPEED_100 : SPEED_10;
\r
699 ulDuplex = ( ulBMCR & BMCR_FULLDPLX ) ? DUPLEX_FULL : DUPLEX_HALF;
\r
702 /* Update the MAC */
\r
703 ulMACCfg = AT91C_BASE_EMAC->EMAC_NCFGR & ~( AT91C_EMAC_SPD | AT91C_EMAC_FD );
\r
704 if( ulSpeed == SPEED_100 )
\r
706 if( ulDuplex == DUPLEX_FULL )
\r
708 /* 100 Full Duplex */
\r
709 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD | AT91C_EMAC_FD;
\r
713 /* 100 Half Duplex */
\r
714 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD;
\r
719 if (ulDuplex == DUPLEX_FULL)
\r
721 /* 10 Full Duplex */
\r
722 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_FD;
\r
726 /* 10 Half Duplex */
\r
727 AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg;
\r
731 /* End of code supplied by Atmel ------------------------*/
\r