git.sur5r.net Git - freertos/blob - FreeRTOS/Demo/uIP_Demo_IAR_ARM7/resource/SAM7.mac

   1 // ---------------------------------------------------------\r
   2 //               Microcontroller Software Support  -  ROUSSET  -\r
   3 // ---------------------------------------------------------\r
   4 // The software is delivered "AS IS" without warranty or \r
   5 // condition of any  kind, either express, implied or \r
   6 // statutory. This includes without limitation any warranty \r
   7 // or condition with respect to merchantability or fitness \r
   8 // for any particular purpose, or against the infringements of\r
   9 // intellectual property rights of others.\r
  10 // ---------------------------------------------------------\r
  11 //  File: SAM7.mac\r
  12 //\r
  13 //  1.0 08/Mar/04 JPP    : Creation\r
  14 //  1.1 23/Mar/05 JPP    : Change Variable name\r
  15 //\r
  16 //  $Revision: 1.5 $\r
  17 //\r
  18 // ---------------------------------------------------------\r
  19 \r
  20 __var __mac_i;\r
  21 __var __mac_pt;\r
  22 \r
  23 execUserReset()\r
  24 {\r
  25    AIC();\r
  26 //*  Watchdog Disable\r
  27    Watchdog();\r
  28 }\r
  29 \r
  30 execUserPreload()\r
  31 {\r
  32 //*  Set the RAM memory at 0x0020 0000 for code AT 0 flash area \r
  33      CheckRemap();\r
  34 //*  Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R\r
  35     __mac_i =__readMemory32(0xFFFFF240,"Memory");\r
  36     __message " ---------------------------------------- Chip ID   0x",__mac_i:%X;  \r
  37     __mac_i =__readMemory32(0xFFFFF244,"Memory");\r
  38     __message " ---------------------------------------- Extention 0x",__mac_i:%X;  \r
  39 //* Get the chip status\r
  40 \r
  41 //* Init AIC\r
  42    AIC();\r
  43 //*  Watchdog Disable\r
  44    Watchdog();\r
  45 \r
  46 }\r
  47 \r
  48 \r
  49 //-----------------------------------------------------------------------------\r
  50 // Watchdog\r
  51 //-------------------------------\r
  52 // Normally, the Watchdog is enable at the reset for load it's preferable to\r
  53 // Disable.\r
  54 //-----------------------------------------------------------------------------\r
  55 Watchdog()\r
  56 {\r
  57 //* Watchdog Disable\r
  58 //      AT91C_BASE_WDTC->WDTC_WDMR= AT91C_WDTC_WDDIS;\r
  59    __writeMemory32(0x00008000,0xFFFFFD44,"Memory");\r
  60    __message "------------------------------- Watchdog Disable ----------------------------------------";  \r
  61 }\r
  62 \r
  63 \r
  64 //-----------------------------------------------------------------------------\r
  65 // Check Remap\r
  66 //-------------\r
  67 //-----------------------------------------------------------------------------\r
  68 CheckRemap()\r
  69 {\r
  70 //* Read the value at 0x0\r
  71     __mac_i =__readMemory32(0x00000000,"Memory");\r
  72     __mac_i =__mac_i+1;\r
  73     __writeMemory32(__mac_i,0x00,"Memory");\r
  74     __mac_pt =__readMemory32(0x00000000,"Memory");\r
  75     \r
  76  if (__mac_i == __mac_pt)  \r
  77  {\r
  78    __message "------------------------------- The Remap is done ----------------------------------------";  \r
  79 //*   Toggel RESET The remap\r
  80     __writeMemory32(0x00000001,0xFFFFFF00,"Memory");\r
  81    \r
  82  } else {  \r
  83    __message "------------------------------- The Remap is NOT -----------------------------------------";  \r
  84  }\r
  85 \r
  86 }\r
  87 \r
  88 \r
  89 execUserSetup()\r
  90 {\r
  91  ini();\r
  92      __message "-------------------------------Set PC ----------------------------------------";  \r
  93      __writeMemory32(0x00000000,0xB4,"Register");\r
  94 }\r
  95 \r
  96 //-----------------------------------------------------------------------------\r
  97 // Reset the Interrupt Controller\r
  98 //-------------------------------\r
  99 // Normally, the code is executed only if a reset has been actually performed.\r
 100 // So, the AIC initialization resumes at setting up the default vectors.\r
 101 //-----------------------------------------------------------------------------\r
 102 AIC()\r
 103 {\r
 104 // Mask All interrupt pAic->AIC_IDCR = 0xFFFFFFFF;\r
 105     __writeMemory32(0xffffffff,0xFFFFF124,"Memory");\r
 106     __writeMemory32(0xffffffff,0xFFFFF128,"Memory");\r
 107 // disable peripheral clock  Peripheral Clock Disable Register\r
 108     __writeMemory32(0xffffffff,0xFFFFFC14,"Memory");\r
 109 \r
 110 // #define AT91C_TC0_SR    ((AT91_REG *)        0xFFFA0020) // (TC0) Status Register\r
 111 // #define AT91C_TC1_SR    ((AT91_REG *)        0xFFFA0060) // (TC1) Status Register\r
 112 // #define AT91C_TC2_SR    ((AT91_REG *)        0xFFFA00A0) // (TC2) Status Register\r
 113     __readMemory32(0xFFFA0020,"Memory");\r
 114     __readMemory32(0xFFFA0060,"Memory");\r
 115     __readMemory32(0xFFFA00A0,"Memory");\r
 116 \r
 117     for (__mac_i=0;__mac_i < 8; __mac_i++)\r
 118     {\r
 119       // AT91C_BASE_AIC->AIC_EOICR\r
 120       __mac_pt  =  __readMemory32(0xFFFFF130,"Memory");\r
 121     \r
 122     }\r
 123    __message "------------------------------- AIC 2 INIT ---------------------------------------------";  \r
 124 }\r
 125 \r
 126 ini()\r
 127 {\r
 128 __writeMemory32(0x0,0x00,"Register");\r
 129 __writeMemory32(0x0,0x04,"Register");\r
 130 __writeMemory32(0x0,0x08,"Register");\r
 131 __writeMemory32(0x0,0x0C,"Register");\r
 132 __writeMemory32(0x0,0x10,"Register");\r
 133 __writeMemory32(0x0,0x14,"Register");\r
 134 __writeMemory32(0x0,0x18,"Register");\r
 135 __writeMemory32(0x0,0x1C,"Register");\r
 136 __writeMemory32(0x0,0x20,"Register");\r
 137 __writeMemory32(0x0,0x24,"Register");\r
 138 __writeMemory32(0x0,0x28,"Register");\r
 139 __writeMemory32(0x0,0x2C,"Register");\r
 140 __writeMemory32(0x0,0x30,"Register");\r
 141 __writeMemory32(0x0,0x34,"Register");\r
 142 __writeMemory32(0x0,0x38,"Register");\r
 143 \r
 144 // Set CPSR\r
 145 __writeMemory32(0x0D3,0x98,"Register");\r
 146 \r
 147 \r
 148 }\r
 149 \r
 150 RG()\r
 151 {\r
 152 \r
 153 __mac_i =__readMemory32(0x00,"Register");   __message "R00 0x",__mac_i:%X;  \r
 154 __mac_i =__readMemory32(0x04,"Register");   __message "R01 0x",__mac_i:%X;  \r
 155 __mac_i =__readMemory32(0x08,"Register");   __message "R02 0x",__mac_i:%X;  \r
 156 __mac_i =__readMemory32(0x0C,"Register");   __message "R03 0x",__mac_i:%X;  \r
 157 __mac_i =__readMemory32(0x10,"Register");   __message "R04 0x",__mac_i:%X;  \r
 158 __mac_i =__readMemory32(0x14,"Register");   __message "R05 0x",__mac_i:%X;  \r
 159 __mac_i =__readMemory32(0x18,"Register");   __message "R06 0x",__mac_i:%X;  \r
 160 __mac_i =__readMemory32(0x1C,"Register");   __message "R07 0x",__mac_i:%X;  \r
 161 __mac_i =__readMemory32(0x20,"Register");   __message "R08 0x",__mac_i:%X;  \r
 162 __mac_i =__readMemory32(0x24,"Register");   __message "R09 0x",__mac_i:%X;  \r
 163 __mac_i =__readMemory32(0x28,"Register");   __message "R10 0x",__mac_i:%X;  \r
 164 __mac_i =__readMemory32(0x2C,"Register");   __message "R11 0x",__mac_i:%X;  \r
 165 __mac_i =__readMemory32(0x30,"Register");   __message "R12 0x",__mac_i:%X;  \r
 166 __mac_i =__readMemory32(0x34,"Register");   __message "R13 0x",__mac_i:%X;  \r
 167 __mac_i =__readMemory32(0x38,"Register");   __message "R14 0x",__mac_i:%X;  \r
 168 __mac_i =__readMemory32(0x3C,"Register");   __message "R13 SVC 0x",__mac_i:%X;  \r
 169 __mac_i =__readMemory32(0x40,"Register");   __message "R14 SVC 0x",__mac_i:%X;  \r
 170 __mac_i =__readMemory32(0x44,"Register");   __message "R13 ABT 0x",__mac_i:%X;  \r
 171 __mac_i =__readMemory32(0x48,"Register");   __message "R14 ABT 0x",__mac_i:%X;  \r
 172 __mac_i =__readMemory32(0x4C,"Register");   __message "R13 UND 0x",__mac_i:%X;  \r
 173 __mac_i =__readMemory32(0x50,"Register");   __message "R14 UND 0x",__mac_i:%X;  \r
 174 __mac_i =__readMemory32(0x54,"Register");   __message "R13 IRQ 0x",__mac_i:%X;  \r
 175 __mac_i =__readMemory32(0x58,"Register");   __message "R14 IRQ 0x",__mac_i:%X;  \r
 176 __mac_i =__readMemory32(0x5C,"Register");   __message "R08 FIQ 0x",__mac_i:%X;  \r
 177 __mac_i =__readMemory32(0x60,"Register");   __message "R09 FIQ 0x",__mac_i:%X;  \r
 178 __mac_i =__readMemory32(0x64,"Register");   __message "R10 FIQ 0x",__mac_i:%X;  \r
 179 __mac_i =__readMemory32(0x68,"Register");   __message "R11 FIQ 0x",__mac_i:%X;  \r
 180 __mac_i =__readMemory32(0x6C,"Register");   __message "R12 FIQ 0x",__mac_i:%X;  \r
 181 __mac_i =__readMemory32(0x70,"Register");   __message "R13 FIQ 0x",__mac_i:%X;  \r
 182 __mac_i =__readMemory32(0x74,"Register");   __message "R14 FIQ0x",__mac_i:%X; \r
 183 __mac_i =__readMemory32(0x98,"Register");   __message "CPSR     ",__mac_i:%X; \r
 184 __mac_i =__readMemory32(0x94,"Register");   __message "SPSR     ",__mac_i:%X; \r
 185 __mac_i =__readMemory32(0x9C,"Register");   __message "SPSR ABT ",__mac_i:%X; \r
 186 __mac_i =__readMemory32(0xA0,"Register");   __message "SPSR ABT ",__mac_i:%X; \r
 187 __mac_i =__readMemory32(0xA4,"Register");   __message "SPSR UND ",__mac_i:%X; \r
 188 __mac_i =__readMemory32(0xA8,"Register");   __message "SPSR IRQ ",__mac_i:%X; \r
 189 __mac_i =__readMemory32(0xAC,"Register");   __message "SPSR FIQ ",__mac_i:%X; \r
 190 \r
 191 __mac_i =__readMemory32(0xB4,"Register");   __message "PC 0x",__mac_i:%X;  \r
 192 \r
 193 }\r
 194 \r