2 * FreeRTOS Kernel V10.2.1
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3 * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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28 /* Standard includes. */
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31 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
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32 * is defined correctly and privileged functions are placed in correct sections. */
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33 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
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35 /* Portasm includes. */
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36 #include "portasm.h"
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38 /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
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40 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
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42 #if( configENABLE_FPU == 1 )
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43 #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
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46 void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
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50 " .syntax unified \n"
\r
52 " ldr r2, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
\r
53 " ldr r3, [r2] \n" /* Read pxCurrentTCB. */
\r
54 " ldr r0, [r3] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
\r
56 #if( configENABLE_MPU == 1 )
\r
57 " dmb \n" /* Complete outstanding transfers before disabling MPU. */
\r
58 " ldr r2, xMPUCTRLConst2 \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
\r
59 " ldr r4, [r2] \n" /* Read the value of MPU_CTRL. */
\r
60 " movs r5, #1 \n" /* r5 = 1. */
\r
61 " bics r4, r5 \n" /* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */
\r
62 " str r4, [r2] \n" /* Disable MPU. */
\r
64 " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
\r
65 " ldr r4, [r3] \n" /* r4 = *r3 i.e. r4 = MAIR0. */
\r
66 " ldr r2, xMAIR0Const2 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
\r
67 " str r4, [r2] \n" /* Program MAIR0. */
\r
68 " ldr r2, xRNRConst2 \n" /* r2 = 0xe000ed98 [Location of RNR]. */
\r
69 " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
\r
70 " movs r5, #4 \n" /* r5 = 4. */
\r
71 " str r5, [r2] \n" /* Program RNR = 4. */
\r
72 " ldmia r3!, {r6,r7} \n" /* Read first set of RBAR/RLAR from TCB. */
\r
73 " ldr r4, xRBARConst2 \n" /* r4 = 0xe000ed9c [Location of RBAR]. */
\r
74 " stmia r4!, {r6,r7} \n" /* Write first set of RBAR/RLAR registers. */
\r
75 " movs r5, #5 \n" /* r5 = 5. */
\r
76 " str r5, [r2] \n" /* Program RNR = 5. */
\r
77 " ldmia r3!, {r6,r7} \n" /* Read second set of RBAR/RLAR from TCB. */
\r
78 " ldr r4, xRBARConst2 \n" /* r4 = 0xe000ed9c [Location of RBAR]. */
\r
79 " stmia r4!, {r6,r7} \n" /* Write second set of RBAR/RLAR registers. */
\r
80 " movs r5, #6 \n" /* r5 = 6. */
\r
81 " str r5, [r2] \n" /* Program RNR = 6. */
\r
82 " ldmia r3!, {r6,r7} \n" /* Read third set of RBAR/RLAR from TCB. */
\r
83 " ldr r4, xRBARConst2 \n" /* r4 = 0xe000ed9c [Location of RBAR]. */
\r
84 " stmia r4!, {r6,r7} \n" /* Write third set of RBAR/RLAR registers. */
\r
85 " movs r5, #7 \n" /* r5 = 7. */
\r
86 " str r5, [r2] \n" /* Program RNR = 7. */
\r
87 " ldmia r3!, {r6,r7} \n" /* Read fourth set of RBAR/RLAR from TCB. */
\r
88 " ldr r4, xRBARConst2 \n" /* r4 = 0xe000ed9c [Location of RBAR]. */
\r
89 " stmia r4!, {r6,r7} \n" /* Write fourth set of RBAR/RLAR registers. */
\r
91 " ldr r2, xMPUCTRLConst2 \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
\r
92 " ldr r4, [r2] \n" /* Read the value of MPU_CTRL. */
\r
93 " movs r5, #1 \n" /* r5 = 1. */
\r
94 " orrs r4, r5 \n" /* r4 = r4 | r5 i.e. Set the bit 0 in r4. */
\r
95 " str r4, [r2] \n" /* Enable MPU. */
\r
96 " dsb \n" /* Force memory writes before continuing. */
\r
97 #endif /* configENABLE_MPU */
\r
99 #if( configENABLE_MPU == 1 )
\r
100 " ldm r0!, {r1-r4} \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
\r
101 " ldr r5, xSecureContextConst2 \n"
\r
102 " str r1, [r5] \n" /* Set xSecureContext to this task's value for the same. */
\r
103 " msr psplim, r2 \n" /* Set this task's PSPLIM value. */
\r
104 " msr control, r3 \n" /* Set this task's CONTROL value. */
\r
105 " adds r0, #32 \n" /* Discard everything up to r0. */
\r
106 " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */
\r
108 " bx r4 \n" /* Finally, branch to EXC_RETURN. */
\r
109 #else /* configENABLE_MPU */
\r
110 " ldm r0!, {r1-r3} \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
\r
111 " ldr r4, xSecureContextConst2 \n"
\r
112 " str r1, [r4] \n" /* Set xSecureContext to this task's value for the same. */
\r
113 " msr psplim, r2 \n" /* Set this task's PSPLIM value. */
\r
114 " movs r1, #2 \n" /* r1 = 2. */
\r
115 " msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */
\r
116 " adds r0, #32 \n" /* Discard everything up to r0. */
\r
117 " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */
\r
119 " bx r3 \n" /* Finally, branch to EXC_RETURN. */
\r
120 #endif /* configENABLE_MPU */
\r
123 "pxCurrentTCBConst2: .word pxCurrentTCB \n"
\r
124 "xSecureContextConst2: .word xSecureContext \n"
\r
125 #if( configENABLE_MPU == 1 )
\r
126 "xMPUCTRLConst2: .word 0xe000ed94 \n"
\r
127 "xMAIR0Const2: .word 0xe000edc0 \n"
\r
128 "xRNRConst2: .word 0xe000ed98 \n"
\r
129 "xRBARConst2: .word 0xe000ed9c \n"
\r
130 #endif /* configENABLE_MPU */
\r
133 /*-----------------------------------------------------------*/
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135 BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
\r
139 " mrs r0, control \n" /* r0 = CONTROL. */
\r
140 " movs r1, #1 \n" /* r1 = 1. */
\r
141 " tst r0, r1 \n" /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
\r
142 " beq running_privileged \n" /* If the result of previous AND operation was 0, branch. */
\r
143 " movs r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
\r
144 " bx lr \n" /* Return. */
\r
145 " running_privileged: \n"
\r
146 " movs r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
\r
147 " bx lr \n" /* Return. */
\r
150 ::: "r0", "r1", "memory"
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153 /*-----------------------------------------------------------*/
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155 void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
\r
159 " mrs r0, control \n" /* Read the CONTROL register. */
\r
160 " movs r1, #1 \n" /* r1 = 1. */
\r
161 " bics r0, r1 \n" /* Clear the bit 0. */
\r
162 " msr control, r0 \n" /* Write back the new CONTROL value. */
\r
163 " bx lr \n" /* Return to the caller. */
\r
164 ::: "r0", "r1", "memory"
\r
167 /*-----------------------------------------------------------*/
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169 void vResetPrivilege( void ) /* __attribute__ (( naked )) */
\r
173 " mrs r0, control \n" /* r0 = CONTROL. */
\r
174 " movs r1, #1 \n" /* r1 = 1. */
\r
175 " orrs r0, r1 \n" /* r0 = r0 | r1. */
\r
176 " msr control, r0 \n" /* CONTROL = r0. */
\r
177 " bx lr \n" /* Return to the caller. */
\r
178 :::"r0", "r1", "memory"
\r
181 /*-----------------------------------------------------------*/
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183 void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
\r
187 " ldr r0, xVTORConst \n" /* Use the NVIC offset register to locate the stack. */
\r
188 " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */
\r
189 " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */
\r
190 " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */
\r
191 " cpsie i \n" /* Globally enable interrupts. */
\r
194 " svc %0 \n" /* System call to start the first task. */
\r
198 "xVTORConst: .word 0xe000ed08 \n"
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199 :: "i" ( portSVC_START_SCHEDULER ) : "memory"
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202 /*-----------------------------------------------------------*/
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204 uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
\r
208 " mrs r0, PRIMASK \n"
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214 /*-----------------------------------------------------------*/
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216 void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
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220 " msr PRIMASK, r0 \n"
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225 /*-----------------------------------------------------------*/
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227 void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
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231 " .syntax unified \n"
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232 " .extern SecureContext_SaveContext \n"
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233 " .extern SecureContext_LoadContext \n"
\r
235 " mrs r1, psp \n" /* Read PSP in r1. */
\r
236 " ldr r2, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
\r
237 " ldr r0, [r2] \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
\r
239 " cbz r0, save_ns_context \n" /* No secure context to save. */
\r
240 " push {r0-r2, r14} \n"
\r
241 " bl SecureContext_SaveContext \n"
\r
242 " pop {r0-r3} \n" /* LR is now in r3. */
\r
243 " mov lr, r3 \n" /* LR = r3. */
\r
244 " lsls r2, r3, #25 \n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
\r
245 " bpl save_ns_context \n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
\r
246 " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
\r
247 " ldr r2, [r3] \n" /* Read pxCurrentTCB. */
\r
248 #if( configENABLE_MPU == 1 )
\r
249 " subs r1, r1, #16 \n" /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
\r
250 " str r1, [r2] \n" /* Save the new top of stack in TCB. */
\r
251 " mrs r2, psplim \n" /* r2 = PSPLIM. */
\r
252 " mrs r3, control \n" /* r3 = CONTROL. */
\r
253 " mov r4, lr \n" /* r4 = LR/EXC_RETURN. */
\r
254 " stmia r1!, {r0, r2-r4} \n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
\r
255 #else /* configENABLE_MPU */
\r
256 " subs r1, r1, #12 \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
\r
257 " str r1, [r2] \n" /* Save the new top of stack in TCB. */
\r
258 " mrs r2, psplim \n" /* r2 = PSPLIM. */
\r
259 " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */
\r
260 " stmia r1!, {r0, r2-r3} \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
\r
261 #endif /* configENABLE_MPU */
\r
262 " b select_next_task \n"
\r
264 " save_ns_context: \n"
\r
265 " ldr r3, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
\r
266 " ldr r2, [r3] \n" /* Read pxCurrentTCB. */
\r
267 #if( configENABLE_MPU == 1 )
\r
268 " subs r1, r1, #48 \n" /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
\r
269 " str r1, [r2] \n" /* Save the new top of stack in TCB. */
\r
270 " adds r1, r1, #16 \n" /* r1 = r1 + 16. */
\r
271 " stmia r1!, {r4-r7} \n" /* Store the low registers that are not saved automatically. */
\r
272 " mov r4, r8 \n" /* r4 = r8. */
\r
273 " mov r5, r9 \n" /* r5 = r9. */
\r
274 " mov r6, r10 \n" /* r6 = r10. */
\r
275 " mov r7, r11 \n" /* r7 = r11. */
\r
276 " stmia r1!, {r4-r7} \n" /* Store the high registers that are not saved automatically. */
\r
277 " mrs r2, psplim \n" /* r2 = PSPLIM. */
\r
278 " mrs r3, control \n" /* r3 = CONTROL. */
\r
279 " mov r4, lr \n" /* r4 = LR/EXC_RETURN. */
\r
280 " subs r1, r1, #48 \n" /* r1 = r1 - 48. */
\r
281 " stmia r1!, {r0, r2-r4} \n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
\r
282 #else /* configENABLE_MPU */
\r
283 " subs r1, r1, #44 \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
\r
284 " str r1, [r2] \n" /* Save the new top of stack in TCB. */
\r
285 " mrs r2, psplim \n" /* r2 = PSPLIM. */
\r
286 " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */
\r
287 " stmia r1!, {r0, r2-r7} \n" /* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */
\r
288 " mov r4, r8 \n" /* r4 = r8. */
\r
289 " mov r5, r9 \n" /* r5 = r9. */
\r
290 " mov r6, r10 \n" /* r6 = r10. */
\r
291 " mov r7, r11 \n" /* r7 = r11. */
\r
292 " stmia r1!, {r4-r7} \n" /* Store the high registers that are not saved automatically. */
\r
293 #endif /* configENABLE_MPU */
\r
295 " select_next_task: \n"
\r
297 " bl vTaskSwitchContext \n"
\r
300 " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
\r
301 " ldr r3, [r2] \n" /* Read pxCurrentTCB. */
\r
302 " ldr r1, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
\r
304 #if( configENABLE_MPU == 1 )
\r
305 " dmb \n" /* Complete outstanding transfers before disabling MPU. */
\r
306 " ldr r2, xMPUCTRLConst \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
\r
307 " ldr r4, [r2] \n" /* Read the value of MPU_CTRL. */
\r
308 " movs r5, #1 \n" /* r5 = 1. */
\r
309 " bics r4, r5 \n" /* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */
\r
310 " str r4, [r2] \n" /* Disable MPU. */
\r
312 " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
\r
313 " ldr r4, [r3] \n" /* r4 = *r3 i.e. r4 = MAIR0. */
\r
314 " ldr r2, xMAIR0Const \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
\r
315 " str r4, [r2] \n" /* Program MAIR0. */
\r
316 " ldr r2, xRNRConst \n" /* r2 = 0xe000ed98 [Location of RNR]. */
\r
317 " adds r3, #4 \n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
\r
318 " movs r5, #4 \n" /* r5 = 4. */
\r
319 " str r5, [r2] \n" /* Program RNR = 4. */
\r
320 " ldmia r3!, {r6,r7} \n" /* Read first set of RBAR/RLAR from TCB. */
\r
321 " ldr r4, xRBARConst \n" /* r4 = 0xe000ed9c [Location of RBAR]. */
\r
322 " stmia r4!, {r6,r7} \n" /* Write first set of RBAR/RLAR registers. */
\r
323 " movs r5, #5 \n" /* r5 = 5. */
\r
324 " str r5, [r2] \n" /* Program RNR = 5. */
\r
325 " ldmia r3!, {r6,r7} \n" /* Read second set of RBAR/RLAR from TCB. */
\r
326 " ldr r4, xRBARConst \n" /* r4 = 0xe000ed9c [Location of RBAR]. */
\r
327 " stmia r4!, {r6,r7} \n" /* Write second set of RBAR/RLAR registers. */
\r
328 " movs r5, #6 \n" /* r5 = 6. */
\r
329 " str r5, [r2] \n" /* Program RNR = 6. */
\r
330 " ldmia r3!, {r6,r7} \n" /* Read third set of RBAR/RLAR from TCB. */
\r
331 " ldr r4, xRBARConst \n" /* r4 = 0xe000ed9c [Location of RBAR]. */
\r
332 " stmia r4!, {r6,r7} \n" /* Write third set of RBAR/RLAR registers. */
\r
333 " movs r5, #7 \n" /* r5 = 7. */
\r
334 " str r5, [r2] \n" /* Program RNR = 7. */
\r
335 " ldmia r3!, {r6,r7} \n" /* Read fourth set of RBAR/RLAR from TCB. */
\r
336 " ldr r4, xRBARConst \n" /* r4 = 0xe000ed9c [Location of RBAR]. */
\r
337 " stmia r4!, {r6,r7} \n" /* Write fourth set of RBAR/RLAR registers. */
\r
339 " ldr r2, xMPUCTRLConst \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
\r
340 " ldr r4, [r2] \n" /* Read the value of MPU_CTRL. */
\r
341 " movs r5, #1 \n" /* r5 = 1. */
\r
342 " orrs r4, r5 \n" /* r4 = r4 | r5 i.e. Set the bit 0 in r4. */
\r
343 " str r4, [r2] \n" /* Enable MPU. */
\r
344 " dsb \n" /* Force memory writes before continuing. */
\r
345 #endif /* configENABLE_MPU */
\r
347 #if( configENABLE_MPU == 1 )
\r
348 " ldmia r1!, {r0, r2-r4} \n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
\r
349 " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */
\r
350 " msr control, r3 \n" /* Restore the CONTROL register value for the task. */
\r
351 " mov lr, r4 \n" /* LR = r4. */
\r
352 " ldr r2, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
\r
353 " str r0, [r2] \n" /* Restore the task's xSecureContext. */
\r
354 " cbz r0, restore_ns_context \n" /* If there is no secure context for the task, restore the non-secure context. */
\r
356 " bl SecureContext_LoadContext \n" /* Restore the secure context. */
\r
358 " mov lr, r4 \n" /* LR = r4. */
\r
359 " lsls r2, r4, #25 \n" /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
\r
360 " bpl restore_ns_context \n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
\r
361 " msr psp, r1 \n" /* Remember the new top of stack for the task. */
\r
363 #else /* configENABLE_MPU */
\r
364 " ldmia r1!, {r0, r2-r3} \n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
\r
365 " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */
\r
366 " mov lr, r3 \n" /* LR = r3. */
\r
367 " ldr r2, xSecureContextConst \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
\r
368 " str r0, [r2] \n" /* Restore the task's xSecureContext. */
\r
369 " cbz r0, restore_ns_context \n" /* If there is no secure context for the task, restore the non-secure context. */
\r
371 " bl SecureContext_LoadContext \n" /* Restore the secure context. */
\r
373 " mov lr, r3 \n" /* LR = r3. */
\r
374 " lsls r2, r3, #25 \n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
\r
375 " bpl restore_ns_context \n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
\r
376 " msr psp, r1 \n" /* Remember the new top of stack for the task. */
\r
378 #endif /* configENABLE_MPU */
\r
380 " restore_ns_context: \n"
\r
381 " adds r1, r1, #16 \n" /* Move to the high registers. */
\r
382 " ldmia r1!, {r4-r7} \n" /* Restore the high registers that are not automatically restored. */
\r
383 " mov r8, r4 \n" /* r8 = r4. */
\r
384 " mov r9, r5 \n" /* r9 = r5. */
\r
385 " mov r10, r6 \n" /* r10 = r6. */
\r
386 " mov r11, r7 \n" /* r11 = r7. */
\r
387 " msr psp, r1 \n" /* Remember the new top of stack for the task. */
\r
388 " subs r1, r1, #32 \n" /* Go back to the low registers. */
\r
389 " ldmia r1!, {r4-r7} \n" /* Restore the low registers that are not automatically restored. */
\r
393 "pxCurrentTCBConst: .word pxCurrentTCB \n"
\r
394 "xSecureContextConst: .word xSecureContext \n"
\r
395 #if( configENABLE_MPU == 1 )
\r
396 "xMPUCTRLConst: .word 0xe000ed94 \n"
\r
397 "xMAIR0Const: .word 0xe000edc0 \n"
\r
398 "xRNRConst: .word 0xe000ed98 \n"
\r
399 "xRBARConst: .word 0xe000ed9c \n"
\r
400 #endif /* configENABLE_MPU */
\r
403 /*-----------------------------------------------------------*/
\r
405 void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
\r
412 " beq stacking_used_msp \n"
\r
414 " ldr r2, svchandler_address_const \n"
\r
416 " stacking_used_msp: \n"
\r
418 " ldr r2, svchandler_address_const \n"
\r
422 "svchandler_address_const: .word vPortSVCHandler_C \n"
\r
425 /*-----------------------------------------------------------*/
\r
427 void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */
\r
431 " svc %0 \n" /* Secure context is allocated in the supervisor call. */
\r
432 " bx lr \n" /* Return. */
\r
433 :: "i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
\r
436 /*-----------------------------------------------------------*/
\r
438 void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
\r
442 " ldr r1, [r0] \n" /* The first item in the TCB is the top of the stack. */
\r
443 " ldr r0, [r1] \n" /* The first item on the stack is the task's xSecureContext. */
\r
444 " cmp r0, #0 \n" /* Raise svc if task's xSecureContext is not NULL. */
\r
445 " beq free_secure_context \n"
\r
446 " bx lr \n" /* There is no secure context (xSecureContext is NULL). */
\r
447 " free_secure_context: \n"
\r
448 " svc %0 \n" /* Secure context is freed in the supervisor call. */
\r
449 " bx lr \n" /* Return. */
\r
450 :: "i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"
\r
453 /*-----------------------------------------------------------*/
\r
projects / freertos / blob