2 * FreeRTOS Kernel V10.2.1
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3 * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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28 /* Standard includes. */
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31 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
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32 * is defined correctly and privileged functions are placed in correct sections. */
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33 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
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35 /* Portasm includes. */
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36 #include "portasm.h"
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38 /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
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40 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
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42 #if( configENABLE_FPU == 1 )
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43 #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
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46 void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
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50 " .syntax unified \n"
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52 " ldr r2, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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53 " ldr r1, [r2] \n" /* Read pxCurrentTCB. */
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54 " ldr r0, [r1] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
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56 #if( configENABLE_MPU == 1 )
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57 " dmb \n" /* Complete outstanding transfers before disabling MPU. */
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58 " ldr r2, xMPUCTRLConst2 \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
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59 " ldr r3, [r2] \n" /* Read the value of MPU_CTRL. */
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60 " movs r4, #1 \n" /* r4 = 1. */
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61 " bics r3, r4 \n" /* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */
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62 " str r3, [r2] \n" /* Disable MPU. */
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64 " adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
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65 " ldr r4, [r1] \n" /* r4 = *r1 i.e. r4 = MAIR0. */
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66 " ldr r2, xMAIR0Const2 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
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67 " str r4, [r2] \n" /* Program MAIR0. */
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68 " ldr r2, xRNRConst2 \n" /* r2 = 0xe000ed98 [Location of RNR]. */
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69 " adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
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70 " movs r4, #4 \n" /* r4 = 4. */
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71 " str r4, [r2] \n" /* Program RNR = 4. */
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72 " ldmia r1!, {r5,r6} \n" /* Read first set of RBAR/RLAR from TCB. */
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73 " ldr r3, xRBARConst2 \n" /* r3 = 0xe000ed9c [Location of RBAR]. */
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74 " stmia r3!, {r5,r6} \n" /* Write first set of RBAR/RLAR registers. */
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75 " movs r4, #5 \n" /* r4 = 5. */
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76 " str r4, [r2] \n" /* Program RNR = 5. */
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77 " ldmia r1!, {r5,r6} \n" /* Read second set of RBAR/RLAR from TCB. */
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78 " ldr r3, xRBARConst2 \n" /* r3 = 0xe000ed9c [Location of RBAR]. */
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79 " stmia r3!, {r5,r6} \n" /* Write second set of RBAR/RLAR registers. */
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80 " movs r4, #6 \n" /* r4 = 6. */
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81 " str r4, [r2] \n" /* Program RNR = 6. */
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82 " ldmia r1!, {r5,r6} \n" /* Read third set of RBAR/RLAR from TCB. */
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83 " ldr r3, xRBARConst2 \n" /* r3 = 0xe000ed9c [Location of RBAR]. */
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84 " stmia r3!, {r5,r6} \n" /* Write third set of RBAR/RLAR registers. */
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85 " movs r4, #7 \n" /* r4 = 7. */
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86 " str r4, [r2] \n" /* Program RNR = 7. */
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87 " ldmia r1!, {r5,r6} \n" /* Read fourth set of RBAR/RLAR from TCB. */
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88 " ldr r3, xRBARConst2 \n" /* r3 = 0xe000ed9c [Location of RBAR]. */
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89 " stmia r3!, {r5,r6} \n" /* Write fourth set of RBAR/RLAR registers. */
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91 " ldr r2, xMPUCTRLConst2 \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
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92 " ldr r3, [r2] \n" /* Read the value of MPU_CTRL. */
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93 " movs r4, #1 \n" /* r4 = 1. */
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94 " orrs r3, r4 \n" /* r3 = r3 | r4 i.e. Set the bit 0 in r3. */
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95 " str r3, [r2] \n" /* Enable MPU. */
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96 " dsb \n" /* Force memory writes before continuing. */
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97 #endif /* configENABLE_MPU */
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99 #if( configENABLE_MPU == 1 )
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100 " ldm r0!, {r1-r3} \n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
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101 " msr psplim, r1 \n" /* Set this task's PSPLIM value. */
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102 " msr control, r2 \n" /* Set this task's CONTROL value. */
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103 " adds r0, #32 \n" /* Discard everything up to r0. */
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104 " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */
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106 " bx r3 \n" /* Finally, branch to EXC_RETURN. */
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107 #else /* configENABLE_MPU */
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108 " ldm r0!, {r1-r2} \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
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109 " msr psplim, r1 \n" /* Set this task's PSPLIM value. */
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110 " movs r1, #2 \n" /* r1 = 2. */
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111 " msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */
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112 " adds r0, #32 \n" /* Discard everything up to r0. */
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113 " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */
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115 " bx r2 \n" /* Finally, branch to EXC_RETURN. */
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116 #endif /* configENABLE_MPU */
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119 "pxCurrentTCBConst2: .word pxCurrentTCB \n"
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120 #if( configENABLE_MPU == 1 )
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121 "xMPUCTRLConst2: .word 0xe000ed94 \n"
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122 "xMAIR0Const2: .word 0xe000edc0 \n"
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123 "xRNRConst2: .word 0xe000ed98 \n"
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124 "xRBARConst2: .word 0xe000ed9c \n"
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125 #endif /* configENABLE_MPU */
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128 /*-----------------------------------------------------------*/
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130 BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
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134 " mrs r0, control \n" /* r0 = CONTROL. */
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135 " movs r1, #1 \n" /* r1 = 1. */
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136 " tst r0, r1 \n" /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
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137 " beq running_privileged \n" /* If the result of previous AND operation was 0, branch. */
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138 " movs r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
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139 " bx lr \n" /* Return. */
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140 " running_privileged: \n"
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141 " movs r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
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142 " bx lr \n" /* Return. */
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145 ::: "r0", "r1", "memory"
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148 /*-----------------------------------------------------------*/
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150 void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
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154 " mrs r0, control \n" /* Read the CONTROL register. */
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155 " movs r1, #1 \n" /* r1 = 1. */
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156 " bics r0, r1 \n" /* Clear the bit 0. */
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157 " msr control, r0 \n" /* Write back the new CONTROL value. */
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158 " bx lr \n" /* Return to the caller. */
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159 ::: "r0", "r1", "memory"
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162 /*-----------------------------------------------------------*/
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164 void vResetPrivilege( void ) /* __attribute__ (( naked )) */
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168 " mrs r0, control \n" /* r0 = CONTROL. */
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169 " movs r1, #1 \n" /* r1 = 1. */
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170 " orrs r0, r1 \n" /* r0 = r0 | r1. */
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171 " msr control, r0 \n" /* CONTROL = r0. */
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172 " bx lr \n" /* Return to the caller. */
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173 :::"r0", "r1", "memory"
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176 /*-----------------------------------------------------------*/
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178 void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
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182 " ldr r0, xVTORConst \n" /* Use the NVIC offset register to locate the stack. */
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183 " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */
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184 " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */
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185 " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */
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186 " cpsie i \n" /* Globally enable interrupts. */
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189 " svc %0 \n" /* System call to start the first task. */
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193 "xVTORConst: .word 0xe000ed08 \n"
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194 :: "i" ( portSVC_START_SCHEDULER ) : "memory"
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197 /*-----------------------------------------------------------*/
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199 uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
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203 " mrs r0, PRIMASK \n"
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209 /*-----------------------------------------------------------*/
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211 void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
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215 " msr PRIMASK, r0 \n"
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220 /*-----------------------------------------------------------*/
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222 void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
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226 " .syntax unified \n"
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228 " mrs r0, psp \n" /* Read PSP in r0. */
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229 " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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230 " ldr r1, [r2] \n" /* Read pxCurrentTCB. */
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231 #if( configENABLE_MPU == 1 )
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232 " subs r0, r0, #44 \n" /* Make space for PSPLIM, CONTROL, LR and the remaining registers on the stack. */
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233 " str r0, [r1] \n" /* Save the new top of stack in TCB. */
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234 " mrs r1, psplim \n" /* r1 = PSPLIM. */
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235 " mrs r2, control \n" /* r2 = CONTROL. */
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236 " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */
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237 " stmia r0!, {r1-r7} \n" /* Store on the stack - PSPLIM, CONTROL, LR and low registers that are not automatically saved. */
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238 " mov r4, r8 \n" /* r4 = r8. */
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239 " mov r5, r9 \n" /* r5 = r9. */
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240 " mov r6, r10 \n" /* r6 = r10. */
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241 " mov r7, r11 \n" /* r7 = r11. */
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242 " stmia r0!, {r4-r7} \n" /* Store the high registers that are not saved automatically. */
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243 #else /* configENABLE_MPU */
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244 " subs r0, r0, #40 \n" /* Make space for PSPLIM, LR and the remaining registers on the stack. */
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245 " str r0, [r1] \n" /* Save the new top of stack in TCB. */
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246 " mrs r2, psplim \n" /* r2 = PSPLIM. */
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247 " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */
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248 " stmia r0!, {r2-r7} \n" /* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */
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249 " mov r4, r8 \n" /* r4 = r8. */
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250 " mov r5, r9 \n" /* r5 = r9. */
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251 " mov r6, r10 \n" /* r6 = r10. */
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252 " mov r7, r11 \n" /* r7 = r11. */
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253 " stmia r0!, {r4-r7} \n" /* Store the high registers that are not saved automatically. */
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254 #endif /* configENABLE_MPU */
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257 " bl vTaskSwitchContext \n"
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260 " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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261 " ldr r1, [r2] \n" /* Read pxCurrentTCB. */
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262 " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
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264 #if( configENABLE_MPU == 1 )
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265 " dmb \n" /* Complete outstanding transfers before disabling MPU. */
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266 " ldr r2, xMPUCTRLConst \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
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267 " ldr r3, [r2] \n" /* Read the value of MPU_CTRL. */
\r
268 " movs r4, #1 \n" /* r4 = 1. */
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269 " bics r3, r4 \n" /* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */
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270 " str r3, [r2] \n" /* Disable MPU. */
\r
272 " adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
\r
273 " ldr r4, [r1] \n" /* r4 = *r1 i.e. r4 = MAIR0. */
\r
274 " ldr r2, xMAIR0Const \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
\r
275 " str r4, [r2] \n" /* Program MAIR0. */
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276 " ldr r2, xRNRConst \n" /* r2 = 0xe000ed98 [Location of RNR]. */
\r
277 " adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
\r
278 " movs r4, #4 \n" /* r4 = 4. */
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279 " str r4, [r2] \n" /* Program RNR = 4. */
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280 " ldmia r1!, {r5,r6} \n" /* Read first set of RBAR/RLAR from TCB. */
\r
281 " ldr r3, xRBARConst \n" /* r3 = 0xe000ed9c [Location of RBAR]. */
\r
282 " stmia r3!, {r5,r6} \n" /* Write first set of RBAR/RLAR registers. */
\r
283 " movs r4, #5 \n" /* r4 = 5. */
\r
284 " str r4, [r2] \n" /* Program RNR = 5. */
\r
285 " ldmia r1!, {r5,r6} \n" /* Read second set of RBAR/RLAR from TCB. */
\r
286 " ldr r3, xRBARConst \n" /* r3 = 0xe000ed9c [Location of RBAR]. */
\r
287 " stmia r3!, {r5,r6} \n" /* Write second set of RBAR/RLAR registers. */
\r
288 " movs r4, #6 \n" /* r4 = 6. */
\r
289 " str r4, [r2] \n" /* Program RNR = 6. */
\r
290 " ldmia r1!, {r5,r6} \n" /* Read third set of RBAR/RLAR from TCB. */
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291 " ldr r3, xRBARConst \n" /* r3 = 0xe000ed9c [Location of RBAR]. */
\r
292 " stmia r3!, {r5,r6} \n" /* Write third set of RBAR/RLAR registers. */
\r
293 " movs r4, #7 \n" /* r4 = 7. */
\r
294 " str r4, [r2] \n" /* Program RNR = 7. */
\r
295 " ldmia r1!, {r5,r6} \n" /* Read fourth set of RBAR/RLAR from TCB. */
\r
296 " ldr r3, xRBARConst \n" /* r3 = 0xe000ed9c [Location of RBAR]. */
\r
297 " stmia r3!, {r5,r6} \n" /* Write fourth set of RBAR/RLAR registers. */
\r
299 " ldr r2, xMPUCTRLConst \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
\r
300 " ldr r3, [r2] \n" /* Read the value of MPU_CTRL. */
\r
301 " movs r4, #1 \n" /* r4 = 1. */
\r
302 " orrs r3, r4 \n" /* r3 = r3 | r4 i.e. Set the bit 0 in r3. */
\r
303 " str r3, [r2] \n" /* Enable MPU. */
\r
304 " dsb \n" /* Force memory writes before continuing. */
\r
305 #endif /* configENABLE_MPU */
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307 #if( configENABLE_MPU == 1 )
\r
308 " adds r0, r0, #28 \n" /* Move to the high registers. */
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309 " ldmia r0!, {r4-r7} \n" /* Restore the high registers that are not automatically restored. */
\r
310 " mov r8, r4 \n" /* r8 = r4. */
\r
311 " mov r9, r5 \n" /* r9 = r5. */
\r
312 " mov r10, r6 \n" /* r10 = r6. */
\r
313 " mov r11, r7 \n" /* r11 = r7. */
\r
314 " msr psp, r0 \n" /* Remember the new top of stack for the task. */
\r
315 " subs r0, r0, #44 \n" /* Move to the starting of the saved context. */
\r
316 " ldmia r0!, {r1-r7} \n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r7 restored. */
\r
317 " msr psplim, r1 \n" /* Restore the PSPLIM register value for the task. */
\r
318 " msr control, r2 \n" /* Restore the CONTROL register value for the task. */
\r
320 #else /* configENABLE_MPU */
\r
321 " adds r0, r0, #24 \n" /* Move to the high registers. */
\r
322 " ldmia r0!, {r4-r7} \n" /* Restore the high registers that are not automatically restored. */
\r
323 " mov r8, r4 \n" /* r8 = r4. */
\r
324 " mov r9, r5 \n" /* r9 = r5. */
\r
325 " mov r10, r6 \n" /* r10 = r6. */
\r
326 " mov r11, r7 \n" /* r11 = r7. */
\r
327 " msr psp, r0 \n" /* Remember the new top of stack for the task. */
\r
328 " subs r0, r0, #40 \n" /* Move to the starting of the saved context. */
\r
329 " ldmia r0!, {r2-r7} \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */
\r
330 " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */
\r
332 #endif /* configENABLE_MPU */
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335 "pxCurrentTCBConst: .word pxCurrentTCB \n"
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336 #if( configENABLE_MPU == 1 )
\r
337 "xMPUCTRLConst: .word 0xe000ed94 \n"
\r
338 "xMAIR0Const: .word 0xe000edc0 \n"
\r
339 "xRNRConst: .word 0xe000ed98 \n"
\r
340 "xRBARConst: .word 0xe000ed9c \n"
\r
341 #endif /* configENABLE_MPU */
\r
344 /*-----------------------------------------------------------*/
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346 void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
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353 " beq stacking_used_msp \n"
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355 " ldr r2, svchandler_address_const \n"
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357 " stacking_used_msp: \n"
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359 " ldr r2, svchandler_address_const \n"
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363 "svchandler_address_const: .word vPortSVCHandler_C \n"
\r
366 /*-----------------------------------------------------------*/
\r
projects / freertos / blob