2 * FreeRTOS Kernel V10.2.1
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3 * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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28 /* Standard includes. */
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31 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
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32 * is defined correctly and privileged functions are placed in correct sections. */
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33 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
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35 /* Portasm includes. */
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36 #include "portasm.h"
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38 /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
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40 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
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42 void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
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46 " .syntax unified \n"
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48 " ldr r2, pxCurrentTCBConst2 \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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49 " ldr r1, [r2] \n" /* Read pxCurrentTCB. */
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50 " ldr r0, [r1] \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
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52 #if( configENABLE_MPU == 1 )
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53 " dmb \n" /* Complete outstanding transfers before disabling MPU. */
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54 " ldr r2, xMPUCTRLConst2 \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
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55 " ldr r4, [r2] \n" /* Read the value of MPU_CTRL. */
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56 " bic r4, #1 \n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
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57 " str r4, [r2] \n" /* Disable MPU. */
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59 " adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
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60 " ldr r3, [r1] \n" /* r3 = *r1 i.e. r3 = MAIR0. */
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61 " ldr r2, xMAIR0Const2 \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
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62 " str r3, [r2] \n" /* Program MAIR0. */
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63 " ldr r2, xRNRConst2 \n" /* r2 = 0xe000ed98 [Location of RNR]. */
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64 " movs r3, #4 \n" /* r3 = 4. */
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65 " str r3, [r2] \n" /* Program RNR = 4. */
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66 " adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
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67 " ldr r2, xRBARConst2 \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
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68 " ldmia r1!, {r4-r11} \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
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69 " stmia r2!, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
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71 " ldr r2, xMPUCTRLConst2 \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
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72 " ldr r4, [r2] \n" /* Read the value of MPU_CTRL. */
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73 " orr r4, #1 \n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
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74 " str r4, [r2] \n" /* Enable MPU. */
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75 " dsb \n" /* Force memory writes before continuing. */
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76 #endif /* configENABLE_MPU */
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78 #if( configENABLE_MPU == 1 )
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79 " ldm r0!, {r1-r3} \n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
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80 " msr psplim, r1 \n" /* Set this task's PSPLIM value. */
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81 " msr control, r2 \n" /* Set this task's CONTROL value. */
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82 " adds r0, #32 \n" /* Discard everything up to r0. */
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83 " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */
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85 " bx r3 \n" /* Finally, branch to EXC_RETURN. */
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86 #else /* configENABLE_MPU */
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87 " ldm r0!, {r1-r2} \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
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88 " msr psplim, r1 \n" /* Set this task's PSPLIM value. */
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89 " movs r1, #2 \n" /* r1 = 2. */
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90 " msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */
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91 " adds r0, #32 \n" /* Discard everything up to r0. */
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92 " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */
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94 " bx r2 \n" /* Finally, branch to EXC_RETURN. */
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95 #endif /* configENABLE_MPU */
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98 "pxCurrentTCBConst2: .word pxCurrentTCB \n"
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99 #if( configENABLE_MPU == 1 )
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100 "xMPUCTRLConst2: .word 0xe000ed94 \n"
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101 "xMAIR0Const2: .word 0xe000edc0 \n"
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102 "xRNRConst2: .word 0xe000ed98 \n"
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103 "xRBARConst2: .word 0xe000ed9c \n"
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104 #endif /* configENABLE_MPU */
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107 /*-----------------------------------------------------------*/
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109 BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
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113 " mrs r0, control \n" /* r0 = CONTROL. */
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114 " tst r0, #1 \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
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116 " movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
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117 " moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
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118 " bx lr \n" /* Return. */
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124 /*-----------------------------------------------------------*/
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126 void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
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130 " mrs r0, control \n" /* Read the CONTROL register. */
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131 " bic r0, #1 \n" /* Clear the bit 0. */
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132 " msr control, r0 \n" /* Write back the new CONTROL value. */
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133 " bx lr \n" /* Return to the caller. */
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137 /*-----------------------------------------------------------*/
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139 void vResetPrivilege( void ) /* __attribute__ (( naked )) */
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143 " mrs r0, control \n" /* r0 = CONTROL. */
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144 " orr r0, #1 \n" /* r0 = r0 | 1. */
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145 " msr control, r0 \n" /* CONTROL = r0. */
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146 " bx lr \n" /* Return to the caller. */
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150 /*-----------------------------------------------------------*/
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152 void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
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156 " ldr r0, xVTORConst \n" /* Use the NVIC offset register to locate the stack. */
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157 " ldr r0, [r0] \n" /* Read the VTOR register which gives the address of vector table. */
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158 " ldr r0, [r0] \n" /* The first entry in vector table is stack pointer. */
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159 " msr msp, r0 \n" /* Set the MSP back to the start of the stack. */
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160 " cpsie i \n" /* Globally enable interrupts. */
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164 " svc %0 \n" /* System call to start the first task. */
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168 "xVTORConst: .word 0xe000ed08 \n"
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169 :: "i" ( portSVC_START_SCHEDULER ) : "memory"
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172 /*-----------------------------------------------------------*/
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174 uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
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178 " mrs r0, PRIMASK \n"
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184 #if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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185 /* To avoid compiler warnings. The return statement will never be reached,
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186 * but some compilers warn if it is not included, while others won't compile
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191 /*-----------------------------------------------------------*/
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193 void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
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197 " msr PRIMASK, r0 \n"
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202 #if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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203 /* Just to avoid compiler warning. ulMask is used from the asm code but
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204 * the compiler can't see that. Some compilers generate warnings without
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205 * the following line, while others generate warnings if the line is
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210 /*-----------------------------------------------------------*/
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212 void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
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216 " .syntax unified \n"
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218 " mrs r0, psp \n" /* Read PSP in r0. */
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219 #if( configENABLE_FPU == 1 )
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220 " tst lr, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
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222 " vstmdbeq r0!, {s16-s31} \n" /* Store the FPU registers which are not saved automatically. */
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223 #endif /* configENABLE_FPU */
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224 #if( configENABLE_MPU == 1 )
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225 " mrs r1, psplim \n" /* r1 = PSPLIM. */
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226 " mrs r2, control \n" /* r2 = CONTROL. */
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227 " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */
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228 " stmdb r0!, {r1-r11} \n" /* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */
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229 #else /* configENABLE_MPU */
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230 " mrs r2, psplim \n" /* r2 = PSPLIM. */
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231 " mov r3, lr \n" /* r3 = LR/EXC_RETURN. */
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232 " stmdb r0!, {r2-r11} \n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
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233 #endif /* configENABLE_MPU */
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235 " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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236 " ldr r1, [r2] \n" /* Read pxCurrentTCB. */
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237 " str r0, [r1] \n" /* Save the new top of stack in TCB. */
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240 " bl vTaskSwitchContext \n"
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243 " ldr r2, pxCurrentTCBConst \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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244 " ldr r1, [r2] \n" /* Read pxCurrentTCB. */
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245 " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
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247 #if( configENABLE_MPU == 1 )
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248 " dmb \n" /* Complete outstanding transfers before disabling MPU. */
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249 " ldr r2, xMPUCTRLConst \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
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250 " ldr r4, [r2] \n" /* Read the value of MPU_CTRL. */
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251 " bic r4, #1 \n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
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252 " str r4, [r2] \n" /* Disable MPU. */
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254 " adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
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255 " ldr r3, [r1] \n" /* r3 = *r1 i.e. r3 = MAIR0. */
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256 " ldr r2, xMAIR0Const \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
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257 " str r3, [r2] \n" /* Program MAIR0. */
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258 " ldr r2, xRNRConst \n" /* r2 = 0xe000ed98 [Location of RNR]. */
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259 " movs r3, #4 \n" /* r3 = 4. */
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260 " str r3, [r2] \n" /* Program RNR = 4. */
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261 " adds r1, #4 \n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
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262 " ldr r2, xRBARConst \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
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263 " ldmia r1!, {r4-r11} \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
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264 " stmia r2!, {r4-r11} \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
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266 " ldr r2, xMPUCTRLConst \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
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267 " ldr r4, [r2] \n" /* Read the value of MPU_CTRL. */
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268 " orr r4, #1 \n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
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269 " str r4, [r2] \n" /* Enable MPU. */
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270 " dsb \n" /* Force memory writes before continuing. */
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271 #endif /* configENABLE_MPU */
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273 #if( configENABLE_MPU == 1 )
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274 " ldmia r0!, {r1-r11} \n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */
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275 #else /* configENABLE_MPU */
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276 " ldmia r0!, {r2-r11} \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
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277 #endif /* configENABLE_MPU */
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279 #if( configENABLE_FPU == 1 )
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280 " tst r3, #0x10 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
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282 " vldmiaeq r0!, {s16-s31} \n" /* Restore the FPU registers which are not restored automatically. */
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283 #endif /* configENABLE_FPU */
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285 #if( configENABLE_MPU == 1 )
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286 " msr psplim, r1 \n" /* Restore the PSPLIM register value for the task. */
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287 " msr control, r2 \n" /* Restore the CONTROL register value for the task. */
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288 #else /* configENABLE_MPU */
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289 " msr psplim, r2 \n" /* Restore the PSPLIM register value for the task. */
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290 #endif /* configENABLE_MPU */
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291 " msr psp, r0 \n" /* Remember the new top of stack for the task. */
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295 "pxCurrentTCBConst: .word pxCurrentTCB \n"
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296 #if( configENABLE_MPU == 1 )
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297 "xMPUCTRLConst: .word 0xe000ed94 \n"
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298 "xMAIR0Const: .word 0xe000edc0 \n"
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299 "xRNRConst: .word 0xe000ed98 \n"
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300 "xRBARConst: .word 0xe000ed9c \n"
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301 #endif /* configENABLE_MPU */
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304 /*-----------------------------------------------------------*/
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306 void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
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312 " mrseq r0, msp \n"
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313 " mrsne r0, psp \n"
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314 " ldr r1, svchandler_address_const \n"
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318 "svchandler_address_const: .word vPortSVCHandler_C \n"
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321 /*-----------------------------------------------------------*/
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