git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s

   1 /*\r
   2  * FreeRTOS Kernel V10.2.1\r
   3  * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
   4  *\r
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
   6  * this software and associated documentation files (the "Software"), to deal in\r
   7  * the Software without restriction, including without limitation the rights to\r
   8  * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
   9  * the Software, and to permit persons to whom the Software is furnished to do so,\r
  10  * subject to the following conditions:\r
  11  *\r
  12  * The above copyright notice and this permission notice shall be included in all\r
  13  * copies or substantial portions of the Software.\r
  14  *\r
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
  17  * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
  18  * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
  19  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
  20  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
  21  *\r
  22  * http://www.FreeRTOS.org\r
  23  * http://aws.amazon.com/freertos\r
  24  *\r
  25  * 1 tab == 4 spaces!\r
  26  */\r
  27 /* Including FreeRTOSConfig.h here will cause build errors if the header file\r
  28 contains code not understood by the assembler - for example the 'extern' keyword.\r
  29 To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so\r
  30 the code is included in C files but excluded by the preprocessor in assembly\r
  31 files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */\r
  32 #include "FreeRTOSConfig.h"\r
  33 \r
  34         EXTERN pxCurrentTCB\r
  35         EXTERN xSecureContext\r
  36         EXTERN vTaskSwitchContext\r
  37         EXTERN vPortSVCHandler_C\r
  38         EXTERN SecureContext_SaveContext\r
  39         EXTERN SecureContext_LoadContext\r
  40 \r
  41         PUBLIC xIsPrivileged\r
  42         PUBLIC vResetPrivilege\r
  43         PUBLIC vPortAllocateSecureContext\r
  44         PUBLIC vRestoreContextOfFirstTask\r
  45         PUBLIC vRaisePrivilege\r
  46         PUBLIC vStartFirstTask\r
  47         PUBLIC ulSetInterruptMask\r
  48         PUBLIC vClearInterruptMask\r
  49         PUBLIC PendSV_Handler\r
  50         PUBLIC SVC_Handler\r
  51         PUBLIC vPortFreeSecureContext\r
  52 /*-----------------------------------------------------------*/\r
  53 \r
  54 /*---------------- Unprivileged Functions -------------------*/\r
  55 \r
  56 /*-----------------------------------------------------------*/\r
  57 \r
  58         SECTION .text:CODE:NOROOT(2)\r
  59         THUMB\r
  60 /*-----------------------------------------------------------*/\r
  61 \r
  62 xIsPrivileged:\r
  63         mrs r0, control                                                 /* r0 = CONTROL. */\r
  64         tst r0, #1                                                              /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\r
  65         ite ne\r
  66         movne r0, #0                                                    /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
  67         moveq r0, #1                                                    /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */\r
  68         bx lr                                                                   /* Return. */\r
  69 /*-----------------------------------------------------------*/\r
  70 \r
  71 vResetPrivilege:\r
  72         mrs r0, control                                                 /* r0 = CONTROL. */\r
  73         orr r0, r0, #1                                                  /* r0 = r0 | 1. */\r
  74         msr control, r0                                                 /* CONTROL = r0. */\r
  75         bx lr                                                                   /* Return to the caller. */\r
  76 /*-----------------------------------------------------------*/\r
  77 \r
  78 vPortAllocateSecureContext:\r
  79         svc 0                                                                   /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */\r
  80         bx lr                                                                   /* Return. */\r
  81 /*-----------------------------------------------------------*/\r
  82 \r
  83 /*----------------- Privileged Functions --------------------*/\r
  84 \r
  85 /*-----------------------------------------------------------*/\r
  86 \r
  87         SECTION privileged_functions:CODE:NOROOT(2)\r
  88         THUMB\r
  89 /*-----------------------------------------------------------*/\r
  90 \r
  91 vRestoreContextOfFirstTask:\r
  92         ldr  r2, =pxCurrentTCB                                  /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
  93         ldr  r3, [r2]                                                   /* Read pxCurrentTCB. */\r
  94         ldr  r0, [r3]                                                   /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
  95 \r
  96 #if ( configENABLE_MPU == 1 )\r
  97         dmb                                                                             /* Complete outstanding transfers before disabling MPU. */\r
  98         ldr r2, =0xe000ed94                                             /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
  99         ldr r4, [r2]                                                    /* Read the value of MPU_CTRL. */\r
 100         bic r4, r4, #1                                                  /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\r
 101         str r4, [r2]                                                    /* Disable MPU. */\r
 102 \r
 103         adds r3, #4                                                             /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
 104         ldr  r4, [r3]                                                   /* r4 = *r3 i.e. r4 = MAIR0. */\r
 105         ldr  r2, =0xe000edc0                                    /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
 106         str  r4, [r2]                                                   /* Program MAIR0. */\r
 107         ldr  r2, =0xe000ed98                                    /* r2 = 0xe000ed98 [Location of RNR]. */\r
 108         movs r4, #4                                                             /* r4 = 4. */\r
 109         str  r4, [r2]                                                   /* Program RNR = 4. */\r
 110         adds r3, #4                                                             /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\r
 111         ldr  r2, =0xe000ed9c                                    /* r2 = 0xe000ed9c [Location of RBAR]. */\r
 112         ldmia r3!, {r4-r11}                                             /* Read 4 set of RBAR/RLAR registers from TCB. */\r
 113         stmia r2!, {r4-r11}                                             /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
 114 \r
 115         ldr r2, =0xe000ed94                                             /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
 116         ldr r4, [r2]                                                    /* Read the value of MPU_CTRL. */\r
 117         orr r4, r4, #1                                                  /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\r
 118         str r4, [r2]                                                    /* Enable MPU. */\r
 119         dsb                                                                             /* Force memory writes before continuing. */\r
 120 #endif /* configENABLE_MPU */\r
 121 \r
 122 #if ( configENABLE_MPU == 1 )\r
 123         ldm  r0!, {r1-r4}                                               /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */\r
 124         ldr  r5, =xSecureContext\r
 125         str  r1, [r5]                                                   /* Set xSecureContext to this task's value for the same. */\r
 126         msr  psplim, r2                                                 /* Set this task's PSPLIM value. */\r
 127         msr  control, r3                                                /* Set this task's CONTROL value. */\r
 128         adds r0, #32                                                    /* Discard everything up to r0. */\r
 129         msr  psp, r0                                                    /* This is now the new top of stack to use in the task. */\r
 130         isb\r
 131         bx   r4                                                                 /* Finally, branch to EXC_RETURN. */\r
 132 #else /* configENABLE_MPU */\r
 133         ldm  r0!, {r1-r3}                                               /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */\r
 134         ldr  r4, =xSecureContext\r
 135         str  r1, [r4]                                                   /* Set xSecureContext to this task's value for the same. */\r
 136         msr  psplim, r2                                                 /* Set this task's PSPLIM value. */\r
 137         movs r1, #2                                                             /* r1 = 2. */\r
 138         msr  CONTROL, r1                                                /* Switch to use PSP in the thread mode. */\r
 139         adds r0, #32                                                    /* Discard everything up to r0. */\r
 140         msr  psp, r0                                                    /* This is now the new top of stack to use in the task. */\r
 141         isb\r
 142         bx   r3                                                                 /* Finally, branch to EXC_RETURN. */\r
 143 #endif /* configENABLE_MPU */\r
 144 /*-----------------------------------------------------------*/\r
 145 \r
 146 vRaisePrivilege:\r
 147         mrs  r0, control                                                /* Read the CONTROL register. */\r
 148         bic r0, r0, #1                                                  /* Clear the bit 0. */\r
 149         msr  control, r0                                                /* Write back the new CONTROL value. */\r
 150         bx lr                                                                   /* Return to the caller. */\r
 151 /*-----------------------------------------------------------*/\r
 152 \r
 153 vStartFirstTask:\r
 154         ldr r0, =0xe000ed08                                             /* Use the NVIC offset register to locate the stack. */\r
 155         ldr r0, [r0]                                                    /* Read the VTOR register which gives the address of vector table. */\r
 156         ldr r0, [r0]                                                    /* The first entry in vector table is stack pointer. */\r
 157         msr msp, r0                                                             /* Set the MSP back to the start of the stack. */\r
 158         cpsie i                                                                 /* Globally enable interrupts. */\r
 159         cpsie f\r
 160         dsb\r
 161         isb\r
 162         svc 2                                                                   /* System call to start the first task. portSVC_START_SCHEDULER = 2. */\r
 163 /*-----------------------------------------------------------*/\r
 164 \r
 165 ulSetInterruptMask:\r
 166         mrs r0, basepri                                                 /* r0 = basepri. Return original basepri value. */\r
 167         mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY\r
 168         msr basepri, r1                                                 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\r
 169         dsb\r
 170         isb\r
 171         bx lr                                                                   /* Return. */\r
 172 /*-----------------------------------------------------------*/\r
 173 \r
 174 vClearInterruptMask:\r
 175         msr basepri, r0                                                 /* basepri = ulMask. */\r
 176         dsb\r
 177         isb\r
 178         bx lr                                                                   /* Return. */\r
 179 /*-----------------------------------------------------------*/\r
 180 \r
 181 PendSV_Handler:\r
 182         mrs r1, psp                                                             /* Read PSP in r1. */\r
 183         ldr r2, =xSecureContext                                 /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
 184         ldr r0, [r2]                                                    /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */\r
 185 \r
 186         cbz r0, save_ns_context                                 /* No secure context to save. */\r
 187         push {r0-r2, r14}\r
 188         bl SecureContext_SaveContext\r
 189         pop {r0-r3}                                                             /* LR is now in r3. */\r
 190         mov lr, r3                                                              /* LR = r3. */\r
 191         lsls r2, r3, #25                                                /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
 192         bpl save_ns_context                                             /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
 193         ldr r3, =pxCurrentTCB                                   /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
 194         ldr r2, [r3]                                                    /* Read pxCurrentTCB. */\r
 195 #if ( configENABLE_MPU == 1 )\r
 196         subs r1, r1, #16                                                /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
 197         str r1, [r2]                                                    /* Save the new top of stack in TCB. */\r
 198         mrs r2, psplim                                                  /* r2 = PSPLIM. */\r
 199         mrs r3, control                                                 /* r3 = CONTROL. */\r
 200         mov r4, lr                                                              /* r4 = LR/EXC_RETURN. */\r
 201         stmia r1!, {r0, r2-r4}                                  /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
 202 #else /* configENABLE_MPU */\r
 203         subs r1, r1, #12                                                /* Make space for xSecureContext, PSPLIM and LR on the stack. */\r
 204         str r1, [r2]                                                    /* Save the new top of stack in TCB. */\r
 205         mrs r2, psplim                                                  /* r2 = PSPLIM. */\r
 206         mov r3, lr                                                              /* r3 = LR/EXC_RETURN. */\r
 207         stmia r1!, {r0, r2-r3}                                  /* Store xSecureContext, PSPLIM and LR on the stack. */\r
 208 #endif /* configENABLE_MPU */\r
 209         b select_next_task\r
 210 \r
 211         save_ns_context:\r
 212                 ldr r3, =pxCurrentTCB                           /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
 213                 ldr r2, [r3]                                            /* Read pxCurrentTCB. */\r
 214         #if ( configENABLE_FPU == 1 )\r
 215                 tst lr, #0x10                                           /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
 216                 it eq\r
 217                 vstmdbeq r1!, {s16-s31}                         /* Store the FPU registers which are not saved automatically. */\r
 218         #endif /* configENABLE_FPU */\r
 219         #if ( configENABLE_MPU == 1 )\r
 220                 subs r1, r1, #48                                        /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */\r
 221                 str r1, [r2]                                            /* Save the new top of stack in TCB. */\r
 222                 adds r1, r1, #16                                        /* r1 = r1 + 16. */\r
 223                 stm r1, {r4-r11}                                        /* Store the registers that are not saved automatically. */\r
 224                 mrs r2, psplim                                          /* r2 = PSPLIM. */\r
 225                 mrs r3, control                                         /* r3 = CONTROL. */\r
 226                 mov r4, lr                                                      /* r4 = LR/EXC_RETURN. */\r
 227                 subs r1, r1, #16                                        /* r1 = r1 - 16. */\r
 228                 stm r1, {r0, r2-r4}                                     /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
 229         #else /* configENABLE_MPU */\r
 230                 subs r1, r1, #44                                        /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */\r
 231                 str r1, [r2]                                            /* Save the new top of stack in TCB. */\r
 232                 adds r1, r1, #12                                        /* r1 = r1 + 12. */\r
 233                 stm r1, {r4-r11}                                        /* Store the registers that are not saved automatically. */\r
 234                 mrs r2, psplim                                          /* r2 = PSPLIM. */\r
 235                 mov r3, lr                                                      /* r3 = LR/EXC_RETURN. */\r
 236                 subs r1, r1, #12                                        /* r1 = r1 - 12. */\r
 237                 stmia r1!, {r0, r2-r3}                          /* Store xSecureContext, PSPLIM and LR on the stack. */\r
 238         #endif /* configENABLE_MPU */\r
 239 \r
 240         select_next_task:\r
 241                 mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY\r
 242                 msr basepri, r0                                         /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\r
 243                 dsb\r
 244                 isb\r
 245                 bl vTaskSwitchContext\r
 246                 mov r0, #0                                                      /* r0 = 0. */\r
 247                 msr basepri, r0                                         /* Enable interrupts. */\r
 248 \r
 249                 ldr r2, =pxCurrentTCB                           /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
 250                 ldr r3, [r2]                                            /* Read pxCurrentTCB. */\r
 251                 ldr r1, [r3]                                            /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */\r
 252 \r
 253         #if ( configENABLE_MPU == 1 )\r
 254                 dmb                                                                     /* Complete outstanding transfers before disabling MPU. */\r
 255                 ldr r2, =0xe000ed94                                     /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
 256                 ldr r4, [r2]                                            /* Read the value of MPU_CTRL. */\r
 257                 bic r4, r4, #1                                          /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\r
 258                 str r4, [r2]                                            /* Disable MPU. */\r
 259 \r
 260                 adds r3, #4                                                     /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
 261                 ldr r4, [r3]                                            /* r4 = *r3 i.e. r4 = MAIR0. */\r
 262                 ldr r2, =0xe000edc0                                     /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
 263                 str r4, [r2]                                            /* Program MAIR0. */\r
 264                 ldr r2, =0xe000ed98                                     /* r2 = 0xe000ed98 [Location of RNR]. */\r
 265                 movs r4, #4                                                     /* r4 = 4. */\r
 266                 str r4, [r2]                                            /* Program RNR = 4. */\r
 267                 adds r3, #4                                                     /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\r
 268                 ldr  r2, =0xe000ed9c                            /* r2 = 0xe000ed9c [Location of RBAR]. */\r
 269                 ldmia r3!, {r4-r11}                                     /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
 270                 stmia r2!, {r4-r11}                                     /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
 271 \r
 272                 ldr r2, =0xe000ed94                                     /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
 273                 ldr r4, [r2]                                            /* Read the value of MPU_CTRL. */\r
 274                 orr r4, r4, #1                                          /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\r
 275                 str r4, [r2]                                            /* Enable MPU. */\r
 276                 dsb                                                                     /* Force memory writes before continuing. */\r
 277         #endif /* configENABLE_MPU */\r
 278 \r
 279         #if ( configENABLE_MPU == 1 )\r
 280                 ldmia r1!, {r0, r2-r4}                          /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */\r
 281                 msr psplim, r2                                          /* Restore the PSPLIM register value for the task. */\r
 282                 msr control, r3                                         /* Restore the CONTROL register value for the task. */\r
 283                 mov lr, r4                                                      /* LR = r4. */\r
 284                 ldr r2, =xSecureContext                         /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
 285                 str r0, [r2]                                            /* Restore the task's xSecureContext. */\r
 286                 cbz r0, restore_ns_context                      /* If there is no secure context for the task, restore the non-secure context. */\r
 287                 push {r1,r4}\r
 288                 bl SecureContext_LoadContext            /* Restore the secure context. */\r
 289                 pop {r1,r4}\r
 290                 mov lr, r4                                                      /* LR = r4. */\r
 291                 lsls r2, r4, #25                                        /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
 292                 bpl restore_ns_context                          /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
 293                 msr psp, r1                                                     /* Remember the new top of stack for the task. */\r
 294                 bx lr\r
 295         #else /* configENABLE_MPU */\r
 296                 ldmia r1!, {r0, r2-r3}                          /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */\r
 297                 msr psplim, r2                                          /* Restore the PSPLIM register value for the task. */\r
 298                 mov lr, r3                                                      /* LR = r3. */\r
 299                 ldr r2, =xSecureContext                         /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
 300                 str r0, [r2]                                            /* Restore the task's xSecureContext. */\r
 301                 cbz r0, restore_ns_context                      /* If there is no secure context for the task, restore the non-secure context. */\r
 302                 push {r1,r3}\r
 303                 bl SecureContext_LoadContext            /* Restore the secure context. */\r
 304                 pop {r1,r3}\r
 305                 mov lr, r3                                                      /* LR = r3. */\r
 306                 lsls r2, r3, #25                                        /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
 307                 bpl restore_ns_context                          /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
 308                 msr psp, r1                                                     /* Remember the new top of stack for the task. */\r
 309                 bx lr\r
 310         #endif /* configENABLE_MPU */\r
 311 \r
 312         restore_ns_context:\r
 313                 ldmia r1!, {r4-r11}                                     /* Restore the registers that are not automatically restored. */\r
 314         #if ( configENABLE_FPU == 1 )\r
 315                 tst lr, #0x10                                           /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
 316                 it eq\r
 317                 vldmiaeq r1!, {s16-s31}                         /* Restore the FPU registers which are not restored automatically. */\r
 318         #endif /* configENABLE_FPU */\r
 319                 msr psp, r1                                                     /* Remember the new top of stack for the task. */\r
 320                 bx lr\r
 321 /*-----------------------------------------------------------*/\r
 322 \r
 323 SVC_Handler:\r
 324         tst lr, #4\r
 325         ite eq\r
 326         mrseq r0, msp\r
 327         mrsne r0, psp\r
 328         b vPortSVCHandler_C\r
 329 /*-----------------------------------------------------------*/\r
 330 \r
 331 vPortFreeSecureContext:\r
 332         /* r0 = uint32_t *pulTCB. */\r
 333         ldr r1, [r0]                                                    /* The first item in the TCB is the top of the stack. */\r
 334         ldr r0, [r1]                                                    /* The first item on the stack is the task's xSecureContext. */\r
 335         cmp r0, #0                                                              /* Raise svc if task's xSecureContext is not NULL. */\r
 336         it ne\r
 337         svcne 1                                                                 /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */\r
 338         bx lr                                                                   /* Return. */\r
 339 /*-----------------------------------------------------------*/\r
 340 \r
 341         END\r