2 * FreeRTOS Kernel V10.3.0
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3 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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29 /*-----------------------------------------------------------
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30 * Implementation of functions defined in portable.h for the Atmel AT91R40008
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33 * Components that can be compiled to either ARM or THUMB mode are
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34 * contained in this file. The ISR routines, which can only be compiled
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35 * to ARM mode are contained in portISR.c.
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36 *----------------------------------------------------------*/
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38 /* Standard includes. */
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41 /* Scheduler includes. */
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42 #include "FreeRTOS.h"
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45 /* Hardware specific definitions. */
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46 #include "AT91R40008.h"
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51 /* Constants required to setup the task context. */
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52 #define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
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53 #define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
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54 #define portINSTRUCTION_SIZE ( ( StackType_t ) 4 )
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55 #define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 )
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56 #define portTICK_PRIORITY_6 ( 6 )
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57 /*-----------------------------------------------------------*/
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59 /* Setup the timer to generate the tick interrupts. */
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60 static void prvSetupTimerInterrupt( void );
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63 * The scheduler can only be started from ARM mode, so
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64 * vPortISRStartFirstSTask() is defined in portISR.c.
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66 extern void vPortISRStartFirstTask( void );
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68 /*-----------------------------------------------------------*/
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71 * Initialise the stack of a task to look exactly as if a call to
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72 * portSAVE_CONTEXT had been called.
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74 * See header file for description.
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76 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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78 StackType_t *pxOriginalTOS;
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80 pxOriginalTOS = pxTopOfStack;
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82 /* To ensure asserts in tasks.c don't fail, although in this case the assert
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83 is not really required. */
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86 /* Setup the initial stack of the task. The stack is set exactly as
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87 expected by the portRESTORE_CONTEXT() macro. */
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89 /* First on the stack is the return address - which in this case is the
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90 start of the task. The offset is added to make the return address appear
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91 as it would within an IRQ ISR. */
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92 *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
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95 *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */
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97 *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
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99 *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
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101 *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
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103 *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
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105 *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
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107 *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
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109 *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
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111 *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
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113 *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
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115 *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
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117 *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
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119 *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
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121 *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
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124 /* When the task starts is will expect to find the function parameter in
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126 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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129 /* The last thing onto the stack is the status register, which is set for
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130 system mode, with interrupts enabled. */
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131 *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
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133 #ifdef THUMB_INTERWORK
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135 /* We want the task to start in thumb mode. */
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136 *pxTopOfStack |= portTHUMB_MODE_BIT;
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142 /* Some optimisation levels use the stack differently to others. This
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143 means the interrupt flags cannot always be stored on the stack and will
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144 instead be stored in a variable, which is then saved as part of the
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146 *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
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148 return pxTopOfStack;
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150 /*-----------------------------------------------------------*/
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152 BaseType_t xPortStartScheduler( void )
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154 /* Start the timer that generates the tick ISR. Interrupts are disabled
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156 prvSetupTimerInterrupt();
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158 /* Start the first task. */
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159 vPortISRStartFirstTask();
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161 /* Should not get here! */
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164 /*-----------------------------------------------------------*/
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166 void vPortEndScheduler( void )
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168 /* It is unlikely that the ARM port will require this function as there
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169 is nothing to return to. */
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171 /*-----------------------------------------------------------*/
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174 * Setup the tick timer to generate the tick interrupts at the required frequency.
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176 static void prvSetupTimerInterrupt( void )
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178 volatile uint32_t ulDummy;
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180 /* Enable clock to the tick timer... */
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181 AT91C_BASE_PS->PS_PCER = portTIMER_CLK_ENABLE_BIT;
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183 /* Stop the tick timer... */
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184 portTIMER_REG_BASE_PTR->TC_CCR = TC_CLKDIS;
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186 /* Start with tick timer interrupts disabled... */
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187 portTIMER_REG_BASE_PTR->TC_IDR = 0xFFFFFFFF;
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189 /* Clear any pending tick timer interrupts... */
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190 ulDummy = portTIMER_REG_BASE_PTR->TC_SR;
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192 /* Store interrupt handler function address in tick timer vector register...
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193 The ISR installed depends on whether the preemptive or cooperative
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194 scheduler is being used. */
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195 #if configUSE_PREEMPTION == 1
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197 extern void ( vPreemptiveTick )( void );
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198 AT91C_BASE_AIC->AIC_SVR[portTIMER_AIC_CHANNEL] = ( uint32_t ) vPreemptiveTick;
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200 #else // else use cooperative scheduler
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202 extern void ( vNonPreemptiveTick )( void );
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203 AT91C_BASE_AIC->AIC_SVR[portTIMER_AIC_CHANNEL] = ( uint32_t ) vNonPreemptiveTick;
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207 /* Tick timer interrupt level-sensitive, priority 6... */
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208 AT91C_BASE_AIC->AIC_SMR[ portTIMER_AIC_CHANNEL ] = AIC_SRCTYPE_INT_LEVEL_SENSITIVE | portTICK_PRIORITY_6;
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210 /* Enable the tick timer interrupt...
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212 First at timer level */
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213 portTIMER_REG_BASE_PTR->TC_IER = TC_CPCS;
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215 /* Then at the AIC level. */
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216 AT91C_BASE_AIC->AIC_IECR = (1 << portTIMER_AIC_CHANNEL);
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218 /* Calculate timer compare value to achieve the desired tick rate... */
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219 if( (configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 2) ) <= 0xFFFF )
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221 /* The tick rate is fast enough for us to use the faster timer input
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222 clock (main clock / 2). */
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223 portTIMER_REG_BASE_PTR->TC_CMR = TC_WAVE | TC_CLKS_MCK2 | TC_BURST_NONE | TC_CPCTRG;
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224 portTIMER_REG_BASE_PTR->TC_RC = configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 2);
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228 /* We must use a slower timer input clock (main clock / 8) because the
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229 tick rate is too slow for the faster input clock. */
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230 portTIMER_REG_BASE_PTR->TC_CMR = TC_WAVE | TC_CLKS_MCK8 | TC_BURST_NONE | TC_CPCTRG;
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231 portTIMER_REG_BASE_PTR->TC_RC = configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 8);
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234 /* Start tick timer... */
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235 portTIMER_REG_BASE_PTR->TC_CCR = TC_SWTRG | TC_CLKEN;
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237 /*-----------------------------------------------------------*/
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