2 FreeRTOS V7.3.0 - Copyright (C) 2012 Real Time Engineers Ltd.
\r
4 FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
\r
5 http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
\r
7 ***************************************************************************
\r
9 * FreeRTOS tutorial books are available in pdf and paperback. *
\r
10 * Complete, revised, and edited pdf reference manuals are also *
\r
13 * Purchasing FreeRTOS documentation will not only help you, by *
\r
14 * ensuring you get running as quickly as possible and with an *
\r
15 * in-depth knowledge of how to use FreeRTOS, it will also help *
\r
16 * the FreeRTOS project to continue with its mission of providing *
\r
17 * professional grade, cross platform, de facto standard solutions *
\r
18 * for microcontrollers - completely free of charge! *
\r
20 * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
\r
22 * Thank you for using FreeRTOS, and thank you for your support! *
\r
24 ***************************************************************************
\r
27 This file is part of the FreeRTOS distribution.
\r
29 FreeRTOS is free software; you can redistribute it and/or modify it under
\r
30 the terms of the GNU General Public License (version 2) as published by the
\r
31 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
\r
32 >>>NOTE<<< The modification to the GPL is included to allow you to
\r
33 distribute a combined work that includes FreeRTOS without being obliged to
\r
34 provide the source code for proprietary components outside of the FreeRTOS
\r
35 kernel. FreeRTOS is distributed in the hope that it will be useful, but
\r
36 WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
\r
37 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
\r
38 more details. You should have received a copy of the GNU General Public
\r
39 License and the FreeRTOS license exception along with FreeRTOS; if not it
\r
40 can be viewed here: http://www.freertos.org/a00114.html and also obtained
\r
41 by writing to Richard Barry, contact details for whom are available on the
\r
46 ***************************************************************************
\r
48 * Having a problem? Start by reading the FAQ "My application does *
\r
49 * not run, what could be wrong?" *
\r
51 * http://www.FreeRTOS.org/FAQHelp.html *
\r
53 ***************************************************************************
\r
56 http://www.FreeRTOS.org - Documentation, training, latest versions, license
\r
57 and contact details.
\r
59 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
\r
60 including FreeRTOS+Trace - an indispensable productivity tool.
\r
62 Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
\r
63 the code with commercial support, indemnification, and middleware, under
\r
64 the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
\r
65 provide a safety engineered and independently SIL3 certified version under
\r
66 the SafeRTOS brand: http://www.SafeRTOS.com.
\r
70 /*-----------------------------------------------------------
\r
71 * Components that can be compiled to either ARM or THUMB mode are
\r
72 * contained in port.c The ISR routines, which can only be compiled
\r
73 * to ARM mode, are contained in this file.
\r
74 *----------------------------------------------------------*/
\r
79 + The assembler statements are now included in a single asm block rather
\r
80 than each line having its own asm block.
\r
84 /* Scheduler includes. */
\r
85 #include "FreeRTOS.h"
\r
88 /* Constants required to handle interrupts. */
\r
89 #define portCLEAR_AIC_INTERRUPT ( ( unsigned long ) 0 )
\r
91 /* Constants required to handle critical sections. */
\r
92 #define portNO_CRITICAL_NESTING ( ( unsigned long ) 0 )
\r
93 volatile unsigned long ulCriticalNesting = 9999UL;
\r
95 /*-----------------------------------------------------------*/
\r
97 /* ISR to handle manual context switches (from a call to taskYIELD()). */
\r
98 void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));
\r
101 * The scheduler can only be started from ARM mode, hence the inclusion of this
\r
104 void vPortISRStartFirstTask( void );
\r
105 /*-----------------------------------------------------------*/
\r
107 void vPortISRStartFirstTask( void )
\r
109 /* Simply start the scheduler. This is included here as it can only be
\r
110 called from ARM mode. */
\r
111 portRESTORE_CONTEXT();
\r
113 /*-----------------------------------------------------------*/
\r
116 * Called by portYIELD() or taskYIELD() to manually force a context switch.
\r
118 * When a context switch is performed from the task level the saved task
\r
119 * context is made to look as if it occurred from within the tick ISR. This
\r
120 * way the same restore context function can be used when restoring the context
\r
121 * saved from the ISR or that saved from a call to vPortYieldProcessor.
\r
123 void vPortYieldProcessor( void )
\r
125 /* Within an IRQ ISR the link register has an offset from the true return
\r
126 address, but an SWI ISR does not. Add the offset manually so the same
\r
127 ISR return code can be used in both cases. */
\r
128 asm volatile ( "ADD LR, LR, #4" );
\r
130 /* Perform the context switch. First save the context of the current task. */
\r
131 portSAVE_CONTEXT();
\r
133 /* Find the highest priority task that is ready to run. */
\r
134 vTaskSwitchContext();
\r
136 /* Restore the context of the new task. */
\r
137 portRESTORE_CONTEXT();
\r
139 /*-----------------------------------------------------------*/
\r
142 * The ISR used for the scheduler tick depends on whether the cooperative or
\r
143 * the preemptive scheduler is being used.
\r
146 #if configUSE_PREEMPTION == 0
\r
148 /* The cooperative scheduler requires a normal IRQ service routine to
\r
149 simply increment the system tick. */
\r
150 void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ")));
\r
151 void vNonPreemptiveTick( void )
\r
153 static volatile unsigned long ulDummy;
\r
155 /* Clear tick timer interrupt indication. */
\r
156 ulDummy = portTIMER_REG_BASE_PTR->TC_SR;
\r
158 vTaskIncrementTick();
\r
160 /* Acknowledge the interrupt at AIC level... */
\r
161 AT91C_BASE_AIC->AIC_EOICR = portCLEAR_AIC_INTERRUPT;
\r
164 #else /* else preemption is turned on */
\r
166 /* The preemptive scheduler is defined as "naked" as the full context is
\r
167 saved on entry as part of the context switch. */
\r
168 void vPreemptiveTick( void ) __attribute__((naked));
\r
169 void vPreemptiveTick( void )
\r
171 /* Save the context of the interrupted task. */
\r
172 portSAVE_CONTEXT();
\r
174 /* WARNING - Do not use local (stack) variables here. Use globals
\r
176 static volatile unsigned long ulDummy;
\r
178 /* Clear tick timer interrupt indication. */
\r
179 ulDummy = portTIMER_REG_BASE_PTR->TC_SR;
\r
181 /* Increment the RTOS tick count, then look for the highest priority
\r
182 task that is ready to run. */
\r
183 vTaskIncrementTick();
\r
184 vTaskSwitchContext();
\r
186 /* Acknowledge the interrupt at AIC level... */
\r
187 AT91C_BASE_AIC->AIC_EOICR = portCLEAR_AIC_INTERRUPT;
\r
189 /* Restore the context of the new task. */
\r
190 portRESTORE_CONTEXT();
\r
194 /*-----------------------------------------------------------*/
\r
197 * The interrupt management utilities can only be called from ARM mode. When
\r
198 * THUMB_INTERWORK is defined the utilities are defined as functions here to
\r
199 * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then
\r
200 * the utilities are defined as macros in portmacro.h - as per other ports.
\r
202 #ifdef THUMB_INTERWORK
\r
204 void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
\r
205 void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
\r
207 void vPortDisableInterruptsFromThumb( void )
\r
210 "STMDB SP!, {R0} \n\t" /* Push R0. */
\r
211 "MRS R0, CPSR \n\t" /* Get CPSR. */
\r
212 "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
\r
213 "MSR CPSR, R0 \n\t" /* Write back modified value. */
\r
214 "LDMIA SP!, {R0} \n\t" /* Pop R0. */
\r
215 "BX R14" ); /* Return back to thumb. */
\r
218 void vPortEnableInterruptsFromThumb( void )
\r
221 "STMDB SP!, {R0} \n\t" /* Push R0. */
\r
222 "MRS R0, CPSR \n\t" /* Get CPSR. */
\r
223 "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
\r
224 "MSR CPSR, R0 \n\t" /* Write back modified value. */
\r
225 "LDMIA SP!, {R0} \n\t" /* Pop R0. */
\r
226 "BX R14" ); /* Return back to thumb. */
\r
229 #endif /* THUMB_INTERWORK */
\r
231 /* The code generated by the GCC compiler uses the stack in different ways at
\r
232 different optimisation levels. The interrupt flags can therefore not always
\r
233 be saved to the stack. Instead the critical section nesting level is stored
\r
234 in a variable, which is then saved as part of the stack context. */
\r
235 void vPortEnterCritical( void )
\r
237 /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
\r
239 "STMDB SP!, {R0} \n\t" /* Push R0. */
\r
240 "MRS R0, CPSR \n\t" /* Get CPSR. */
\r
241 "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
\r
242 "MSR CPSR, R0 \n\t" /* Write back modified value. */
\r
243 "LDMIA SP!, {R0}" ); /* Pop R0. */
\r
245 /* Now interrupts are disabled ulCriticalNesting can be accessed
\r
246 directly. Increment ulCriticalNesting to keep a count of how many times
\r
247 portENTER_CRITICAL() has been called. */
\r
248 ulCriticalNesting++;
\r
251 void vPortExitCritical( void )
\r
253 if( ulCriticalNesting > portNO_CRITICAL_NESTING )
\r
255 /* Decrement the nesting count as we are leaving a critical section. */
\r
256 ulCriticalNesting--;
\r
258 /* If the nesting level has reached zero then interrupts should be
\r
260 if( ulCriticalNesting == portNO_CRITICAL_NESTING )
\r
262 /* Enable interrupts as per portEXIT_CRITICAL(). */
\r
264 "STMDB SP!, {R0} \n\t" /* Push R0. */
\r
265 "MRS R0, CPSR \n\t" /* Get CPSR. */
\r
266 "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
\r
267 "MSR CPSR, R0 \n\t" /* Write back modified value. */
\r
268 "LDMIA SP!, {R0}" ); /* Pop R0. */
\r