2 * FreeRTOS Kernel V10.3.0
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3 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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31 + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.
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35 + Removed the use of the %0 parameter within the assembler macros and
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36 replaced them with hard coded registers. This will ensure the
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37 assembler does not select the link register as the temp register as
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38 was occasionally happening previously.
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40 + The assembler statements are now included in a single asm block rather
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41 than each line having its own asm block.
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45 + Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros
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46 and replaced them with portYIELD_FROM_ISR() macro. Application code
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47 should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()
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48 macros as per the V4.5.1 demo code.
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58 /*-----------------------------------------------------------
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59 * Port specific definitions.
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61 * The settings in this file configure FreeRTOS correctly for the
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62 * given hardware and compiler.
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64 * These settings should not be altered.
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65 *-----------------------------------------------------------
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68 /* Type definitions. */
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69 #define portCHAR char
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70 #define portFLOAT float
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71 #define portDOUBLE double
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72 #define portLONG long
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73 #define portSHORT short
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74 #define portSTACK_TYPE uint32_t
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75 #define portBASE_TYPE long
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77 typedef portSTACK_TYPE StackType_t;
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78 typedef long BaseType_t;
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79 typedef unsigned long UBaseType_t;
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81 #if( configUSE_16_BIT_TICKS == 1 )
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82 typedef uint16_t TickType_t;
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83 #define portMAX_DELAY ( TickType_t ) 0xffff
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85 typedef uint32_t TickType_t;
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86 #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
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88 /*-----------------------------------------------------------*/
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90 /* Hardware specifics. */
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91 #define portSTACK_GROWTH ( -1 )
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92 #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
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93 #define portBYTE_ALIGNMENT 8
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94 #define portYIELD() asm volatile ( "SWI 0" )
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95 #define portNOP() asm volatile ( "NOP" )
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98 * These define the timer to use for generating the tick interrupt.
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99 * They are put in this file so they can be shared between "port.c"
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102 #define portTIMER_REG_BASE_PTR AT91C_BASE_TC0
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103 #define portTIMER_CLK_ENABLE_BIT AT91C_PS_TC0
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104 #define portTIMER_AIC_CHANNEL ( ( uint32_t ) 4 )
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105 /*-----------------------------------------------------------*/
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107 /* Task utilities. */
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110 * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR
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111 * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but
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112 * are included here for efficiency. An attempt to call one from
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113 * THUMB mode code will result in a compile time error.
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116 #define portRESTORE_CONTEXT() \
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118 extern volatile void * volatile pxCurrentTCB; \
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119 extern volatile uint32_t ulCriticalNesting; \
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121 /* Set the LR to the task stack. */ \
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123 "LDR R0, =pxCurrentTCB \n\t" \
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124 "LDR R0, [R0] \n\t" \
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125 "LDR LR, [R0] \n\t" \
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127 /* The critical nesting depth is the first item on the stack. */ \
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128 /* Load it into the ulCriticalNesting variable. */ \
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129 "LDR R0, =ulCriticalNesting \n\t" \
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130 "LDMFD LR!, {R1} \n\t" \
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131 "STR R1, [R0] \n\t" \
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133 /* Get the SPSR from the stack. */ \
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134 "LDMFD LR!, {R0} \n\t" \
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135 "MSR SPSR, R0 \n\t" \
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137 /* Restore all system mode registers for the task. */ \
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138 "LDMFD LR, {R0-R14}^ \n\t" \
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141 /* Restore the return address. */ \
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142 "LDR LR, [LR, #+60] \n\t" \
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144 /* And return - correcting the offset in the LR to obtain the */ \
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145 /* correct address. */ \
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146 "SUBS PC, LR, #4 \n\t" \
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148 ( void ) ulCriticalNesting; \
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149 ( void ) pxCurrentTCB; \
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151 /*-----------------------------------------------------------*/
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153 #define portSAVE_CONTEXT() \
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155 extern volatile void * volatile pxCurrentTCB; \
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156 extern volatile uint32_t ulCriticalNesting; \
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158 /* Push R0 as we are going to use the register. */ \
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160 "STMDB SP!, {R0} \n\t" \
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162 /* Set R0 to point to the task stack pointer. */ \
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163 "STMDB SP,{SP}^ \n\t" \
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165 "SUB SP, SP, #4 \n\t" \
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166 "LDMIA SP!,{R0} \n\t" \
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168 /* Push the return address onto the stack. */ \
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169 "STMDB R0!, {LR} \n\t" \
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171 /* Now we have saved LR we can use it instead of R0. */ \
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172 "MOV LR, R0 \n\t" \
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174 /* Pop R0 so we can save it onto the system mode stack. */ \
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175 "LDMIA SP!, {R0} \n\t" \
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177 /* Push all the system mode registers onto the task stack. */ \
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178 "STMDB LR,{R0-LR}^ \n\t" \
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180 "SUB LR, LR, #60 \n\t" \
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182 /* Push the SPSR onto the task stack. */ \
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183 "MRS R0, SPSR \n\t" \
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184 "STMDB LR!, {R0} \n\t" \
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186 "LDR R0, =ulCriticalNesting \n\t" \
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187 "LDR R0, [R0] \n\t" \
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188 "STMDB LR!, {R0} \n\t" \
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190 /* Store the new top of stack for the task. */ \
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191 "LDR R0, =pxCurrentTCB \n\t" \
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192 "LDR R0, [R0] \n\t" \
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193 "STR LR, [R0] \n\t" \
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195 ( void ) ulCriticalNesting; \
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196 ( void ) pxCurrentTCB; \
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199 #define portYIELD_FROM_ISR() vTaskSwitchContext()
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201 /* Critical section handling. */
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204 * The interrupt management utilities can only be called from ARM mode. When
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205 * THUMB_INTERWORK is defined the utilities are defined as functions in
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206 * portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not
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207 * defined then the utilities are defined as macros here - as per other ports.
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210 #ifdef THUMB_INTERWORK
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212 extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
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213 extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
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215 #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb()
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216 #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb()
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220 #define portDISABLE_INTERRUPTS() \
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222 "STMDB SP!, {R0} \n\t" /* Push R0. */ \
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223 "MRS R0, CPSR \n\t" /* Get CPSR. */ \
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224 "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \
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225 "MSR CPSR, R0 \n\t" /* Write back modified value. */ \
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226 "LDMIA SP!, {R0} " ) /* Pop R0. */
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228 #define portENABLE_INTERRUPTS() \
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230 "STMDB SP!, {R0} \n\t" /* Push R0. */ \
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231 "MRS R0, CPSR \n\t" /* Get CPSR. */ \
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232 "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \
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233 "MSR CPSR, R0 \n\t" /* Write back modified value. */ \
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234 "LDMIA SP!, {R0} " ) /* Pop R0. */
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236 #endif /* THUMB_INTERWORK */
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238 extern void vPortEnterCritical( void );
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239 extern void vPortExitCritical( void );
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241 #define portENTER_CRITICAL() vPortEnterCritical();
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242 #define portEXIT_CRITICAL() vPortExitCritical();
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244 /*-----------------------------------------------------------*/
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246 /* Task function macros as described on the FreeRTOS.org WEB site. */
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247 #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
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248 #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
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254 #endif /* PORTMACRO_H */
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projects / freertos / blob