2 FreeRTOS V8.1.2 - Copyright (C) 2014 Real Time Engineers Ltd.
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5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 ***************************************************************************
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9 * FreeRTOS provides completely free yet professionally developed, *
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10 * robust, strictly quality controlled, supported, and cross *
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11 * platform software that has become a de facto standard. *
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13 * Help yourself get started quickly and support the FreeRTOS *
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14 * project by purchasing a FreeRTOS tutorial book, reference *
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15 * manual, or both from: http://www.FreeRTOS.org/Documentation *
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19 ***************************************************************************
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21 This file is part of the FreeRTOS distribution.
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23 FreeRTOS is free software; you can redistribute it and/or modify it under
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24 the terms of the GNU General Public License (version 2) as published by the
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25 Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
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27 >>! NOTE: The modification to the GPL is included to allow you to !<<
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28 >>! distribute a combined work that includes FreeRTOS without being !<<
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29 >>! obliged to provide the source code for proprietary components !<<
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30 >>! outside of the FreeRTOS kernel. !<<
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32 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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33 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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34 FOR A PARTICULAR PURPOSE. Full license text is available from the following
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35 link: http://www.freertos.org/a00114.html
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39 ***************************************************************************
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41 * Having a problem? Start by reading the FAQ "My application does *
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42 * not run, what could be wrong?" *
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44 * http://www.FreeRTOS.org/FAQHelp.html *
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46 ***************************************************************************
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48 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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49 license and Real Time Engineers Ltd. contact details.
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51 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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52 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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53 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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55 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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56 Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
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57 licenses offer ticketed support, indemnification and middleware.
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59 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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60 engineered and independently SIL3 certified version for use in safety and
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61 mission critical applications that require provable dependability.
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69 + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.
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73 + Removed the use of the %0 parameter within the assembler macros and
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74 replaced them with hard coded registers. This will ensure the
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75 assembler does not select the link register as the temp register as
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76 was occasionally happening previously.
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78 + The assembler statements are now included in a single asm block rather
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79 than each line having its own asm block.
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83 + Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros
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84 and replaced them with portYIELD_FROM_ISR() macro. Application code
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85 should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()
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86 macros as per the V4.5.1 demo code.
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96 /*-----------------------------------------------------------
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97 * Port specific definitions.
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99 * The settings in this file configure FreeRTOS correctly for the
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100 * given hardware and compiler.
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102 * These settings should not be altered.
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103 *-----------------------------------------------------------
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106 /* Type definitions. */
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107 #define portCHAR char
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108 #define portFLOAT float
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109 #define portDOUBLE double
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110 #define portLONG long
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111 #define portSHORT short
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112 #define portSTACK_TYPE uint32_t
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113 #define portBASE_TYPE long
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115 typedef portSTACK_TYPE StackType_t;
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116 typedef long BaseType_t;
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117 typedef unsigned long UBaseType_t;
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119 #if( configUSE_16_BIT_TICKS == 1 )
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120 typedef uint16_t TickType_t;
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121 #define portMAX_DELAY ( TickType_t ) 0xffff
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123 typedef uint32_t TickType_t;
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124 #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
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126 /*-----------------------------------------------------------*/
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128 /* Hardware specifics. */
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129 #define portSTACK_GROWTH ( -1 )
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130 #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
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131 #define portBYTE_ALIGNMENT 8
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132 #define portYIELD() asm volatile ( "SWI 0" )
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133 #define portNOP() asm volatile ( "NOP" )
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136 * These define the timer to use for generating the tick interrupt.
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137 * They are put in this file so they can be shared between "port.c"
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140 #define portTIMER_REG_BASE_PTR AT91C_BASE_TC0
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141 #define portTIMER_CLK_ENABLE_BIT AT91C_PS_TC0
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142 #define portTIMER_AIC_CHANNEL ( ( uint32_t ) 4 )
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143 /*-----------------------------------------------------------*/
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145 /* Task utilities. */
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148 * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR
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149 * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but
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150 * are included here for efficiency. An attempt to call one from
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151 * THUMB mode code will result in a compile time error.
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154 #define portRESTORE_CONTEXT() \
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156 extern volatile void * volatile pxCurrentTCB; \
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157 extern volatile uint32_t ulCriticalNesting; \
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159 /* Set the LR to the task stack. */ \
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161 "LDR R0, =pxCurrentTCB \n\t" \
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162 "LDR R0, [R0] \n\t" \
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163 "LDR LR, [R0] \n\t" \
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165 /* The critical nesting depth is the first item on the stack. */ \
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166 /* Load it into the ulCriticalNesting variable. */ \
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167 "LDR R0, =ulCriticalNesting \n\t" \
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168 "LDMFD LR!, {R1} \n\t" \
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169 "STR R1, [R0] \n\t" \
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171 /* Get the SPSR from the stack. */ \
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172 "LDMFD LR!, {R0} \n\t" \
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173 "MSR SPSR, R0 \n\t" \
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175 /* Restore all system mode registers for the task. */ \
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176 "LDMFD LR, {R0-R14}^ \n\t" \
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179 /* Restore the return address. */ \
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180 "LDR LR, [LR, #+60] \n\t" \
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182 /* And return - correcting the offset in the LR to obtain the */ \
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183 /* correct address. */ \
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184 "SUBS PC, LR, #4 \n\t" \
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186 ( void ) ulCriticalNesting; \
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187 ( void ) pxCurrentTCB; \
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189 /*-----------------------------------------------------------*/
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191 #define portSAVE_CONTEXT() \
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193 extern volatile void * volatile pxCurrentTCB; \
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194 extern volatile uint32_t ulCriticalNesting; \
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196 /* Push R0 as we are going to use the register. */ \
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198 "STMDB SP!, {R0} \n\t" \
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200 /* Set R0 to point to the task stack pointer. */ \
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201 "STMDB SP,{SP}^ \n\t" \
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203 "SUB SP, SP, #4 \n\t" \
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204 "LDMIA SP!,{R0} \n\t" \
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206 /* Push the return address onto the stack. */ \
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207 "STMDB R0!, {LR} \n\t" \
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209 /* Now we have saved LR we can use it instead of R0. */ \
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210 "MOV LR, R0 \n\t" \
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212 /* Pop R0 so we can save it onto the system mode stack. */ \
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213 "LDMIA SP!, {R0} \n\t" \
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215 /* Push all the system mode registers onto the task stack. */ \
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216 "STMDB LR,{R0-LR}^ \n\t" \
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218 "SUB LR, LR, #60 \n\t" \
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220 /* Push the SPSR onto the task stack. */ \
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221 "MRS R0, SPSR \n\t" \
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222 "STMDB LR!, {R0} \n\t" \
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224 "LDR R0, =ulCriticalNesting \n\t" \
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225 "LDR R0, [R0] \n\t" \
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226 "STMDB LR!, {R0} \n\t" \
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228 /* Store the new top of stack for the task. */ \
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229 "LDR R0, =pxCurrentTCB \n\t" \
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230 "LDR R0, [R0] \n\t" \
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231 "STR LR, [R0] \n\t" \
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233 ( void ) ulCriticalNesting; \
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234 ( void ) pxCurrentTCB; \
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237 #define portYIELD_FROM_ISR() vTaskSwitchContext()
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239 /* Critical section handling. */
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242 * The interrupt management utilities can only be called from ARM mode. When
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243 * THUMB_INTERWORK is defined the utilities are defined as functions in
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244 * portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not
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245 * defined then the utilities are defined as macros here - as per other ports.
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248 #ifdef THUMB_INTERWORK
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250 extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
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251 extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
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253 #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb()
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254 #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb()
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258 #define portDISABLE_INTERRUPTS() \
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260 "STMDB SP!, {R0} \n\t" /* Push R0. */ \
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261 "MRS R0, CPSR \n\t" /* Get CPSR. */ \
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262 "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \
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263 "MSR CPSR, R0 \n\t" /* Write back modified value. */ \
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264 "LDMIA SP!, {R0} " ) /* Pop R0. */
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266 #define portENABLE_INTERRUPTS() \
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268 "STMDB SP!, {R0} \n\t" /* Push R0. */ \
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269 "MRS R0, CPSR \n\t" /* Get CPSR. */ \
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270 "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \
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271 "MSR CPSR, R0 \n\t" /* Write back modified value. */ \
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272 "LDMIA SP!, {R0} " ) /* Pop R0. */
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274 #endif /* THUMB_INTERWORK */
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276 extern void vPortEnterCritical( void );
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277 extern void vPortExitCritical( void );
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279 #define portENTER_CRITICAL() vPortEnterCritical();
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280 #define portEXIT_CRITICAL() vPortExitCritical();
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282 /*-----------------------------------------------------------*/
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284 /* Task function macros as described on the FreeRTOS.org WEB site. */
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285 #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
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286 #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
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292 #endif /* PORTMACRO_H */
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projects / freertos / blob