2 * FreeRTOS Kernel V10.0.1
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3 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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29 /*-----------------------------------------------------------
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30 * Components that can be compiled to either ARM or THUMB mode are
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31 * contained in port.c The ISR routines, which can only be compiled
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32 * to ARM mode, are contained in this file.
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33 *----------------------------------------------------------*/
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38 + The critical section management functions have been changed. These no
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39 longer modify the stack and are safe to use at all optimisation levels.
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40 The functions are now also the same for both ARM and THUMB modes.
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44 + Removed the 'static' from the definition of vNonPreemptiveTick() to
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45 allow the demo to link when using the cooperative scheduler.
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49 + The assembler statements are now included in a single asm block rather
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50 than each line having its own asm block.
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54 /* Scheduler includes. */
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55 #include "FreeRTOS.h"
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57 /* Constants required to handle interrupts. */
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58 #define portTIMER_MATCH_ISR_BIT ( ( uint8_t ) 0x01 )
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59 #define portCLEAR_VIC_INTERRUPT ( ( uint32_t ) 0 )
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61 /* Constants required to handle critical sections. */
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62 #define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
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63 volatile uint32_t ulCriticalNesting = 9999UL;
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65 /*-----------------------------------------------------------*/
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67 /* ISR to handle manual context switches (from a call to taskYIELD()). */
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68 void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));
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71 * The scheduler can only be started from ARM mode, hence the inclusion of this
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74 void vPortISRStartFirstTask( void );
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75 /*-----------------------------------------------------------*/
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77 void vPortISRStartFirstTask( void )
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79 /* Simply start the scheduler. This is included here as it can only be
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80 called from ARM mode. */
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81 portRESTORE_CONTEXT();
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83 /*-----------------------------------------------------------*/
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86 * Called by portYIELD() or taskYIELD() to manually force a context switch.
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88 * When a context switch is performed from the task level the saved task
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89 * context is made to look as if it occurred from within the tick ISR. This
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90 * way the same restore context function can be used when restoring the context
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91 * saved from the ISR or that saved from a call to vPortYieldProcessor.
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93 void vPortYieldProcessor( void )
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95 /* Within an IRQ ISR the link register has an offset from the true return
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96 address, but an SWI ISR does not. Add the offset manually so the same
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97 ISR return code can be used in both cases. */
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98 __asm volatile ( "ADD LR, LR, #4" );
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100 /* Perform the context switch. First save the context of the current task. */
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101 portSAVE_CONTEXT();
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103 /* Find the highest priority task that is ready to run. */
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104 __asm volatile ( "bl vTaskSwitchContext" );
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106 /* Restore the context of the new task. */
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107 portRESTORE_CONTEXT();
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109 /*-----------------------------------------------------------*/
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112 * The ISR used for the scheduler tick.
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114 void vTickISR( void ) __attribute__((naked));
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115 void vTickISR( void )
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117 /* Save the context of the interrupted task. */
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118 portSAVE_CONTEXT();
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120 /* Increment the RTOS tick count, then look for the highest priority
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121 task that is ready to run. */
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124 " bl xTaskIncrementTick \t\n" \
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125 " cmp r0, #0 \t\n" \
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126 " beq SkipContextSwitch \t\n" \
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127 " bl vTaskSwitchContext \t\n" \
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128 "SkipContextSwitch: \t\n"
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131 /* Ready for the next interrupt. */
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132 T0_IR = portTIMER_MATCH_ISR_BIT;
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133 VICVectAddr = portCLEAR_VIC_INTERRUPT;
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135 /* Restore the context of the new task. */
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136 portRESTORE_CONTEXT();
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138 /*-----------------------------------------------------------*/
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141 * The interrupt management utilities can only be called from ARM mode. When
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142 * THUMB_INTERWORK is defined the utilities are defined as functions here to
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143 * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then
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144 * the utilities are defined as macros in portmacro.h - as per other ports.
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146 #ifdef THUMB_INTERWORK
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148 void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
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149 void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
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151 void vPortDisableInterruptsFromThumb( void )
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154 "STMDB SP!, {R0} \n\t" /* Push R0. */
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155 "MRS R0, CPSR \n\t" /* Get CPSR. */
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156 "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
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157 "MSR CPSR, R0 \n\t" /* Write back modified value. */
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158 "LDMIA SP!, {R0} \n\t" /* Pop R0. */
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159 "BX R14" ); /* Return back to thumb. */
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162 void vPortEnableInterruptsFromThumb( void )
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165 "STMDB SP!, {R0} \n\t" /* Push R0. */
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166 "MRS R0, CPSR \n\t" /* Get CPSR. */
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167 "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
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168 "MSR CPSR, R0 \n\t" /* Write back modified value. */
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169 "LDMIA SP!, {R0} \n\t" /* Pop R0. */
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170 "BX R14" ); /* Return back to thumb. */
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173 #endif /* THUMB_INTERWORK */
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175 /* The code generated by the GCC compiler uses the stack in different ways at
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176 different optimisation levels. The interrupt flags can therefore not always
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177 be saved to the stack. Instead the critical section nesting level is stored
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178 in a variable, which is then saved as part of the stack context. */
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179 void vPortEnterCritical( void )
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181 /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
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183 "STMDB SP!, {R0} \n\t" /* Push R0. */
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184 "MRS R0, CPSR \n\t" /* Get CPSR. */
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185 "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
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186 "MSR CPSR, R0 \n\t" /* Write back modified value. */
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187 "LDMIA SP!, {R0}" ); /* Pop R0. */
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189 /* Now interrupts are disabled ulCriticalNesting can be accessed
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190 directly. Increment ulCriticalNesting to keep a count of how many times
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191 portENTER_CRITICAL() has been called. */
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192 ulCriticalNesting++;
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195 void vPortExitCritical( void )
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197 if( ulCriticalNesting > portNO_CRITICAL_NESTING )
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199 /* Decrement the nesting count as we are leaving a critical section. */
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200 ulCriticalNesting--;
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202 /* If the nesting level has reached zero then interrupts should be
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204 if( ulCriticalNesting == portNO_CRITICAL_NESTING )
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206 /* Enable interrupts as per portEXIT_CRITICAL(). */
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208 "STMDB SP!, {R0} \n\t" /* Push R0. */
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209 "MRS R0, CPSR \n\t" /* Get CPSR. */
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210 "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
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211 "MSR CPSR, R0 \n\t" /* Write back modified value. */
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212 "LDMIA SP!, {R0}" ); /* Pop R0. */
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