2 * FreeRTOS Kernel V10.0.0
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3 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software. If you wish to use our Amazon
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14 * FreeRTOS name, please do so in a fair use way that does not cause confusion.
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16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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18 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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19 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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20 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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23 * http://www.FreeRTOS.org
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24 * http://aws.amazon.com/freertos
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26 * 1 tab == 4 spaces!
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29 /* Standard includes. */
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32 /* Scheduler includes. */
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33 #include "FreeRTOS.h"
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36 #ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
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37 #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
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40 #ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
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41 #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
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44 #ifndef configUNIQUE_INTERRUPT_PRIORITIES
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45 #error configUNIQUE_INTERRUPT_PRIORITIES must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
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48 #ifndef configSETUP_TICK_INTERRUPT
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49 #error configSETUP_TICK_INTERRUPT() must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
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50 #endif /* configSETUP_TICK_INTERRUPT */
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52 #ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
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53 #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
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56 #if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
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57 #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
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60 #if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
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61 #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
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64 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
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65 /* Check the configuration. */
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66 #if( configMAX_PRIORITIES > 32 )
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67 #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
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69 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
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71 /* In case security extensions are implemented. */
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72 #if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
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73 #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
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76 /* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in
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78 #ifndef configCLEAR_TICK_INTERRUPT
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79 #define configCLEAR_TICK_INTERRUPT()
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82 /* A critical section is exited when the critical section nesting count reaches
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84 #define portNO_CRITICAL_NESTING ( ( size_t ) 0 )
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86 /* In all GICs 255 can be written to the priority mask register to unmask all
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87 (but the lowest) interrupt priority. */
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88 #define portUNMASK_VALUE ( 0xFFUL )
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90 /* Tasks are not created with a floating point context, but can be given a
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91 floating point context after they have been created. A variable is stored as
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92 part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
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93 does not have an FPU context, or any other value if the task does have an FPU
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95 #define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
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97 /* Constants required to setup the initial task context. */
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98 #define portSP_ELx ( ( StackType_t ) 0x01 )
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99 #define portSP_EL0 ( ( StackType_t ) 0x00 )
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101 #if defined( GUEST )
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102 #define portEL1 ( ( StackType_t ) 0x04 )
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103 #define portINITIAL_PSTATE ( portEL1 | portSP_EL0 )
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105 #define portEL3 ( ( StackType_t ) 0x0c )
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106 /* At the time of writing, the BSP only supports EL3. */
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107 #define portINITIAL_PSTATE ( portEL3 | portSP_EL0 )
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111 /* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
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113 #define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 )
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115 /* Masks all bits in the APSR other than the mode bits. */
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116 #define portAPSR_MODE_BITS_MASK ( 0x0C )
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118 /* The I bit in the DAIF bits. */
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119 #define portDAIF_I ( 0x80 )
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121 /* Macro to unmask all interrupt priorities. */
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122 #define portCLEAR_INTERRUPT_MASK() \
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124 portDISABLE_INTERRUPTS(); \
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125 portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \
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126 __asm volatile ( "DSB SY \n" \
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128 portENABLE_INTERRUPTS(); \
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131 /* Hardware specifics used when sanity checking the configuration. */
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132 #define portINTERRUPT_PRIORITY_REGISTER_OFFSET 0x400UL
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133 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
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134 #define portBIT_0_SET ( ( uint8_t ) 0x01 )
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136 /*-----------------------------------------------------------*/
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139 * Starts the first task executing. This function is necessarily written in
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140 * assembly code so is implemented in portASM.s.
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142 extern void vPortRestoreTaskContext( void );
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144 /*-----------------------------------------------------------*/
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146 /* A variable is used to keep track of the critical section nesting. This
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147 variable has to be stored as part of the task context and must be initialised to
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148 a non zero value to ensure interrupts don't inadvertently become unmasked before
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149 the scheduler starts. As it is stored as part of the task context it will
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150 automatically be set to 0 when the first task is started. */
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151 volatile uint64_t ullCriticalNesting = 9999ULL;
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153 /* Saved as part of the task context. If ullPortTaskHasFPUContext is non-zero
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154 then floating point context must be saved and restored for the task. */
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155 uint64_t ullPortTaskHasFPUContext = pdFALSE;
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157 /* Set to 1 to pend a context switch from an ISR. */
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158 uint64_t ullPortYieldRequired = pdFALSE;
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160 /* Counts the interrupt nesting depth. A context switch is only performed if
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161 if the nesting depth is 0. */
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162 uint64_t ullPortInterruptNesting = 0;
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164 /* Used in the ASM code. */
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165 __attribute__(( used )) const uint64_t ullICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;
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166 __attribute__(( used )) const uint64_t ullICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;
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167 __attribute__(( used )) const uint64_t ullICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;
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168 __attribute__(( used )) const uint64_t ullMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
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170 /*-----------------------------------------------------------*/
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173 * See header file for description.
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175 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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177 /* Setup the initial stack of the task. The stack is set exactly as
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178 expected by the portRESTORE_CONTEXT() macro. */
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180 /* First all the general purpose registers. */
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182 *pxTopOfStack = 0x0101010101010101ULL; /* R1 */
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184 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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186 *pxTopOfStack = 0x0303030303030303ULL; /* R3 */
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188 *pxTopOfStack = 0x0202020202020202ULL; /* R2 */
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190 *pxTopOfStack = 0x0505050505050505ULL; /* R5 */
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192 *pxTopOfStack = 0x0404040404040404ULL; /* R4 */
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194 *pxTopOfStack = 0x0707070707070707ULL; /* R7 */
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196 *pxTopOfStack = 0x0606060606060606ULL; /* R6 */
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198 *pxTopOfStack = 0x0909090909090909ULL; /* R9 */
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200 *pxTopOfStack = 0x0808080808080808ULL; /* R8 */
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202 *pxTopOfStack = 0x1111111111111111ULL; /* R11 */
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204 *pxTopOfStack = 0x1010101010101010ULL; /* R10 */
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206 *pxTopOfStack = 0x1313131313131313ULL; /* R13 */
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208 *pxTopOfStack = 0x1212121212121212ULL; /* R12 */
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210 *pxTopOfStack = 0x1515151515151515ULL; /* R15 */
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212 *pxTopOfStack = 0x1414141414141414ULL; /* R14 */
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214 *pxTopOfStack = 0x1717171717171717ULL; /* R17 */
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216 *pxTopOfStack = 0x1616161616161616ULL; /* R16 */
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218 *pxTopOfStack = 0x1919191919191919ULL; /* R19 */
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220 *pxTopOfStack = 0x1818181818181818ULL; /* R18 */
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222 *pxTopOfStack = 0x2121212121212121ULL; /* R21 */
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224 *pxTopOfStack = 0x2020202020202020ULL; /* R20 */
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226 *pxTopOfStack = 0x2323232323232323ULL; /* R23 */
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228 *pxTopOfStack = 0x2222222222222222ULL; /* R22 */
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230 *pxTopOfStack = 0x2525252525252525ULL; /* R25 */
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232 *pxTopOfStack = 0x2424242424242424ULL; /* R24 */
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234 *pxTopOfStack = 0x2727272727272727ULL; /* R27 */
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236 *pxTopOfStack = 0x2626262626262626ULL; /* R26 */
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238 *pxTopOfStack = 0x2929292929292929ULL; /* R29 */
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240 *pxTopOfStack = 0x2828282828282828ULL; /* R28 */
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242 *pxTopOfStack = ( StackType_t ) 0x00; /* XZR - has no effect, used so there are an even number of registers. */
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244 *pxTopOfStack = ( StackType_t ) 0x00; /* R30 - procedure call link register. */
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247 *pxTopOfStack = portINITIAL_PSTATE;
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250 *pxTopOfStack = ( StackType_t ) pxCode; /* Exception return address. */
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253 /* The task will start with a critical nesting count of 0 as interrupts are
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255 *pxTopOfStack = portNO_CRITICAL_NESTING;
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258 /* The task will start without a floating point context. A task that uses
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259 the floating point hardware must call vPortTaskUsesFPU() before executing
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260 any floating point instructions. */
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261 *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
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263 return pxTopOfStack;
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265 /*-----------------------------------------------------------*/
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267 BaseType_t xPortStartScheduler( void )
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271 #if( configASSERT_DEFINED == 1 )
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273 volatile uint32_t ulOriginalPriority;
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274 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET );
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275 volatile uint8_t ucMaxPriorityValue;
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277 /* Determine how many priority bits are implemented in the GIC.
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279 Save the interrupt priority value that is about to be clobbered. */
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280 ulOriginalPriority = *pucFirstUserPriorityRegister;
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282 /* Determine the number of priority bits available. First write to
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283 all possible bits. */
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284 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
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286 /* Read the value back to see how many bits stuck. */
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287 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
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289 /* Shift to the least significant bits. */
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290 while( ( ucMaxPriorityValue & portBIT_0_SET ) != portBIT_0_SET )
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292 ucMaxPriorityValue >>= ( uint8_t ) 0x01;
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295 /* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read
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298 configASSERT( ucMaxPriorityValue >= portLOWEST_INTERRUPT_PRIORITY );
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301 /* Restore the clobbered interrupt priority register to its original
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303 *pucFirstUserPriorityRegister = ulOriginalPriority;
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305 #endif /* conifgASSERT_DEFINED */
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308 /* At the time of writing, the BSP only supports EL3. */
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309 __asm volatile ( "MRS %0, CurrentEL" : "=r" ( ulAPSR ) );
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310 ulAPSR &= portAPSR_MODE_BITS_MASK;
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312 #if defined( GUEST )
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313 #warning Building for execution as a guest under XEN. THIS IS NOT A FULLY TESTED PATH.
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314 configASSERT( ulAPSR == portEL1 );
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315 if( ulAPSR == portEL1 )
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317 configASSERT( ulAPSR == portEL3 );
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318 if( ulAPSR == portEL3 )
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321 /* Only continue if the binary point value is set to its lowest possible
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322 setting. See the comments in vPortValidateInterruptPriority() below for
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323 more information. */
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324 configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
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326 if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
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328 /* Interrupts are turned off in the CPU itself to ensure a tick does
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329 not execute while the scheduler is being started. Interrupts are
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330 automatically turned back on in the CPU when the first task starts
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332 portDISABLE_INTERRUPTS();
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334 /* Start the timer that generates the tick ISR. */
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335 configSETUP_TICK_INTERRUPT();
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337 /* Start the first task executing. */
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338 vPortRestoreTaskContext();
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344 /*-----------------------------------------------------------*/
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346 void vPortEndScheduler( void )
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348 /* Not implemented in ports where there is nothing to return to.
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349 Artificially force an assert. */
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350 configASSERT( ullCriticalNesting == 1000ULL );
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352 /*-----------------------------------------------------------*/
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354 void vPortEnterCritical( void )
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356 /* Mask interrupts up to the max syscall interrupt priority. */
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357 uxPortSetInterruptMask();
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359 /* Now interrupts are disabled ullCriticalNesting can be accessed
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360 directly. Increment ullCriticalNesting to keep a count of how many times
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361 portENTER_CRITICAL() has been called. */
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362 ullCriticalNesting++;
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364 /* This is not the interrupt safe version of the enter critical function so
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365 assert() if it is being called from an interrupt context. Only API
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366 functions that end in "FromISR" can be used in an interrupt. Only assert if
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367 the critical nesting count is 1 to protect against recursive calls if the
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368 assert function also uses a critical section. */
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369 if( ullCriticalNesting == 1ULL )
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371 configASSERT( ullPortInterruptNesting == 0 );
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374 /*-----------------------------------------------------------*/
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376 void vPortExitCritical( void )
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378 if( ullCriticalNesting > portNO_CRITICAL_NESTING )
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380 /* Decrement the nesting count as the critical section is being
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382 ullCriticalNesting--;
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384 /* If the nesting level has reached zero then all interrupt
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385 priorities must be re-enabled. */
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386 if( ullCriticalNesting == portNO_CRITICAL_NESTING )
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388 /* Critical nesting has reached zero so all interrupt priorities
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389 should be unmasked. */
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390 portCLEAR_INTERRUPT_MASK();
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394 /*-----------------------------------------------------------*/
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396 void FreeRTOS_Tick_Handler( void )
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398 /* Must be the lowest possible priority. */
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399 #if !defined( QEMU )
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401 configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER == ( uint32_t ) ( portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
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405 /* Interrupts should not be enabled before this point. */
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406 #if( configASSERT_DEFINED == 1 )
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408 uint32_t ulMaskBits;
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410 __asm volatile( "mrs %0, daif" : "=r"( ulMaskBits ) :: "memory" );
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411 configASSERT( ( ulMaskBits & portDAIF_I ) != 0 );
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413 #endif /* configASSERT_DEFINED */
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415 /* Set interrupt mask before altering scheduler structures. The tick
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416 handler runs at the lowest priority, so interrupts cannot already be masked,
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417 so there is no need to save and restore the current mask value. It is
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418 necessary to turn off interrupts in the CPU itself while the ICCPMR is being
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420 portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
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421 __asm volatile ( "dsb sy \n"
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422 "isb sy \n" ::: "memory" );
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424 /* Ok to enable interrupts after the interrupt source has been cleared. */
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425 configCLEAR_TICK_INTERRUPT();
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426 portENABLE_INTERRUPTS();
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428 /* Increment the RTOS tick. */
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429 if( xTaskIncrementTick() != pdFALSE )
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431 ullPortYieldRequired = pdTRUE;
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434 /* Ensure all interrupt priorities are active again. */
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435 portCLEAR_INTERRUPT_MASK();
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437 /*-----------------------------------------------------------*/
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439 void vPortTaskUsesFPU( void )
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441 /* A task is registering the fact that it needs an FPU context. Set the
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442 FPU flag (which is saved as part of the task context). */
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443 ullPortTaskHasFPUContext = pdTRUE;
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445 /* Consider initialising the FPSR here - but probably not necessary in
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448 /*-----------------------------------------------------------*/
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450 void vPortClearInterruptMask( UBaseType_t uxNewMaskValue )
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452 if( uxNewMaskValue == pdFALSE )
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454 portCLEAR_INTERRUPT_MASK();
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457 /*-----------------------------------------------------------*/
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459 UBaseType_t uxPortSetInterruptMask( void )
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463 /* Interrupt in the CPU must be turned off while the ICCPMR is being
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465 portDISABLE_INTERRUPTS();
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466 if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
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468 /* Interrupts were already masked. */
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473 ulReturn = pdFALSE;
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474 portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
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475 __asm volatile ( "dsb sy \n"
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476 "isb sy \n" ::: "memory" );
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478 portENABLE_INTERRUPTS();
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482 /*-----------------------------------------------------------*/
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484 #if( configASSERT_DEFINED == 1 )
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486 void vPortValidateInterruptPriority( void )
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488 /* The following assertion will fail if a service routine (ISR) for
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489 an interrupt that has been assigned a priority above
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490 configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
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491 function. ISR safe FreeRTOS API functions must *only* be called
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492 from interrupts that have been assigned a priority at or below
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493 configMAX_SYSCALL_INTERRUPT_PRIORITY.
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495 Numerically low interrupt priority numbers represent logically high
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496 interrupt priorities, therefore the priority of the interrupt must
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497 be set to a value equal to or numerically *higher* than
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498 configMAX_SYSCALL_INTERRUPT_PRIORITY.
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500 FreeRTOS maintains separate thread and ISR API functions to ensure
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501 interrupt entry is as fast and simple as possible. */
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502 configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
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504 /* Priority grouping: The interrupt controller (GIC) allows the bits
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505 that define each interrupt's priority to be split between bits that
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506 define the interrupt's pre-emption priority bits and bits that define
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507 the interrupt's sub-priority. For simplicity all bits must be defined
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508 to be pre-emption priority bits. The following assertion will fail if
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509 this is not the case (if some bits represent a sub-priority).
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511 The priority grouping is configured by the GIC's binary point register
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512 (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest
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513 possible value (which may be above 0). */
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514 configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
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517 #endif /* configASSERT_DEFINED */
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518 /*-----------------------------------------------------------*/
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