git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/ARM_CA9/portmacro.h

   1 /*\r
   2     FreeRTOS V8.1.2 - Copyright (C) 2014 Real Time Engineers Ltd.\r
   3     All rights reserved\r
   4 \r
   5     VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
   6 \r
   7     ***************************************************************************\r
   8      *                                                                       *\r
   9      *    FreeRTOS provides completely free yet professionally developed,    *\r
  10      *    robust, strictly quality controlled, supported, and cross          *\r
  11      *    platform software that has become a de facto standard.             *\r
  12      *                                                                       *\r
  13      *    Help yourself get started quickly and support the FreeRTOS         *\r
  14      *    project by purchasing a FreeRTOS tutorial book, reference          *\r
  15      *    manual, or both from: http://www.FreeRTOS.org/Documentation        *\r
  16      *                                                                       *\r
  17      *    Thank you!                                                         *\r
  18      *                                                                       *\r
  19     ***************************************************************************\r
  20 \r
  21     This file is part of the FreeRTOS distribution.\r
  22 \r
  23     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  24     the terms of the GNU General Public License (version 2) as published by the\r
  25     Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
  26 \r
  27     >>!   NOTE: The modification to the GPL is included to allow you to     !<<\r
  28     >>!   distribute a combined work that includes FreeRTOS without being   !<<\r
  29     >>!   obliged to provide the source code for proprietary components     !<<\r
  30     >>!   outside of the FreeRTOS kernel.                                   !<<\r
  31 \r
  32     FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
  33     WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
  34     FOR A PARTICULAR PURPOSE.  Full license text is available from the following\r
  35     link: http://www.freertos.org/a00114.html\r
  36 \r
  37     1 tab == 4 spaces!\r
  38 \r
  39     ***************************************************************************\r
  40      *                                                                       *\r
  41      *    Having a problem?  Start by reading the FAQ "My application does   *\r
  42      *    not run, what could be wrong?"                                     *\r
  43      *                                                                       *\r
  44      *    http://www.FreeRTOS.org/FAQHelp.html                               *\r
  45      *                                                                       *\r
  46     ***************************************************************************\r
  47 \r
  48     http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
  49     license and Real Time Engineers Ltd. contact details.\r
  50 \r
  51     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
  52     including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
  53     compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
  54 \r
  55     http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
  56     Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS\r
  57     licenses offer ticketed support, indemnification and middleware.\r
  58 \r
  59     http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
  60     engineered and independently SIL3 certified version for use in safety and\r
  61     mission critical applications that require provable dependability.\r
  62 \r
  63     1 tab == 4 spaces!\r
  64 */\r
  65 \r
  66 #ifndef PORTMACRO_H\r
  67 #define PORTMACRO_H\r
  68 \r
  69 #ifdef __cplusplus\r
  70         extern "C" {\r
  71 #endif\r
  72 \r
  73 /*-----------------------------------------------------------\r
  74  * Port specific definitions.\r
  75  *\r
  76  * The settings in this file configure FreeRTOS correctly for the given hardware\r
  77  * and compiler.\r
  78  *\r
  79  * These settings should not be altered.\r
  80  *-----------------------------------------------------------\r
  81  */\r
  82 \r
  83 /* Type definitions. */\r
  84 #define portCHAR                char\r
  85 #define portFLOAT               float\r
  86 #define portDOUBLE              double\r
  87 #define portLONG                long\r
  88 #define portSHORT               short\r
  89 #define portSTACK_TYPE  uint32_t\r
  90 #define portBASE_TYPE   long\r
  91 \r
  92 typedef portSTACK_TYPE StackType_t;\r
  93 typedef long BaseType_t;\r
  94 typedef unsigned long UBaseType_t;\r
  95 \r
  96 typedef uint32_t TickType_t;\r
  97 #define portMAX_DELAY ( TickType_t ) 0xffffffffUL\r
  98 \r
  99 /*-----------------------------------------------------------*/\r
 100 \r
 101 /* Hardware specifics. */\r
 102 #define portSTACK_GROWTH                        ( -1 )\r
 103 #define portTICK_PERIOD_MS                      ( ( TickType_t ) 1000 / configTICK_RATE_HZ )\r
 104 #define portBYTE_ALIGNMENT                      8\r
 105 \r
 106 /*-----------------------------------------------------------*/\r
 107 \r
 108 /* Task utilities. */\r
 109 \r
 110 /* Called at the end of an ISR that can cause a context switch. */\r
 111 #define portEND_SWITCHING_ISR( xSwitchRequired )\\r
 112 {                                                                                               \\r
 113 extern uint32_t ulPortYieldRequired;                    \\r
 114                                                                                                 \\r
 115         if( xSwitchRequired != pdFALSE )                        \\r
 116         {                                                                                       \\r
 117                 ulPortYieldRequired = pdTRUE;                   \\r
 118         }                                                                                       \\r
 119 }\r
 120 \r
 121 #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\r
 122 #define portYIELD() __asm volatile ( "SWI 0" );\r
 123 \r
 124 \r
 125 /*-----------------------------------------------------------\r
 126  * Critical section control\r
 127  *----------------------------------------------------------*/\r
 128 \r
 129 extern void vPortEnterCritical( void );\r
 130 extern void vPortExitCritical( void );\r
 131 extern uint32_t ulPortSetInterruptMask( void );\r
 132 extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );\r
 133 extern void vPortInstallFreeRTOSVectorTable( void );\r
 134 \r
 135 /* These macros do not globally disable/enable interrupts.  They do mask off\r
 136 interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */\r
 137 #define portENTER_CRITICAL()            vPortEnterCritical();\r
 138 #define portEXIT_CRITICAL()                     vPortExitCritical();\r
 139 #define portDISABLE_INTERRUPTS()        ulPortSetInterruptMask()\r
 140 #define portENABLE_INTERRUPTS()         vPortClearInterruptMask( 0 )\r
 141 #define portSET_INTERRUPT_MASK_FROM_ISR()               ulPortSetInterruptMask()\r
 142 #define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)    vPortClearInterruptMask(x)\r
 143 \r
 144 /*-----------------------------------------------------------*/\r
 145 \r
 146 /* Task function macros as described on the FreeRTOS.org WEB site.  These are\r
 147 not required for this port but included in case common demo code that uses these\r
 148 macros is used. */\r
 149 #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )      void vFunction( void *pvParameters )\r
 150 #define portTASK_FUNCTION( vFunction, pvParameters )    void vFunction( void *pvParameters )\r
 151 \r
 152 /* Prototype of the FreeRTOS tick handler.  This must be installed as the\r
 153 handler for whichever peripheral is used to generate the RTOS tick. */\r
 154 void FreeRTOS_Tick_Handler( void );\r
 155 \r
 156 /* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()\r
 157 before any floating point instructions are executed. */\r
 158 void vPortTaskUsesFPU( void );\r
 159 #define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()\r
 160 \r
 161 #define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )\r
 162 #define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )\r
 163 \r
 164 /* Architecture specific optimisations. */\r
 165 #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION\r
 166         #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1\r
 167 #endif\r
 168 \r
 169 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1\r
 170 \r
 171         /* Store/clear the ready priorities in a bit map. */\r
 172         #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )\r
 173         #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )\r
 174 \r
 175         /*-----------------------------------------------------------*/\r
 176 \r
 177         #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( uxReadyPriorities ) )\r
 178 \r
 179 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\r
 180 \r
 181 #ifdef configASSERT\r
 182         void vPortValidateInterruptPriority( void );\r
 183         #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()      vPortValidateInterruptPriority()\r
 184 #endif /* configASSERT */\r
 185 \r
 186 #define portNOP() __asm volatile( "NOP" )\r
 187 \r
 188 \r
 189 #ifdef __cplusplus\r
 190         } /* extern C */\r
 191 #endif\r
 192 \r
 193 \r
 194 /* The number of bits to shift for an interrupt priority is dependent on the\r
 195 number of bits implemented by the interrupt controller. */\r
 196 #if configUNIQUE_INTERRUPT_PRIORITIES == 16\r
 197         #define portPRIORITY_SHIFT 4\r
 198         #define portMAX_BINARY_POINT_VALUE      3\r
 199 #elif configUNIQUE_INTERRUPT_PRIORITIES == 32\r
 200         #define portPRIORITY_SHIFT 3\r
 201         #define portMAX_BINARY_POINT_VALUE      2\r
 202 #elif configUNIQUE_INTERRUPT_PRIORITIES == 64\r
 203         #define portPRIORITY_SHIFT 2\r
 204         #define portMAX_BINARY_POINT_VALUE      1\r
 205 #elif configUNIQUE_INTERRUPT_PRIORITIES == 128\r
 206         #define portPRIORITY_SHIFT 1\r
 207         #define portMAX_BINARY_POINT_VALUE      0\r
 208 #elif configUNIQUE_INTERRUPT_PRIORITIES == 256\r
 209         #define portPRIORITY_SHIFT 0\r
 210         #define portMAX_BINARY_POINT_VALUE      0\r
 211 #else\r
 212         #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting.  configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware\r
 213 #endif\r
 214 \r
 215 /* Interrupt controller access addresses. */\r
 216 #define portICCPMR_PRIORITY_MASK_OFFSET                                                 ( 0x04 )\r
 217 #define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET                                 ( 0x0C )\r
 218 #define portICCEOIR_END_OF_INTERRUPT_OFFSET                                     ( 0x10 )\r
 219 #define portICCBPR_BINARY_POINT_OFFSET                                                  ( 0x08 )\r
 220 #define portICCRPR_RUNNING_PRIORITY_OFFSET                                              ( 0x14 )\r
 221 \r
 222 #define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS          ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )\r
 223 #define portICCPMR_PRIORITY_MASK_REGISTER                                       ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )\r
 224 #define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS       ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )\r
 225 #define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS           ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )\r
 226 #define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS                       ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )\r
 227 #define portICCBPR_BINARY_POINT_REGISTER                                        ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )\r
 228 #define portICCRPR_RUNNING_PRIORITY_REGISTER                            ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )\r
 229 \r
 230 #endif /* PORTMACRO_H */\r
 231 \r