git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/ARM_CM0/port.c

   1 /*\r
   2     FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd.\r
   3     All rights reserved\r
   4 \r
   5     VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
   6 \r
   7     This file is part of the FreeRTOS distribution.\r
   8 \r
   9     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  10     the terms of the GNU General Public License (version 2) as published by the\r
  11     Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
  12 \r
  13     ***************************************************************************\r
  14     >>!   NOTE: The modification to the GPL is included to allow you to     !<<\r
  15     >>!   distribute a combined work that includes FreeRTOS without being   !<<\r
  16     >>!   obliged to provide the source code for proprietary components     !<<\r
  17     >>!   outside of the FreeRTOS kernel.                                   !<<\r
  18     ***************************************************************************\r
  19 \r
  20     FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
  21     WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
  22     FOR A PARTICULAR PURPOSE.  Full license text is available on the following\r
  23     link: http://www.freertos.org/a00114.html\r
  24 \r
  25     ***************************************************************************\r
  26      *                                                                       *\r
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  35      *    http://www.FreeRTOS.org/Documentation                              *\r
  36      *                                                                       *\r
  37     ***************************************************************************\r
  38 \r
  39     http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading\r
  40     the FAQ page "My application does not run, what could be wrong?".  Have you\r
  41     defined configASSERT()?\r
  42 \r
  43     http://www.FreeRTOS.org/support - In return for receiving this top quality\r
  44     embedded software for free we request you assist our global community by\r
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  46 \r
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  48     be as productive as possible as early as possible.  Now you can receive\r
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  50     Ltd, and the world's leading authority on the world's leading RTOS.\r
  51 \r
  52     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
  53     including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
  54     compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
  55 \r
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  57     Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
  58 \r
  59     http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
  60     Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS\r
  61     licenses offer ticketed support, indemnification and commercial middleware.\r
  62 \r
  63     http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
  64     engineered and independently SIL3 certified version for use in safety and\r
  65     mission critical applications that require provable dependability.\r
  66 \r
  67     1 tab == 4 spaces!\r
  68 */\r
  69 \r
  70 /*-----------------------------------------------------------\r
  71  * Implementation of functions defined in portable.h for the ARM CM0 port.\r
  72  *----------------------------------------------------------*/\r
  73 \r
  74 /* Scheduler includes. */\r
  75 #include "FreeRTOS.h"\r
  76 #include "task.h"\r
  77 \r
  78 /* Constants required to manipulate the NVIC. */\r
  79 #define portNVIC_SYSTICK_CTRL           ( ( volatile uint32_t *) 0xe000e010 )\r
  80 #define portNVIC_SYSTICK_LOAD           ( ( volatile uint32_t *) 0xe000e014 )\r
  81 #define portNVIC_INT_CTRL                       ( ( volatile uint32_t *) 0xe000ed04 )\r
  82 #define portNVIC_SYSPRI2                        ( ( volatile uint32_t *) 0xe000ed20 )\r
  83 #define portNVIC_SYSTICK_CLK            0x00000004\r
  84 #define portNVIC_SYSTICK_INT            0x00000002\r
  85 #define portNVIC_SYSTICK_ENABLE         0x00000001\r
  86 #define portNVIC_PENDSVSET                      0x10000000\r
  87 #define portMIN_INTERRUPT_PRIORITY      ( 255UL )\r
  88 #define portNVIC_PENDSV_PRI                     ( portMIN_INTERRUPT_PRIORITY << 16UL )\r
  89 #define portNVIC_SYSTICK_PRI            ( portMIN_INTERRUPT_PRIORITY << 24UL )\r
  90 \r
  91 /* Constants required to set up the initial stack. */\r
  92 #define portINITIAL_XPSR                        ( 0x01000000 )\r
  93 \r
  94 /* Let the user override the pre-loading of the initial LR with the address of\r
  95 prvTaskExitError() in case it messes up unwinding of the stack in the\r
  96 debugger. */\r
  97 #ifdef configTASK_RETURN_ADDRESS\r
  98         #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS\r
  99 #else\r
 100         #define portTASK_RETURN_ADDRESS prvTaskExitError\r
 101 #endif\r
 102 \r
 103 /* Each task maintains its own interrupt status in the critical nesting\r
 104 variable. */\r
 105 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\r
 106 \r
 107 /*\r
 108  * Setup the timer to generate the tick interrupts.\r
 109  */\r
 110 static void prvSetupTimerInterrupt( void );\r
 111 \r
 112 /*\r
 113  * Exception handlers.\r
 114  */\r
 115 void xPortPendSVHandler( void ) __attribute__ (( naked ));\r
 116 void xPortSysTickHandler( void );\r
 117 void vPortSVCHandler( void );\r
 118 \r
 119 /*\r
 120  * Start first task is a separate function so it can be tested in isolation.\r
 121  */\r
 122 static void vPortStartFirstTask( void ) __attribute__ (( naked ));\r
 123 \r
 124 /*\r
 125  * Used to catch tasks that attempt to return from their implementing function.\r
 126  */\r
 127 static void prvTaskExitError( void );\r
 128 \r
 129 /*-----------------------------------------------------------*/\r
 130 \r
 131 /*\r
 132  * See header file for description.\r
 133  */\r
 134 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )\r
 135 {\r
 136         /* Simulate the stack frame as it would be created by a context switch\r
 137         interrupt. */\r
 138         pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
 139         *pxTopOfStack = portINITIAL_XPSR;       /* xPSR */\r
 140         pxTopOfStack--;\r
 141         *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
 142         pxTopOfStack--;\r
 143         *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;        /* LR */\r
 144         pxTopOfStack -= 5;      /* R12, R3, R2 and R1. */\r
 145         *pxTopOfStack = ( StackType_t ) pvParameters;   /* R0 */\r
 146         pxTopOfStack -= 8; /* R11..R4. */\r
 147 \r
 148         return pxTopOfStack;\r
 149 }\r
 150 /*-----------------------------------------------------------*/\r
 151 \r
 152 static void prvTaskExitError( void )\r
 153 {\r
 154         /* A function that implements a task must not exit or attempt to return to\r
 155         its caller as there is nothing to return to.  If a task wants to exit it\r
 156         should instead call vTaskDelete( NULL ).\r
 157 \r
 158         Artificially force an assert() to be triggered if configASSERT() is\r
 159         defined, then stop here so application writers can catch the error. */\r
 160         configASSERT( uxCriticalNesting == ~0UL );\r
 161         portDISABLE_INTERRUPTS();\r
 162         for( ;; );\r
 163 }\r
 164 /*-----------------------------------------------------------*/\r
 165 \r
 166 void vPortSVCHandler( void )\r
 167 {\r
 168         /* This function is no longer used, but retained for backward\r
 169         compatibility. */\r
 170 }\r
 171 /*-----------------------------------------------------------*/\r
 172 \r
 173 void vPortStartFirstTask( void )\r
 174 {\r
 175         /* The MSP stack is not reset as, unlike on M3/4 parts, there is no vector\r
 176         table offset register that can be used to locate the initial stack value.\r
 177         Not all M0 parts have the application vector table at address 0. */\r
 178         __asm volatile(\r
 179         "       ldr     r2, pxCurrentTCBConst2  \n" /* Obtain location of pxCurrentTCB. */\r
 180         "       ldr r3, [r2]                            \n"\r
 181         "       ldr r0, [r3]                            \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
 182         "       add r0, #32                                     \n" /* Discard everything up to r0. */\r
 183         "       msr psp, r0                                     \n" /* This is now the new top of stack to use in the task. */\r
 184         "       movs r0, #2                                     \n" /* Switch to the psp stack. */\r
 185         "       msr CONTROL, r0                         \n"\r
 186         "       isb                                                     \n"\r
 187         "       pop {r0-r5}                                     \n" /* Pop the registers that are saved automatically. */\r
 188         "       mov lr, r5                                      \n" /* lr is now in r5. */\r
 189         "       cpsie i                                         \n" /* The first task has its context and interrupts can be enabled. */\r
 190         "       pop {pc}                                        \n" /* Finally, pop the PC to jump to the user defined task code. */\r
 191         "                                                               \n"\r
 192         "       .align 4                                        \n"\r
 193         "pxCurrentTCBConst2: .word pxCurrentTCB   "\r
 194                                   );\r
 195 }\r
 196 /*-----------------------------------------------------------*/\r
 197 \r
 198 /*\r
 199  * See header file for description.\r
 200  */\r
 201 BaseType_t xPortStartScheduler( void )\r
 202 {\r
 203         /* Make PendSV, CallSV and SysTick the same priroity as the kernel. */\r
 204         *(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI;\r
 205         *(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI;\r
 206 \r
 207         /* Start the timer that generates the tick ISR.  Interrupts are disabled\r
 208         here already. */\r
 209         prvSetupTimerInterrupt();\r
 210 \r
 211         /* Initialise the critical nesting count ready for the first task. */\r
 212         uxCriticalNesting = 0;\r
 213 \r
 214         /* Start the first task. */\r
 215         vPortStartFirstTask();\r
 216 \r
 217         /* Should never get here as the tasks will now be executing!  Call the task\r
 218         exit error function to prevent compiler warnings about a static function\r
 219         not being called in the case that the application writer overrides this\r
 220         functionality by defining configTASK_RETURN_ADDRESS. */\r
 221         prvTaskExitError();\r
 222 \r
 223         /* Should not get here! */\r
 224         return 0;\r
 225 }\r
 226 /*-----------------------------------------------------------*/\r
 227 \r
 228 void vPortEndScheduler( void )\r
 229 {\r
 230         /* Not implemented in ports where there is nothing to return to.\r
 231         Artificially force an assert. */\r
 232         configASSERT( uxCriticalNesting == 1000UL );\r
 233 }\r
 234 /*-----------------------------------------------------------*/\r
 235 \r
 236 void vPortYield( void )\r
 237 {\r
 238         /* Set a PendSV to request a context switch. */\r
 239         *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;\r
 240 \r
 241         /* Barriers are normally not required but do ensure the code is completely\r
 242         within the specified behaviour for the architecture. */\r
 243         __asm volatile( "dsb" );\r
 244         __asm volatile( "isb" );\r
 245 }\r
 246 /*-----------------------------------------------------------*/\r
 247 \r
 248 void vPortEnterCritical( void )\r
 249 {\r
 250     portDISABLE_INTERRUPTS();\r
 251     uxCriticalNesting++;\r
 252         __asm volatile( "dsb" );\r
 253         __asm volatile( "isb" );\r
 254 }\r
 255 /*-----------------------------------------------------------*/\r
 256 \r
 257 void vPortExitCritical( void )\r
 258 {\r
 259         configASSERT( uxCriticalNesting );\r
 260     uxCriticalNesting--;\r
 261     if( uxCriticalNesting == 0 )\r
 262     {\r
 263         portENABLE_INTERRUPTS();\r
 264     }\r
 265 }\r
 266 /*-----------------------------------------------------------*/\r
 267 \r
 268 uint32_t ulSetInterruptMaskFromISR( void )\r
 269 {\r
 270         __asm volatile(\r
 271                                         " mrs r0, PRIMASK       \n"\r
 272                                         " cpsid i                       \n"\r
 273                                         " bx lr                           "\r
 274                                   );\r
 275 \r
 276         /* To avoid compiler warnings.  This line will never be reached. */\r
 277         return 0;\r
 278 }\r
 279 /*-----------------------------------------------------------*/\r
 280 \r
 281 void vClearInterruptMaskFromISR( uint32_t ulMask )\r
 282 {\r
 283         __asm volatile(\r
 284                                         " msr PRIMASK, r0       \n"\r
 285                                         " bx lr                           "\r
 286                                   );\r
 287 \r
 288         /* Just to avoid compiler warning. */\r
 289         ( void ) ulMask;\r
 290 }\r
 291 /*-----------------------------------------------------------*/\r
 292 \r
 293 void xPortPendSVHandler( void )\r
 294 {\r
 295         /* This is a naked function. */\r
 296 \r
 297         __asm volatile\r
 298         (\r
 299         "       mrs r0, psp                                                     \n"\r
 300         "                                                                               \n"\r
 301         "       ldr     r3, pxCurrentTCBConst                   \n" /* Get the location of the current TCB. */\r
 302         "       ldr     r2, [r3]                                                \n"\r
 303         "                                                                               \n"\r
 304         "       sub r0, r0, #32                                         \n" /* Make space for the remaining low registers. */\r
 305         "       str r0, [r2]                                            \n" /* Save the new top of stack. */\r
 306         "       stmia r0!, {r4-r7}                                      \n" /* Store the low registers that are not saved automatically. */\r
 307         "       mov r4, r8                                                      \n" /* Store the high registers. */\r
 308         "       mov r5, r9                                                      \n"\r
 309         "       mov r6, r10                                                     \n"\r
 310         "       mov r7, r11                                                     \n"\r
 311         "       stmia r0!, {r4-r7}                      \n"\r
 312         "                                                                               \n"\r
 313         "       push {r3, r14}                                          \n"\r
 314         "       cpsid i                                                         \n"\r
 315         "       bl vTaskSwitchContext                           \n"\r
 316         "       cpsie i                                                         \n"\r
 317         "       pop {r2, r3}                                            \n" /* lr goes in r3. r2 now holds tcb pointer. */\r
 318         "                                                                               \n"\r
 319         "       ldr r1, [r2]                                            \n"\r
 320         "       ldr r0, [r1]                                            \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
 321         "       add r0, r0, #16                                         \n" /* Move to the high registers. */\r
 322         "       ldmia r0!, {r4-r7}                                      \n" /* Pop the high registers. */\r
 323         "       mov r8, r4                                                      \n"\r
 324         "       mov r9, r5                                                      \n"\r
 325         "       mov r10, r6                                                     \n"\r
 326         "       mov r11, r7                                                     \n"\r
 327         "                                                                               \n"\r
 328         "       msr psp, r0                                                     \n" /* Remember the new top of stack for the task. */\r
 329         "                                                                               \n"\r
 330         "       sub r0, r0, #32                                         \n" /* Go back for the low registers that are not automatically restored. */\r
 331         "       ldmia r0!, {r4-r7}                      \n" /* Pop low registers.  */\r
 332         "                                                                               \n"\r
 333         "       bx r3                                                           \n"\r
 334         "                                                                               \n"\r
 335         "       .align 4                                                        \n"\r
 336         "pxCurrentTCBConst: .word pxCurrentTCB    "\r
 337         );\r
 338 }\r
 339 /*-----------------------------------------------------------*/\r
 340 \r
 341 void xPortSysTickHandler( void )\r
 342 {\r
 343 uint32_t ulPreviousMask;\r
 344 \r
 345         ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();\r
 346         {\r
 347                 /* Increment the RTOS tick. */\r
 348                 if( xTaskIncrementTick() != pdFALSE )\r
 349                 {\r
 350                         /* Pend a context switch. */\r
 351                         *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;\r
 352                 }\r
 353         }\r
 354         portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );\r
 355 }\r
 356 /*-----------------------------------------------------------*/\r
 357 \r
 358 /*\r
 359  * Setup the systick timer to generate the tick interrupts at the required\r
 360  * frequency.\r
 361  */\r
 362 void prvSetupTimerInterrupt( void )\r
 363 {\r
 364         /* Configure SysTick to interrupt at the requested rate. */\r
 365         *(portNVIC_SYSTICK_LOAD) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
 366         *(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\r
 367 }\r
 368 /*-----------------------------------------------------------*/\r
 369 \r