git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/ARM_CM3/port.c

   1 /*\r
   2     FreeRTOS V7.3.0 - Copyright (C) 2012 Real Time Engineers Ltd.\r
   3 \r
   4     FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME.  PLEASE VISIT\r
   5     http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
   6 \r
   7     ***************************************************************************\r
   8      *                                                                       *\r
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  10      *    Complete, revised, and edited pdf reference manuals are also       *\r
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  23      *                                                                       *\r
  24     ***************************************************************************\r
  25 \r
  26 \r
  27     This file is part of the FreeRTOS distribution.\r
  28 \r
  29     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  30     the terms of the GNU General Public License (version 2) as published by the\r
  31     Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
  32     >>>NOTE<<< The modification to the GPL is included to allow you to\r
  33     distribute a combined work that includes FreeRTOS without being obliged to\r
  34     provide the source code for proprietary components outside of the FreeRTOS\r
  35     kernel.  FreeRTOS is distributed in the hope that it will be useful, but\r
  36     WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
  37     or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
  38     more details. You should have received a copy of the GNU General Public\r
  39     License and the FreeRTOS license exception along with FreeRTOS; if not it\r
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  41     by writing to Richard Barry, contact details for whom are available on the\r
  42     FreeRTOS WEB site.\r
  43 \r
  44     1 tab == 4 spaces!\r
  45 \r
  46     ***************************************************************************\r
  47      *                                                                       *\r
  48      *    Having a problem?  Start by reading the FAQ "My application does   *\r
  49      *    not run, what could be wrong?"                                     *\r
  50      *                                                                       *\r
  51      *    http://www.FreeRTOS.org/FAQHelp.html                               *\r
  52      *                                                                       *\r
  53     ***************************************************************************\r
  54 \r
  55 \r
  56     http://www.FreeRTOS.org - Documentation, training, latest versions, license\r
  57     and contact details.\r
  58 \r
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  61 \r
  62     Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell\r
  63     the code with commercial support, indemnification, and middleware, under\r
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  66     the SafeRTOS brand: http://www.SafeRTOS.com.\r
  67 */\r
  68 \r
  69 /*-----------------------------------------------------------\r
  70  * Implementation of functions defined in portable.h for the ARM CM3 port.\r
  71  *----------------------------------------------------------*/\r
  72 \r
  73 /* Scheduler includes. */\r
  74 #include "FreeRTOS.h"\r
  75 #include "task.h"\r
  76 \r
  77 /* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is\r
  78 defined.  The value should also ensure backward compatibility.\r
  79 FreeRTOS.org versions prior to V4.4.0 did not include this definition. */\r
  80 #ifndef configKERNEL_INTERRUPT_PRIORITY\r
  81         #define configKERNEL_INTERRUPT_PRIORITY 255\r
  82 #endif\r
  83 \r
  84 #ifndef configSYSTICK_CLOCK_HZ\r
  85         #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ\r
  86 #endif\r
  87 \r
  88 /* Constants required to manipulate the core.  Registers first... */\r
  89 #define portNVIC_SYSTICK_CTRL_REG                       ( * ( ( volatile unsigned long * ) 0xe000e010 ) )\r
  90 #define portNVIC_SYSTICK_LOAD_REG                       ( * ( ( volatile unsigned long * ) 0xe000e014 ) )\r
  91 #define portNVIC_SYSTICK_CURRENT_VALUE_REG      ( * ( ( volatile unsigned long * ) 0xe000e018 ) )\r
  92 #define portNVIC_INT_CTRL_REG                           ( * ( ( volatile unsigned long * ) 0xe000ed04 ) )\r
  93 #define portNVIC_SYSPRI2_REG                            ( * ( ( volatile unsigned long * ) 0xe000ed20 ) )\r
  94 /* ...then bits in the registers. */\r
  95 #define portNVIC_SYSTICK_CLK_BIT                        ( 1UL << 2UL )\r
  96 #define portNVIC_SYSTICK_INT_BIT                        ( 1UL << 1UL )\r
  97 #define portNVIC_SYSTICK_ENABLE_BIT                     ( 1UL << 0UL )\r
  98 #define portNVIC_SYSTICK_COUNT_FLAG_BIT         ( 1UL << 16UL )\r
  99 #define portNVIC_PENDSVSET_BIT                          ( 1UL << 28UL )\r
 100 #define portNVIC_PENDSVCLEAR_BIT                        ( 1UL << 27UL )\r
 101 #define portNVIC_PEND_SYSTICK_CLEAR_BIT         ( 1UL << 25UL )\r
 102 \r
 103 #define portNVIC_PENDSV_PRI                             ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
 104 #define portNVIC_SYSTICK_PRI                    ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
 105 \r
 106 /* Constants required to set up the initial stack. */\r
 107 #define portINITIAL_XPSR                        ( 0x01000000 )\r
 108 \r
 109 /* The priority used by the kernel is assigned to a variable to make access\r
 110 from inline assembler easier. */\r
 111 const unsigned long ulKernelPriority = configKERNEL_INTERRUPT_PRIORITY;\r
 112 \r
 113 /* Each task maintains its own interrupt status in the critical nesting\r
 114 variable. */\r
 115 static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;\r
 116 \r
 117 /*\r
 118  * Setup the timer to generate the tick interrupts.  The implementation in this\r
 119  * file is weak to allow application writers to change the timer used to\r
 120  * generate the tick interrupt.\r
 121  */\r
 122 void vPortSetupTimerInterrupt( void );\r
 123 \r
 124 /*\r
 125  * Exception handlers.\r
 126  */\r
 127 void xPortPendSVHandler( void ) __attribute__ (( naked ));\r
 128 void xPortSysTickHandler( void );\r
 129 void vPortSVCHandler( void ) __attribute__ (( naked ));\r
 130 \r
 131 /*\r
 132  * Start first task is a separate function so it can be tested in isolation.\r
 133  */\r
 134 static void prvPortStartFirstTask( void ) __attribute__ (( naked ));\r
 135 \r
 136 /*-----------------------------------------------------------*/\r
 137 \r
 138 /*\r
 139  * The number of SysTick increments that make up one tick period.\r
 140  */\r
 141 #if configUSE_TICKLESS_IDLE == 1\r
 142         static unsigned long ulTimerReloadValueForOneTick = 0;\r
 143 #endif\r
 144 \r
 145 /*\r
 146  * The maximum number of tick periods that can be suppressed is limited by the\r
 147  * 24 bit resolution of the SysTick timer.\r
 148  */\r
 149 #if configUSE_TICKLESS_IDLE == 1\r
 150         static unsigned long xMaximumPossibleSuppressedTicks = 0;\r
 151 #endif /* configUSE_TICKLESS_IDLE */\r
 152 \r
 153 /*\r
 154  * Compensate for the CPU cycles that pass while the SysTick is stopped (low\r
 155  * power functionality only.\r
 156  */\r
 157 #if configUSE_TICKLESS_IDLE == 1\r
 158         static unsigned long ulStoppedTimerCompensation = 0;\r
 159 #endif /* configUSE_TICKLESS_IDLE */\r
 160 \r
 161 /*-----------------------------------------------------------*/\r
 162 \r
 163 /*\r
 164  * See header file for description.\r
 165  */\r
 166 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
 167 {\r
 168         /* Simulate the stack frame as it would be created by a context switch\r
 169         interrupt. */\r
 170         pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
 171         *pxTopOfStack = portINITIAL_XPSR;       /* xPSR */\r
 172         pxTopOfStack--;\r
 173         *pxTopOfStack = ( portSTACK_TYPE ) pxCode;      /* PC */\r
 174         pxTopOfStack--;\r
 175         *pxTopOfStack = 0;      /* LR */\r
 176         pxTopOfStack -= 5;      /* R12, R3, R2 and R1. */\r
 177         *pxTopOfStack = ( portSTACK_TYPE ) pvParameters;        /* R0 */\r
 178         pxTopOfStack -= 8;      /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
 179 \r
 180         return pxTopOfStack;\r
 181 }\r
 182 /*-----------------------------------------------------------*/\r
 183 \r
 184 void vPortSVCHandler( void )\r
 185 {\r
 186         __asm volatile (\r
 187                                         "       ldr     r3, pxCurrentTCBConst2          \n" /* Restore the context. */\r
 188                                         "       ldr r1, [r3]                                    \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */\r
 189                                         "       ldr r0, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
 190                                         "       ldmia r0!, {r4-r11}                             \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */\r
 191                                         "       msr psp, r0                                             \n" /* Restore the task stack pointer. */\r
 192                                         "       mov r0, #0                                              \n"\r
 193                                         "       msr     basepri, r0                                     \n"\r
 194                                         "       orr r14, #0xd                                   \n"\r
 195                                         "       bx r14                                                  \n"\r
 196                                         "                                                                       \n"\r
 197                                         "       .align 2                                                \n"\r
 198                                         "pxCurrentTCBConst2: .word pxCurrentTCB                         \n"\r
 199                                 );\r
 200 }\r
 201 /*-----------------------------------------------------------*/\r
 202 \r
 203 static void prvPortStartFirstTask( void )\r
 204 {\r
 205         __asm volatile(\r
 206                                         " ldr r0, =0xE000ED08   \n" /* Use the NVIC offset register to locate the stack. */\r
 207                                         " ldr r0, [r0]                  \n"\r
 208                                         " ldr r0, [r0]                  \n"\r
 209                                         " msr msp, r0                   \n" /* Set the msp back to the start of the stack. */\r
 210                                         " cpsie i                               \n" /* Globally enable interrupts. */\r
 211                                         " svc 0                                 \n" /* System call to start first task. */\r
 212                                         " nop                                   \n"\r
 213                                 );\r
 214 }\r
 215 /*-----------------------------------------------------------*/\r
 216 \r
 217 /*\r
 218  * See header file for description.\r
 219  */\r
 220 portBASE_TYPE xPortStartScheduler( void )\r
 221 {\r
 222         /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.\r
 223         See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\r
 224         configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );\r
 225 \r
 226         /* Make PendSV, CallSV and SysTick the same priroity as the kernel. */\r
 227         portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;\r
 228         portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;\r
 229 \r
 230         /* Start the timer that generates the tick ISR.  Interrupts are disabled\r
 231         here already. */\r
 232         vPortSetupTimerInterrupt();\r
 233 \r
 234         /* Initialise the critical nesting count ready for the first task. */\r
 235         uxCriticalNesting = 0;\r
 236 \r
 237         /* Start the first task. */\r
 238         prvPortStartFirstTask();\r
 239 \r
 240         /* Should not get here! */\r
 241         return 0;\r
 242 }\r
 243 /*-----------------------------------------------------------*/\r
 244 \r
 245 void vPortEndScheduler( void )\r
 246 {\r
 247         /* It is unlikely that the CM3 port will require this function as there\r
 248         is nothing to return to.  */\r
 249 }\r
 250 /*-----------------------------------------------------------*/\r
 251 \r
 252 void vPortYieldFromISR( void )\r
 253 {\r
 254         /* Set a PendSV to request a context switch. */\r
 255         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 256 }\r
 257 /*-----------------------------------------------------------*/\r
 258 \r
 259 void vPortEnterCritical( void )\r
 260 {\r
 261         portDISABLE_INTERRUPTS();\r
 262         uxCriticalNesting++;\r
 263 }\r
 264 /*-----------------------------------------------------------*/\r
 265 \r
 266 void vPortExitCritical( void )\r
 267 {\r
 268         uxCriticalNesting--;\r
 269         if( uxCriticalNesting == 0 )\r
 270         {\r
 271                 portENABLE_INTERRUPTS();\r
 272         }\r
 273 }\r
 274 /*-----------------------------------------------------------*/\r
 275 \r
 276 __attribute__(( naked )) unsigned long ulPortSetInterruptMask( void )\r
 277 {\r
 278         __asm volatile                                                                                                          \\r
 279         (                                                                                                                                       \\r
 280                 "       mrs r0, basepri                                                                                 \n" \\r
 281                 "       mov r1, %0                                                                                              \n"     \\r
 282                 "       msr basepri, r1                                                                                 \n" \\r
 283                 "       bx lr                                                                                                   \n" \\r
 284                 :: "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "r0", "r1"    \\r
 285         );\r
 286 \r
 287         /* This return will not be reached but is necessary to prevent compiler\r
 288         warnings. */\r
 289         return 0;\r
 290 }\r
 291 /*-----------------------------------------------------------*/\r
 292 \r
 293 __attribute__(( naked )) void vPortClearInterruptMask( unsigned long ulNewMaskValue )\r
 294 {\r
 295         __asm volatile                                                                                                  \\r
 296         (                                                                                                                               \\r
 297                 "       msr basepri, r0                                                                         \n"     \\r
 298                 "       bx lr                                                                                           \n" \\r
 299                 :::"r0"                                                                                                         \\r
 300         );\r
 301 \r
 302         /* Just to avoid compiler warnings. */\r
 303         ( void ) ulNewMaskValue;\r
 304 }\r
 305 /*-----------------------------------------------------------*/\r
 306 \r
 307 void xPortPendSVHandler( void )\r
 308 {\r
 309         /* This is a naked function. */\r
 310 \r
 311         __asm volatile\r
 312         (\r
 313         "       mrs r0, psp                                                     \n"\r
 314         "                                                                               \n"\r
 315         "       ldr     r3, pxCurrentTCBConst                   \n" /* Get the location of the current TCB. */\r
 316         "       ldr     r2, [r3]                                                \n"\r
 317         "                                                                               \n"\r
 318         "       stmdb r0!, {r4-r11}                                     \n" /* Save the remaining registers. */\r
 319         "       str r0, [r2]                                            \n" /* Save the new top of stack into the first member of the TCB. */\r
 320         "                                                                               \n"\r
 321         "       stmdb sp!, {r3, r14}                            \n"\r
 322         "       mov r0, %0                                                      \n"\r
 323         "       msr basepri, r0                                         \n"\r
 324         "       bl vTaskSwitchContext                           \n"\r
 325         "       mov r0, #0                                                      \n"\r
 326         "       msr basepri, r0                                         \n"\r
 327         "       ldmia sp!, {r3, r14}                            \n"\r
 328         "                                                                               \n"     /* Restore the context, including the critical nesting count. */\r
 329         "       ldr r1, [r3]                                            \n"\r
 330         "       ldr r0, [r1]                                            \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
 331         "       ldmia r0!, {r4-r11}                                     \n" /* Pop the registers. */\r
 332         "       msr psp, r0                                                     \n"\r
 333         "       bx r14                                                          \n"\r
 334         "                                                                               \n"\r
 335         "       .align 2                                                        \n"\r
 336         "pxCurrentTCBConst: .word pxCurrentTCB  \n"\r
 337         ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)\r
 338         );\r
 339 }\r
 340 /*-----------------------------------------------------------*/\r
 341 \r
 342 void xPortSysTickHandler( void )\r
 343 {\r
 344         /* If using preemption, also force a context switch. */\r
 345         #if configUSE_PREEMPTION == 1\r
 346                 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 347         #endif\r
 348 \r
 349         /* Only reset the systick load register if configUSE_TICKLESS_IDLE is set to\r
 350         1.  If it is set to 0 tickless idle is not being used.  If it is set to a\r
 351         value other than 0 or 1 then a timer other than the SysTick is being used\r
 352         to generate the tick interrupt. */\r
 353         #if configUSE_TICKLESS_IDLE == 1\r
 354                 portNVIC_SYSTICK_LOAD_REG = ulTimerReloadValueForOneTick;\r
 355         #endif\r
 356 \r
 357         ( void ) portSET_INTERRUPT_MASK_FROM_ISR();\r
 358         {\r
 359                 vTaskIncrementTick();\r
 360         }\r
 361         portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );\r
 362 }\r
 363 /*-----------------------------------------------------------*/\r
 364 \r
 365 #if configUSE_TICKLESS_IDLE == 1\r
 366 \r
 367         __attribute__((weak)) void vPortSuppressTicksAndSleep( portTickType xExpectedIdleTime )\r
 368         {\r
 369         unsigned long ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickIncrements;\r
 370         portTickType xModifiableIdleTime;\r
 371 \r
 372                 /* Make sure the SysTick reload value does not overflow the counter. */\r
 373                 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\r
 374                 {\r
 375                         xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\r
 376                 }\r
 377 \r
 378                 /* Calculate the reload value required to wait xExpectedIdleTime\r
 379                 tick periods.  -1 is used because this code will execute part way\r
 380                 through one of the tick periods, and the fraction of a tick period is\r
 381                 accounted for later. */\r
 382                 ulReloadValue = ( ulTimerReloadValueForOneTick * ( xExpectedIdleTime - 1UL ) );\r
 383                 if( ulReloadValue > ulStoppedTimerCompensation )\r
 384                 {\r
 385                         ulReloadValue -= ulStoppedTimerCompensation;\r
 386                 }\r
 387 \r
 388                 /* Stop the SysTick momentarily.  The time the SysTick is stopped for\r
 389                 is accounted for as best it can be, but using the tickless mode will\r
 390                 inevitably result in some tiny drift of the time maintained by the\r
 391                 kernel with respect to calendar time. */\r
 392                 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\r
 393 \r
 394                 /* If a context switch is pending then abandon the low power entry as\r
 395                 the context switch might have been pended by an external interrupt that\r
 396                 requires processing. */\r
 397                 if( ( portNVIC_INT_CTRL_REG & portNVIC_PENDSVSET_BIT ) != 0 )\r
 398                 {\r
 399                         /* Restart SysTick. */\r
 400                         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 401                 }\r
 402                 else\r
 403                 {\r
 404                         /* Adjust the reload value to take into account that the current\r
 405                         time slice is already partially complete. */\r
 406                         ulReloadValue += ( portNVIC_SYSTICK_LOAD_REG - ( portNVIC_SYSTICK_LOAD_REG - portNVIC_SYSTICK_CURRENT_VALUE_REG ) );\r
 407                         portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\r
 408 \r
 409                         /* Clear the SysTick count flag and set the count value back to\r
 410                         zero. */\r
 411                         portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
 412 \r
 413                         /* Restart SysTick. */\r
 414                         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 415 \r
 416                         /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can\r
 417                         set its parameter to 0 to indicate that its implementation contains\r
 418                         its own wait for interrupt or wait for event instruction, and so wfi\r
 419                         should not be executed again.  However, the original expected idle\r
 420                         time variable must remain unmodified, so a copy is taken. */\r
 421                         xModifiableIdleTime = xExpectedIdleTime;\r
 422                         configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\r
 423                         if( xModifiableIdleTime > 0 )\r
 424                         {\r
 425                                 __asm volatile( "wfi" );\r
 426                         }\r
 427                         configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\r
 428 \r
 429                         /* Stop SysTick.  Again, the time the SysTick is stopped for is\r
 430                         accounted for as best it can be, but using the tickless mode will\r
 431                         inevitably result in some tiny drift of the time maintained by the\r
 432                         kernel with respect to calendar time. */\r
 433                         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\r
 434 \r
 435                         if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\r
 436                         {\r
 437                                 /* The tick interrupt has already executed, and the SysTick\r
 438                                 count reloaded with the portNVIC_SYSTICK_LOAD_REG value.\r
 439                                 Reset the portNVIC_SYSTICK_LOAD_REG with whatever remains of\r
 440                                 this tick period. */\r
 441                                 portNVIC_SYSTICK_LOAD_REG = ulTimerReloadValueForOneTick - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\r
 442 \r
 443                                 /* The tick interrupt handler will already have pended the tick\r
 444                                 processing in the kernel.  As the pending tick will be\r
 445                                 processed as soon as this function exits, the tick value\r
 446                                 maintained by the tick is stepped forward by one less than the\r
 447                                 time spent waiting. */\r
 448                                 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\r
 449                         }\r
 450                         else\r
 451                         {\r
 452                                 /* Something other than the tick interrupt ended the sleep.\r
 453                                 Work out how long the sleep lasted. */\r
 454                                 ulCompletedSysTickIncrements = ( xExpectedIdleTime * ulTimerReloadValueForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;\r
 455 \r
 456                                 /* How many complete tick periods passed while the processor\r
 457                                 was waiting? */\r
 458                                 ulCompleteTickPeriods = ulCompletedSysTickIncrements / ulTimerReloadValueForOneTick;\r
 459 \r
 460                                 /* The reload value is set to whatever fraction of a single tick\r
 461                                 period remains. */\r
 462                                 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1 ) * ulTimerReloadValueForOneTick ) - ulCompletedSysTickIncrements;\r
 463                         }\r
 464 \r
 465                         /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG\r
 466                         again, then set portNVIC_SYSTICK_LOAD_REG back to its standard\r
 467                         value. */\r
 468                         portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
 469                         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 470 \r
 471                         vTaskStepTick( ulCompleteTickPeriods );\r
 472                 }\r
 473         }\r
 474 \r
 475 #endif /* #if configUSE_TICKLESS_IDLE */\r
 476 /*-----------------------------------------------------------*/\r
 477 \r
 478 /*\r
 479  * Setup the systick timer to generate the tick interrupts at the required\r
 480  * frequency.\r
 481  */\r
 482 __attribute__(( weak )) void vPortSetupTimerInterrupt( void )\r
 483 {\r
 484         /* Calculate the constants required to configure the tick interrupt. */\r
 485         #if configUSE_TICKLESS_IDLE == 1\r
 486         {\r
 487                 ulTimerReloadValueForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
 488                 xMaximumPossibleSuppressedTicks = 0xffffffUL / ( ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL );\r
 489                 ulStoppedTimerCompensation = 45UL / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\r
 490         }\r
 491         #endif /* configUSE_TICKLESS_IDLE */\r
 492 \r
 493         /* Configure SysTick to interrupt at the requested rate. */\r
 494         portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;;\r
 495         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 496 }\r
 497 /*-----------------------------------------------------------*/\r
 498 \r