git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/ARM_CM3/port.c

   1 /*\r
   2     FreeRTOS V8.0.0 - Copyright (C) 2014 Real Time Engineers Ltd.\r
   3     All rights reserved\r
   4 \r
   5     VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
   6 \r
   7     ***************************************************************************\r
   8      *                                                                       *\r
   9      *    FreeRTOS provides completely free yet professionally developed,    *\r
  10      *    robust, strictly quality controlled, supported, and cross          *\r
  11      *    platform software that has become a de facto standard.             *\r
  12      *                                                                       *\r
  13      *    Help yourself get started quickly and support the FreeRTOS         *\r
  14      *    project by purchasing a FreeRTOS tutorial book, reference          *\r
  15      *    manual, or both from: http://www.FreeRTOS.org/Documentation        *\r
  16      *                                                                       *\r
  17      *    Thank you!                                                         *\r
  18      *                                                                       *\r
  19     ***************************************************************************\r
  20 \r
  21     This file is part of the FreeRTOS distribution.\r
  22 \r
  23     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  24     the terms of the GNU General Public License (version 2) as published by the\r
  25     Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
  26 \r
  27     >>! NOTE: The modification to the GPL is included to allow you to distribute\r
  28     >>! a combined work that includes FreeRTOS without being obliged to provide\r
  29     >>! the source code for proprietary components outside of the FreeRTOS\r
  30     >>! kernel.\r
  31 \r
  32     FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
  33     WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
  34     FOR A PARTICULAR PURPOSE.  Full license text is available from the following\r
  35     link: http://www.freertos.org/a00114.html\r
  36 \r
  37     1 tab == 4 spaces!\r
  38 \r
  39     ***************************************************************************\r
  40      *                                                                       *\r
  41      *    Having a problem?  Start by reading the FAQ "My application does   *\r
  42      *    not run, what could be wrong?"                                     *\r
  43      *                                                                       *\r
  44      *    http://www.FreeRTOS.org/FAQHelp.html                               *\r
  45      *                                                                       *\r
  46     ***************************************************************************\r
  47 \r
  48     http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
  49     license and Real Time Engineers Ltd. contact details.\r
  50 \r
  51     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
  52     including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
  53     compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
  54 \r
  55     http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
  56     Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS\r
  57     licenses offer ticketed support, indemnification and middleware.\r
  58 \r
  59     http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
  60     engineered and independently SIL3 certified version for use in safety and\r
  61     mission critical applications that require provable dependability.\r
  62 \r
  63     1 tab == 4 spaces!\r
  64 */\r
  65 \r
  66 /*-----------------------------------------------------------\r
  67  * Implementation of functions defined in portable.h for the ARM CM3 port.\r
  68  *----------------------------------------------------------*/\r
  69 \r
  70 /* Scheduler includes. */\r
  71 #include "FreeRTOS.h"\r
  72 #include "task.h"\r
  73 \r
  74 /* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is\r
  75 defined.  The value should also ensure backward compatibility.\r
  76 FreeRTOS.org versions prior to V4.4.0 did not include this definition. */\r
  77 #ifndef configKERNEL_INTERRUPT_PRIORITY\r
  78         #define configKERNEL_INTERRUPT_PRIORITY 255\r
  79 #endif\r
  80 \r
  81 #ifndef configSYSTICK_CLOCK_HZ\r
  82         #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ\r
  83         /* Ensure the SysTick is clocked at the same frequency as the core. */\r
  84         #define portNVIC_SYSTICK_CLK_BIT        ( 1UL << 2UL )\r
  85 #else\r
  86         /* The way the SysTick is clocked is not modified in case it is not the same\r
  87         as the core. */\r
  88         #define portNVIC_SYSTICK_CLK_BIT        ( 0 )\r
  89 #endif\r
  90 \r
  91 /* Constants required to manipulate the core.  Registers first... */\r
  92 #define portNVIC_SYSTICK_CTRL_REG                       ( * ( ( volatile uint32_t * ) 0xe000e010 ) )\r
  93 #define portNVIC_SYSTICK_LOAD_REG                       ( * ( ( volatile uint32_t * ) 0xe000e014 ) )\r
  94 #define portNVIC_SYSTICK_CURRENT_VALUE_REG      ( * ( ( volatile uint32_t * ) 0xe000e018 ) )\r
  95 #define portNVIC_SYSPRI2_REG                            ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )\r
  96 /* ...then bits in the registers. */\r
  97 #define portNVIC_SYSTICK_INT_BIT                        ( 1UL << 1UL )\r
  98 #define portNVIC_SYSTICK_ENABLE_BIT                     ( 1UL << 0UL )\r
  99 #define portNVIC_SYSTICK_COUNT_FLAG_BIT         ( 1UL << 16UL )\r
 100 #define portNVIC_PENDSVCLEAR_BIT                        ( 1UL << 27UL )\r
 101 #define portNVIC_PEND_SYSTICK_CLEAR_BIT         ( 1UL << 25UL )\r
 102 \r
 103 #define portNVIC_PENDSV_PRI                                     ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
 104 #define portNVIC_SYSTICK_PRI                            ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
 105 \r
 106 /* Constants required to check the validity of an interrupt priority. */\r
 107 #define portFIRST_USER_INTERRUPT_NUMBER         ( 16 )\r
 108 #define portNVIC_IP_REGISTERS_OFFSET_16         ( 0xE000E3F0 )\r
 109 #define portAIRCR_REG                                           ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )\r
 110 #define portMAX_8_BIT_VALUE                                     ( ( uint8_t ) 0xff )\r
 111 #define portTOP_BIT_OF_BYTE                                     ( ( uint8_t ) 0x80 )\r
 112 #define portMAX_PRIGROUP_BITS                           ( ( uint8_t ) 7 )\r
 113 #define portPRIORITY_GROUP_MASK                         ( 0x07UL << 8UL )\r
 114 #define portPRIGROUP_SHIFT                                      ( 8UL )\r
 115 \r
 116 /* Constants required to set up the initial stack. */\r
 117 #define portINITIAL_XPSR                                        ( 0x01000000UL )\r
 118 \r
 119 /* The systick is a 24-bit counter. */\r
 120 #define portMAX_24_BIT_NUMBER                           ( 0xffffffUL )\r
 121 \r
 122 /* A fiddle factor to estimate the number of SysTick counts that would have\r
 123 occurred while the SysTick counter is stopped during tickless idle\r
 124 calculations. */\r
 125 #define portMISSED_COUNTS_FACTOR                        ( 45UL )\r
 126 \r
 127 /* Let the user override the pre-loading of the initial LR with the address of\r
 128 prvTaskExitError() in case is messes up unwinding of the stack in the\r
 129 debugger. */\r
 130 #ifdef configTASK_RETURN_ADDRESS\r
 131         #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS\r
 132 #else\r
 133         #define portTASK_RETURN_ADDRESS prvTaskExitError\r
 134 #endif\r
 135 \r
 136 /* Each task maintains its own interrupt status in the critical nesting\r
 137 variable. */\r
 138 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\r
 139 \r
 140 /*\r
 141  * Setup the timer to generate the tick interrupts.  The implementation in this\r
 142  * file is weak to allow application writers to change the timer used to\r
 143  * generate the tick interrupt.\r
 144  */\r
 145 void vPortSetupTimerInterrupt( void );\r
 146 \r
 147 /*\r
 148  * Exception handlers.\r
 149  */\r
 150 void xPortPendSVHandler( void ) __attribute__ (( naked ));\r
 151 void xPortSysTickHandler( void );\r
 152 void vPortSVCHandler( void ) __attribute__ (( naked ));\r
 153 \r
 154 /*\r
 155  * Start first task is a separate function so it can be tested in isolation.\r
 156  */\r
 157 static void prvPortStartFirstTask( void ) __attribute__ (( naked ));\r
 158 \r
 159 /*\r
 160  * Used to catch tasks that attempt to return from their implementing function.\r
 161  */\r
 162 static void prvTaskExitError( void );\r
 163 \r
 164 /*-----------------------------------------------------------*/\r
 165 \r
 166 /*\r
 167  * The number of SysTick increments that make up one tick period.\r
 168  */\r
 169 #if configUSE_TICKLESS_IDLE == 1\r
 170         static uint32_t ulTimerCountsForOneTick = 0;\r
 171 #endif /* configUSE_TICKLESS_IDLE */\r
 172 \r
 173 /*\r
 174  * The maximum number of tick periods that can be suppressed is limited by the\r
 175  * 24 bit resolution of the SysTick timer.\r
 176  */\r
 177 #if configUSE_TICKLESS_IDLE == 1\r
 178         static uint32_t xMaximumPossibleSuppressedTicks = 0;\r
 179 #endif /* configUSE_TICKLESS_IDLE */\r
 180 \r
 181 /*\r
 182  * Compensate for the CPU cycles that pass while the SysTick is stopped (low\r
 183  * power functionality only.\r
 184  */\r
 185 #if configUSE_TICKLESS_IDLE == 1\r
 186         static uint32_t ulStoppedTimerCompensation = 0;\r
 187 #endif /* configUSE_TICKLESS_IDLE */\r
 188 \r
 189 /*\r
 190  * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure\r
 191  * FreeRTOS API functions are not called from interrupts that have been assigned\r
 192  * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 193  */\r
 194 #if ( configASSERT_DEFINED == 1 )\r
 195          static uint8_t ucMaxSysCallPriority = 0;\r
 196          static uint32_t ulMaxPRIGROUPValue = 0;\r
 197          static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;\r
 198 #endif /* configASSERT_DEFINED */\r
 199 \r
 200 /*-----------------------------------------------------------*/\r
 201 \r
 202 /*\r
 203  * See header file for description.\r
 204  */\r
 205 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )\r
 206 {\r
 207         /* Simulate the stack frame as it would be created by a context switch\r
 208         interrupt. */\r
 209         pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
 210         *pxTopOfStack = portINITIAL_XPSR;       /* xPSR */\r
 211         pxTopOfStack--;\r
 212         *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
 213         pxTopOfStack--;\r
 214         *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;        /* LR */\r
 215         pxTopOfStack -= 5;      /* R12, R3, R2 and R1. */\r
 216         *pxTopOfStack = ( StackType_t ) pvParameters;   /* R0 */\r
 217         pxTopOfStack -= 8;      /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
 218 \r
 219         return pxTopOfStack;\r
 220 }\r
 221 /*-----------------------------------------------------------*/\r
 222 \r
 223 static void prvTaskExitError( void )\r
 224 {\r
 225         /* A function that implements a task must not exit or attempt to return to\r
 226         its caller as there is nothing to return to.  If a task wants to exit it\r
 227         should instead call vTaskDelete( NULL ).\r
 228 \r
 229         Artificially force an assert() to be triggered if configASSERT() is\r
 230         defined, then stop here so application writers can catch the error. */\r
 231         configASSERT( uxCriticalNesting == ~0UL );\r
 232         portDISABLE_INTERRUPTS();\r
 233         for( ;; );\r
 234 }\r
 235 /*-----------------------------------------------------------*/\r
 236 \r
 237 void vPortSVCHandler( void )\r
 238 {\r
 239         __asm volatile (\r
 240                                         "       ldr     r3, pxCurrentTCBConst2          \n" /* Restore the context. */\r
 241                                         "       ldr r1, [r3]                                    \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */\r
 242                                         "       ldr r0, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
 243                                         "       ldmia r0!, {r4-r11}                             \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */\r
 244                                         "       msr psp, r0                                             \n" /* Restore the task stack pointer. */\r
 245                                         "       isb                                                             \n"\r
 246                                         "       mov r0, #0                                              \n"\r
 247                                         "       msr     basepri, r0                                     \n"\r
 248                                         "       orr r14, #0xd                                   \n"\r
 249                                         "       bx r14                                                  \n"\r
 250                                         "                                                                       \n"\r
 251                                         "       .align 2                                                \n"\r
 252                                         "pxCurrentTCBConst2: .word pxCurrentTCB                         \n"\r
 253                                 );\r
 254 }\r
 255 /*-----------------------------------------------------------*/\r
 256 \r
 257 static void prvPortStartFirstTask( void )\r
 258 {\r
 259         __asm volatile(\r
 260                                         " ldr r0, =0xE000ED08   \n" /* Use the NVIC offset register to locate the stack. */\r
 261                                         " ldr r0, [r0]                  \n"\r
 262                                         " ldr r0, [r0]                  \n"\r
 263                                         " msr msp, r0                   \n" /* Set the msp back to the start of the stack. */\r
 264                                         " cpsie i                               \n" /* Globally enable interrupts. */\r
 265                                         " dsb                                   \n"\r
 266                                         " isb                                   \n"\r
 267                                         " svc 0                                 \n" /* System call to start first task. */\r
 268                                         " nop                                   \n"\r
 269                                 );\r
 270 }\r
 271 /*-----------------------------------------------------------*/\r
 272 \r
 273 /*\r
 274  * See header file for description.\r
 275  */\r
 276 BaseType_t xPortStartScheduler( void )\r
 277 {\r
 278         /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.\r
 279         See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\r
 280         configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );\r
 281 \r
 282         #if( configASSERT_DEFINED == 1 )\r
 283         {\r
 284                 volatile uint32_t ulOriginalPriority;\r
 285                 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r
 286                 volatile uint8_t ucMaxPriorityValue;\r
 287 \r
 288                 /* Determine the maximum priority from which ISR safe FreeRTOS API\r
 289                 functions can be called.  ISR safe functions are those that end in\r
 290                 "FromISR".  FreeRTOS maintains separate thread and ISR API functions to\r
 291                 ensure interrupt entry is as fast and simple as possible.\r
 292 \r
 293                 Save the interrupt priority value that is about to be clobbered. */\r
 294                 ulOriginalPriority = *pucFirstUserPriorityRegister;\r
 295 \r
 296                 /* Determine the number of priority bits available.  First write to all\r
 297                 possible bits. */\r
 298                 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\r
 299 \r
 300                 /* Read the value back to see how many bits stuck. */\r
 301                 ucMaxPriorityValue = *pucFirstUserPriorityRegister;\r
 302 \r
 303                 /* Use the same mask on the maximum system call priority. */\r
 304                 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\r
 305 \r
 306                 /* Calculate the maximum acceptable priority group value for the number\r
 307                 of bits read back. */\r
 308                 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;\r
 309                 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\r
 310                 {\r
 311                         ulMaxPRIGROUPValue--;\r
 312                         ucMaxPriorityValue <<= ( uint8_t ) 0x01;\r
 313                 }\r
 314 \r
 315                 /* Shift the priority group value back to its position within the AIRCR\r
 316                 register. */\r
 317                 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\r
 318                 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;\r
 319 \r
 320                 /* Restore the clobbered interrupt priority register to its original\r
 321                 value. */\r
 322                 *pucFirstUserPriorityRegister = ulOriginalPriority;\r
 323         }\r
 324         #endif /* conifgASSERT_DEFINED */\r
 325 \r
 326         /* Make PendSV and SysTick the lowest priority interrupts. */\r
 327         portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;\r
 328         portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;\r
 329 \r
 330         /* Start the timer that generates the tick ISR.  Interrupts are disabled\r
 331         here already. */\r
 332         vPortSetupTimerInterrupt();\r
 333 \r
 334         /* Initialise the critical nesting count ready for the first task. */\r
 335         uxCriticalNesting = 0;\r
 336 \r
 337         /* Start the first task. */\r
 338         prvPortStartFirstTask();\r
 339 \r
 340         /* Should never get here as the tasks will now be executing!  Call the task\r
 341         exit error function to prevent compiler warnings about a static function\r
 342         not being called in the case that the application writer overrides this\r
 343         functionality by defining configTASK_RETURN_ADDRESS. */\r
 344         prvTaskExitError();\r
 345 \r
 346         /* Should not get here! */\r
 347         return 0;\r
 348 }\r
 349 /*-----------------------------------------------------------*/\r
 350 \r
 351 void vPortEndScheduler( void )\r
 352 {\r
 353         /* Not implemented in ports where there is nothing to return to.\r
 354         Artificially force an assert. */\r
 355         configASSERT( uxCriticalNesting == 1000UL );\r
 356 }\r
 357 /*-----------------------------------------------------------*/\r
 358 \r
 359 void vPortYield( void )\r
 360 {\r
 361         /* Set a PendSV to request a context switch. */\r
 362         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 363 \r
 364         /* Barriers are normally not required but do ensure the code is completely\r
 365         within the specified behaviour for the architecture. */\r
 366         __asm volatile( "dsb" );\r
 367         __asm volatile( "isb" );\r
 368 }\r
 369 /*-----------------------------------------------------------*/\r
 370 \r
 371 void vPortEnterCritical( void )\r
 372 {\r
 373         portDISABLE_INTERRUPTS();\r
 374         uxCriticalNesting++;\r
 375         __asm volatile( "dsb" );\r
 376         __asm volatile( "isb" );\r
 377 }\r
 378 /*-----------------------------------------------------------*/\r
 379 \r
 380 void vPortExitCritical( void )\r
 381 {\r
 382         configASSERT( uxCriticalNesting );\r
 383         uxCriticalNesting--;\r
 384         if( uxCriticalNesting == 0 )\r
 385         {\r
 386                 portENABLE_INTERRUPTS();\r
 387         }\r
 388 }\r
 389 /*-----------------------------------------------------------*/\r
 390 \r
 391 __attribute__(( naked )) uint32_t ulPortSetInterruptMask( void )\r
 392 {\r
 393         __asm volatile                                                                                                          \\r
 394         (                                                                                                                                       \\r
 395                 "       mrs r0, basepri                                                                                 \n" \\r
 396                 "       mov r1, %0                                                                                              \n"     \\r
 397                 "       msr basepri, r1                                                                                 \n" \\r
 398                 "       bx lr                                                                                                   \n" \\r
 399                 :: "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "r0", "r1"    \\r
 400         );\r
 401 \r
 402         /* This return will not be reached but is necessary to prevent compiler\r
 403         warnings. */\r
 404         return 0;\r
 405 }\r
 406 /*-----------------------------------------------------------*/\r
 407 \r
 408 __attribute__(( naked )) void vPortClearInterruptMask( uint32_t ulNewMaskValue )\r
 409 {\r
 410         __asm volatile                                                                                                  \\r
 411         (                                                                                                                               \\r
 412                 "       msr basepri, r0                                                                         \n"     \\r
 413                 "       bx lr                                                                                           \n" \\r
 414                 :::"r0"                                                                                                         \\r
 415         );\r
 416 \r
 417         /* Just to avoid compiler warnings. */\r
 418         ( void ) ulNewMaskValue;\r
 419 }\r
 420 /*-----------------------------------------------------------*/\r
 421 \r
 422 void xPortPendSVHandler( void )\r
 423 {\r
 424         /* This is a naked function. */\r
 425 \r
 426         __asm volatile\r
 427         (\r
 428         "       mrs r0, psp                                                     \n"\r
 429         "       isb                                                                     \n"\r
 430         "                                                                               \n"\r
 431         "       ldr     r3, pxCurrentTCBConst                   \n" /* Get the location of the current TCB. */\r
 432         "       ldr     r2, [r3]                                                \n"\r
 433         "                                                                               \n"\r
 434         "       stmdb r0!, {r4-r11}                                     \n" /* Save the remaining registers. */\r
 435         "       str r0, [r2]                                            \n" /* Save the new top of stack into the first member of the TCB. */\r
 436         "                                                                               \n"\r
 437         "       stmdb sp!, {r3, r14}                            \n"\r
 438         "       mov r0, %0                                                      \n"\r
 439         "       msr basepri, r0                                         \n"\r
 440         "       bl vTaskSwitchContext                           \n"\r
 441         "       mov r0, #0                                                      \n"\r
 442         "       msr basepri, r0                                         \n"\r
 443         "       ldmia sp!, {r3, r14}                            \n"\r
 444         "                                                                               \n"     /* Restore the context, including the critical nesting count. */\r
 445         "       ldr r1, [r3]                                            \n"\r
 446         "       ldr r0, [r1]                                            \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
 447         "       ldmia r0!, {r4-r11}                                     \n" /* Pop the registers. */\r
 448         "       msr psp, r0                                                     \n"\r
 449         "       isb                                                                     \n"\r
 450         "       bx r14                                                          \n"\r
 451         "                                                                               \n"\r
 452         "       .align 2                                                        \n"\r
 453         "pxCurrentTCBConst: .word pxCurrentTCB  \n"\r
 454         ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)\r
 455         );\r
 456 }\r
 457 /*-----------------------------------------------------------*/\r
 458 \r
 459 void xPortSysTickHandler( void )\r
 460 {\r
 461         /* The SysTick runs at the lowest interrupt priority, so when this interrupt\r
 462         executes all interrupts must be unmasked.  There is therefore no need to\r
 463         save and then restore the interrupt mask value as its value is already\r
 464         known. */\r
 465         ( void ) portSET_INTERRUPT_MASK_FROM_ISR();\r
 466         {\r
 467                 /* Increment the RTOS tick. */\r
 468                 if( xTaskIncrementTick() != pdFALSE )\r
 469                 {\r
 470                         /* A context switch is required.  Context switching is performed in\r
 471                         the PendSV interrupt.  Pend the PendSV interrupt. */\r
 472                         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 473                 }\r
 474         }\r
 475         portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );\r
 476 }\r
 477 /*-----------------------------------------------------------*/\r
 478 \r
 479 #if configUSE_TICKLESS_IDLE == 1\r
 480 \r
 481         __attribute__((weak)) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\r
 482         {\r
 483         uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickCTRL;\r
 484         TickType_t xModifiableIdleTime;\r
 485 \r
 486                 /* Make sure the SysTick reload value does not overflow the counter. */\r
 487                 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\r
 488                 {\r
 489                         xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\r
 490                 }\r
 491 \r
 492                 /* Stop the SysTick momentarily.  The time the SysTick is stopped for\r
 493                 is accounted for as best it can be, but using the tickless mode will\r
 494                 inevitably result in some tiny drift of the time maintained by the\r
 495                 kernel with respect to calendar time. */\r
 496                 portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;\r
 497 \r
 498                 /* Calculate the reload value required to wait xExpectedIdleTime\r
 499                 tick periods.  -1 is used because this code will execute part way\r
 500                 through one of the tick periods. */\r
 501                 ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\r
 502                 if( ulReloadValue > ulStoppedTimerCompensation )\r
 503                 {\r
 504                         ulReloadValue -= ulStoppedTimerCompensation;\r
 505                 }\r
 506 \r
 507                 /* Enter a critical section but don't use the taskENTER_CRITICAL()\r
 508                 method as that will mask interrupts that should exit sleep mode. */\r
 509                 __asm volatile( "cpsid i" );\r
 510 \r
 511                 /* If a context switch is pending or a task is waiting for the scheduler\r
 512                 to be unsuspended then abandon the low power entry. */\r
 513                 if( eTaskConfirmSleepModeStatus() == eAbortSleep )\r
 514                 {\r
 515                         /* Restart from whatever is left in the count register to complete\r
 516                         this tick period. */\r
 517                         portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;\r
 518 \r
 519                         /* Restart SysTick. */\r
 520                         portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\r
 521 \r
 522                         /* Reset the reload register to the value required for normal tick\r
 523                         periods. */\r
 524                         portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\r
 525 \r
 526                         /* Re-enable interrupts - see comments above the cpsid instruction()\r
 527                         above. */\r
 528                         __asm volatile( "cpsie i" );\r
 529                 }\r
 530                 else\r
 531                 {\r
 532                         /* Set the new reload value. */\r
 533                         portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\r
 534 \r
 535                         /* Clear the SysTick count flag and set the count value back to\r
 536                         zero. */\r
 537                         portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
 538 \r
 539                         /* Restart SysTick. */\r
 540                         portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\r
 541 \r
 542                         /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can\r
 543                         set its parameter to 0 to indicate that its implementation contains\r
 544                         its own wait for interrupt or wait for event instruction, and so wfi\r
 545                         should not be executed again.  However, the original expected idle\r
 546                         time variable must remain unmodified, so a copy is taken. */\r
 547                         xModifiableIdleTime = xExpectedIdleTime;\r
 548                         configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\r
 549                         if( xModifiableIdleTime > 0 )\r
 550                         {\r
 551                                 __asm volatile( "dsb" );\r
 552                                 __asm volatile( "wfi" );\r
 553                                 __asm volatile( "isb" );\r
 554                         }\r
 555                         configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\r
 556 \r
 557                         /* Stop SysTick.  Again, the time the SysTick is stopped for is\r
 558                         accounted for as best it can be, but using the tickless mode will\r
 559                         inevitably result in some tiny drift of the time maintained by the\r
 560                         kernel with respect to calendar time. */\r
 561                         ulSysTickCTRL = portNVIC_SYSTICK_CTRL_REG;\r
 562                         portNVIC_SYSTICK_CTRL_REG = ( ulSysTickCTRL & ~portNVIC_SYSTICK_ENABLE_BIT );\r
 563 \r
 564                         /* Re-enable interrupts - see comments above the cpsid instruction()\r
 565                         above. */\r
 566                         __asm volatile( "cpsie i" );\r
 567 \r
 568                         if( ( ulSysTickCTRL & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\r
 569                         {\r
 570                                 uint32_t ulCalculatedLoadValue;\r
 571 \r
 572                                 /* The tick interrupt has already executed, and the SysTick\r
 573                                 count reloaded with ulReloadValue.  Reset the\r
 574                                 portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick\r
 575                                 period. */\r
 576                                 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\r
 577 \r
 578                                 /* Don't allow a tiny value, or values that have somehow\r
 579                                 underflowed because the post sleep hook did something\r
 580                                 that took too long. */\r
 581                                 if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )\r
 582                                 {\r
 583                                         ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );\r
 584                                 }\r
 585 \r
 586                                 portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;\r
 587 \r
 588                                 /* The tick interrupt handler will already have pended the tick\r
 589                                 processing in the kernel.  As the pending tick will be\r
 590                                 processed as soon as this function exits, the tick value\r
 591                                 maintained by the tick is stepped forward by one less than the\r
 592                                 time spent waiting. */\r
 593                                 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\r
 594                         }\r
 595                         else\r
 596                         {\r
 597                                 /* Something other than the tick interrupt ended the sleep.\r
 598                                 Work out how long the sleep lasted rounded to complete tick\r
 599                                 periods (not the ulReload value which accounted for part\r
 600                                 ticks). */\r
 601                                 ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;\r
 602 \r
 603                                 /* How many complete tick periods passed while the processor\r
 604                                 was waiting? */\r
 605                                 ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\r
 606 \r
 607                                 /* The reload value is set to whatever fraction of a single tick\r
 608                                 period remains. */\r
 609                                 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1 ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\r
 610                         }\r
 611 \r
 612                         /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG\r
 613                         again, then set portNVIC_SYSTICK_LOAD_REG back to its standard\r
 614                         value.  The critical section is used to ensure the tick interrupt\r
 615                         can only execute once in the case that the reload register is near\r
 616                         zero. */\r
 617                         portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
 618                         portENTER_CRITICAL();\r
 619                         {\r
 620                                 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\r
 621                                 vTaskStepTick( ulCompleteTickPeriods );\r
 622                                 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\r
 623                         }\r
 624                         portEXIT_CRITICAL();\r
 625                 }\r
 626         }\r
 627 \r
 628 #endif /* #if configUSE_TICKLESS_IDLE */\r
 629 /*-----------------------------------------------------------*/\r
 630 \r
 631 /*\r
 632  * Setup the systick timer to generate the tick interrupts at the required\r
 633  * frequency.\r
 634  */\r
 635 __attribute__(( weak )) void vPortSetupTimerInterrupt( void )\r
 636 {\r
 637         /* Calculate the constants required to configure the tick interrupt. */\r
 638         #if configUSE_TICKLESS_IDLE == 1\r
 639         {\r
 640                 ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\r
 641                 xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\r
 642                 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\r
 643         }\r
 644         #endif /* configUSE_TICKLESS_IDLE */\r
 645 \r
 646         /* Configure SysTick to interrupt at the requested rate. */\r
 647         portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
 648         portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );\r
 649 }\r
 650 /*-----------------------------------------------------------*/\r
 651 \r
 652 #if( configASSERT_DEFINED == 1 )\r
 653 \r
 654         void vPortValidateInterruptPriority( void )\r
 655         {\r
 656         uint32_t ulCurrentInterrupt;\r
 657         uint8_t ucCurrentPriority;\r
 658 \r
 659                 /* Obtain the number of the currently executing interrupt. */\r
 660                 __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );\r
 661 \r
 662                 /* Is the interrupt number a user defined interrupt? */\r
 663                 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\r
 664                 {\r
 665                         /* Look up the interrupt's priority. */\r
 666                         ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\r
 667 \r
 668                         /* The following assertion will fail if a service routine (ISR) for\r
 669                         an interrupt that has been assigned a priority above\r
 670                         configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\r
 671                         function.  ISR safe FreeRTOS API functions must *only* be called\r
 672                         from interrupts that have been assigned a priority at or below\r
 673                         configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 674 \r
 675                         Numerically low interrupt priority numbers represent logically high\r
 676                         interrupt priorities, therefore the priority of the interrupt must\r
 677                         be set to a value equal to or numerically *higher* than\r
 678                         configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 679 \r
 680                         Interrupts that use the FreeRTOS API must not be left at their\r
 681                         default priority of     zero as that is the highest possible priority,\r
 682                         which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,\r
 683                         and     therefore also guaranteed to be invalid.\r
 684 \r
 685                         FreeRTOS maintains separate thread and ISR API functions to ensure\r
 686                         interrupt entry is as fast and simple as possible.\r
 687 \r
 688                         The following links provide detailed information:\r
 689                         http://www.freertos.org/RTOS-Cortex-M3-M4.html\r
 690                         http://www.freertos.org/FAQHelp.html */\r
 691                         configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\r
 692                 }\r
 693 \r
 694                 /* Priority grouping:  The interrupt controller (NVIC) allows the bits\r
 695                 that define each interrupt's priority to be split between bits that\r
 696                 define the interrupt's pre-emption priority bits and bits that define\r
 697                 the interrupt's sub-priority.  For simplicity all bits must be defined\r
 698                 to be pre-emption priority bits.  The following assertion will fail if\r
 699                 this is not the case (if some bits represent a sub-priority).\r
 700 \r
 701                 If the application only uses CMSIS libraries for interrupt\r
 702                 configuration then the correct setting can be achieved on all Cortex-M\r
 703                 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\r
 704                 scheduler.  Note however that some vendor specific peripheral libraries\r
 705                 assume a non-zero priority group setting, in which cases using a value\r
 706                 of zero will result in unpredicable behaviour. */\r
 707                 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );\r
 708         }\r
 709 \r
 710 #endif /* configASSERT_DEFINED */\r
 711 \r
 712 \r
 713 \r
 714 \r
 715 \r
 716 \r
 717 \r
 718 \r
 719 \r
 720 \r
 721 \r
 722 \r
 723 \r
 724 \r
 725 \r
 726 \r
 727 \r
 728 \r
 729 \r
 730 \r
 731 \r