2 FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.
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5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 This file is part of the FreeRTOS distribution.
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9 FreeRTOS is free software; you can redistribute it and/or modify it under
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10 the terms of the GNU General Public License (version 2) as published by the
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11 Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
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13 ***************************************************************************
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14 >>! NOTE: The modification to the GPL is included to allow you to !<<
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15 >>! distribute a combined work that includes FreeRTOS without being !<<
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16 >>! obliged to provide the source code for proprietary components !<<
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17 >>! outside of the FreeRTOS kernel. !<<
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18 ***************************************************************************
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20 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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21 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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22 FOR A PARTICULAR PURPOSE. Full license text is available on the following
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23 link: http://www.freertos.org/a00114.html
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25 ***************************************************************************
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27 * FreeRTOS provides completely free yet professionally developed, *
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28 * robust, strictly quality controlled, supported, and cross *
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29 * platform software that is more than just the market leader, it *
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30 * is the industry's de facto standard. *
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32 * Help yourself get started quickly while simultaneously helping *
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33 * to support the FreeRTOS project by purchasing a FreeRTOS *
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34 * tutorial book, reference manual, or both: *
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35 * http://www.FreeRTOS.org/Documentation *
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37 ***************************************************************************
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39 http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
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40 the FAQ page "My application does not run, what could be wrong?". Have you
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41 defined configASSERT()?
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43 http://www.FreeRTOS.org/support - In return for receiving this top quality
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44 embedded software for free we request you assist our global community by
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45 participating in the support forum.
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47 http://www.FreeRTOS.org/training - Investing in training allows your team to
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48 be as productive as possible as early as possible. Now you can receive
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49 FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
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50 Ltd, and the world's leading authority on the world's leading RTOS.
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52 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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53 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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54 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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56 http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
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57 Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
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59 http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
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60 Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
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61 licenses offer ticketed support, indemnification and commercial middleware.
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63 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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64 engineered and independently SIL3 certified version for use in safety and
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65 mission critical applications that require provable dependability.
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70 /*-----------------------------------------------------------
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71 * Implementation of functions defined in portable.h for the ARM CM3 port.
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72 *----------------------------------------------------------*/
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74 /* Scheduler includes. */
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75 #include "FreeRTOS.h"
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78 /* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is
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79 defined. The value should also ensure backward compatibility.
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80 FreeRTOS.org versions prior to V4.4.0 did not include this definition. */
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81 #ifndef configKERNEL_INTERRUPT_PRIORITY
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82 #define configKERNEL_INTERRUPT_PRIORITY 255
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85 #ifndef configSYSTICK_CLOCK_HZ
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86 #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
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87 /* Ensure the SysTick is clocked at the same frequency as the core. */
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88 #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
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90 /* The way the SysTick is clocked is not modified in case it is not the same
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92 #define portNVIC_SYSTICK_CLK_BIT ( 0 )
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95 /* Constants required to manipulate the core. Registers first... */
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96 #define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )
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97 #define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )
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98 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )
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99 #define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
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100 /* ...then bits in the registers. */
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101 #define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
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102 #define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
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103 #define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
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104 #define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
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105 #define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
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107 #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
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108 #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
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110 /* Constants required to check the validity of an interrupt priority. */
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111 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
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112 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
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113 #define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
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114 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
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115 #define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
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116 #define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
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117 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
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118 #define portPRIGROUP_SHIFT ( 8UL )
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120 /* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
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121 #define portVECTACTIVE_MASK ( 0xFFUL )
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123 /* Constants required to set up the initial stack. */
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124 #define portINITIAL_XPSR ( 0x01000000UL )
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126 /* The systick is a 24-bit counter. */
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127 #define portMAX_24_BIT_NUMBER ( 0xffffffUL )
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129 /* A fiddle factor to estimate the number of SysTick counts that would have
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130 occurred while the SysTick counter is stopped during tickless idle
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132 #define portMISSED_COUNTS_FACTOR ( 45UL )
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134 /* Let the user override the pre-loading of the initial LR with the address of
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135 prvTaskExitError() in case it messes up unwinding of the stack in the
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137 #ifdef configTASK_RETURN_ADDRESS
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138 #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
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140 #define portTASK_RETURN_ADDRESS prvTaskExitError
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143 /* Each task maintains its own interrupt status in the critical nesting
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145 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
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148 * Setup the timer to generate the tick interrupts. The implementation in this
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149 * file is weak to allow application writers to change the timer used to
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150 * generate the tick interrupt.
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152 void vPortSetupTimerInterrupt( void );
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155 * Exception handlers.
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157 void xPortPendSVHandler( void ) __attribute__ (( naked ));
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158 void xPortSysTickHandler( void );
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159 void vPortSVCHandler( void ) __attribute__ (( naked ));
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162 * Start first task is a separate function so it can be tested in isolation.
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164 static void prvPortStartFirstTask( void ) __attribute__ (( naked ));
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167 * Used to catch tasks that attempt to return from their implementing function.
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169 static void prvTaskExitError( void );
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171 /*-----------------------------------------------------------*/
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174 * The number of SysTick increments that make up one tick period.
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176 #if configUSE_TICKLESS_IDLE == 1
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177 static uint32_t ulTimerCountsForOneTick = 0;
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178 #endif /* configUSE_TICKLESS_IDLE */
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181 * The maximum number of tick periods that can be suppressed is limited by the
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182 * 24 bit resolution of the SysTick timer.
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184 #if configUSE_TICKLESS_IDLE == 1
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185 static uint32_t xMaximumPossibleSuppressedTicks = 0;
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186 #endif /* configUSE_TICKLESS_IDLE */
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189 * Compensate for the CPU cycles that pass while the SysTick is stopped (low
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190 * power functionality only.
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192 #if configUSE_TICKLESS_IDLE == 1
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193 static uint32_t ulStoppedTimerCompensation = 0;
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194 #endif /* configUSE_TICKLESS_IDLE */
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197 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
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198 * FreeRTOS API functions are not called from interrupts that have been assigned
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199 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
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201 #if ( configASSERT_DEFINED == 1 )
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202 static uint8_t ucMaxSysCallPriority = 0;
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203 static uint32_t ulMaxPRIGROUPValue = 0;
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204 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
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205 #endif /* configASSERT_DEFINED */
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207 /*-----------------------------------------------------------*/
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210 * See header file for description.
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212 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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214 /* Simulate the stack frame as it would be created by a context switch
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216 pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
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217 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
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219 *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
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221 *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
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222 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
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223 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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224 pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
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226 return pxTopOfStack;
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228 /*-----------------------------------------------------------*/
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230 static void prvTaskExitError( void )
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232 /* A function that implements a task must not exit or attempt to return to
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233 its caller as there is nothing to return to. If a task wants to exit it
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234 should instead call vTaskDelete( NULL ).
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236 Artificially force an assert() to be triggered if configASSERT() is
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237 defined, then stop here so application writers can catch the error. */
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238 configASSERT( uxCriticalNesting == ~0UL );
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239 portDISABLE_INTERRUPTS();
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242 /*-----------------------------------------------------------*/
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244 void vPortSVCHandler( void )
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247 " ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */
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248 " ldr r1, [r3] \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
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249 " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */
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250 " ldmia r0!, {r4-r11} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
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251 " msr psp, r0 \n" /* Restore the task stack pointer. */
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254 " msr basepri, r0 \n"
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255 " orr r14, #0xd \n"
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259 "pxCurrentTCBConst2: .word pxCurrentTCB \n"
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262 /*-----------------------------------------------------------*/
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264 static void prvPortStartFirstTask( void )
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267 " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
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270 " msr msp, r0 \n" /* Set the msp back to the start of the stack. */
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271 " cpsie i \n" /* Globally enable interrupts. */
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275 " svc 0 \n" /* System call to start first task. */
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279 /*-----------------------------------------------------------*/
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282 * See header file for description.
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284 BaseType_t xPortStartScheduler( void )
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286 /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
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287 See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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288 configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
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290 #if( configASSERT_DEFINED == 1 )
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292 volatile uint32_t ulOriginalPriority;
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293 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
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294 volatile uint8_t ucMaxPriorityValue;
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296 /* Determine the maximum priority from which ISR safe FreeRTOS API
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297 functions can be called. ISR safe functions are those that end in
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298 "FromISR". FreeRTOS maintains separate thread and ISR API functions to
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299 ensure interrupt entry is as fast and simple as possible.
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301 Save the interrupt priority value that is about to be clobbered. */
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302 ulOriginalPriority = *pucFirstUserPriorityRegister;
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304 /* Determine the number of priority bits available. First write to all
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306 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
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308 /* Read the value back to see how many bits stuck. */
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309 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
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311 /* Use the same mask on the maximum system call priority. */
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312 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
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314 /* Calculate the maximum acceptable priority group value for the number
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315 of bits read back. */
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316 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
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317 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
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319 ulMaxPRIGROUPValue--;
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320 ucMaxPriorityValue <<= ( uint8_t ) 0x01;
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323 /* Shift the priority group value back to its position within the AIRCR
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325 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
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326 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
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328 /* Restore the clobbered interrupt priority register to its original
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330 *pucFirstUserPriorityRegister = ulOriginalPriority;
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332 #endif /* conifgASSERT_DEFINED */
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334 /* Make PendSV and SysTick the lowest priority interrupts. */
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335 portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
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336 portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
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338 /* Start the timer that generates the tick ISR. Interrupts are disabled
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340 vPortSetupTimerInterrupt();
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342 /* Initialise the critical nesting count ready for the first task. */
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343 uxCriticalNesting = 0;
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345 /* Start the first task. */
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346 prvPortStartFirstTask();
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348 /* Should never get here as the tasks will now be executing! Call the task
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349 exit error function to prevent compiler warnings about a static function
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350 not being called in the case that the application writer overrides this
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351 functionality by defining configTASK_RETURN_ADDRESS. */
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352 prvTaskExitError();
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354 /* Should not get here! */
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357 /*-----------------------------------------------------------*/
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359 void vPortEndScheduler( void )
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361 /* Not implemented in ports where there is nothing to return to.
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362 Artificially force an assert. */
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363 configASSERT( uxCriticalNesting == 1000UL );
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365 /*-----------------------------------------------------------*/
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367 void vPortYield( void )
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369 /* Set a PendSV to request a context switch. */
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370 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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372 /* Barriers are normally not required but do ensure the code is completely
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373 within the specified behaviour for the architecture. */
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374 __asm volatile( "dsb" );
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375 __asm volatile( "isb" );
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377 /*-----------------------------------------------------------*/
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379 void vPortEnterCritical( void )
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381 portDISABLE_INTERRUPTS();
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382 uxCriticalNesting++;
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383 __asm volatile( "dsb" );
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384 __asm volatile( "isb" );
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386 /* This is not the interrupt safe version of the enter critical function so
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387 assert() if it is being called from an interrupt context. Only API
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388 functions that end in "FromISR" can be used in an interrupt. Only assert if
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389 the critical nesting count is 1 to protect against recursive calls if the
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390 assert function also uses a critical section. */
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391 if( uxCriticalNesting == 1 )
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393 configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
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396 /*-----------------------------------------------------------*/
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398 void vPortExitCritical( void )
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400 configASSERT( uxCriticalNesting );
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401 uxCriticalNesting--;
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402 if( uxCriticalNesting == 0 )
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404 portENABLE_INTERRUPTS();
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407 /*-----------------------------------------------------------*/
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409 __attribute__(( naked )) uint32_t ulPortSetInterruptMask( void )
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413 " mrs r0, basepri \n" \
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415 " msr basepri, r1 \n" \
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417 :: "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "r0", "r1" \
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420 /* This return will not be reached but is necessary to prevent compiler
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424 /*-----------------------------------------------------------*/
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426 __attribute__(( naked )) void vPortClearInterruptMask( uint32_t ulNewMaskValue )
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430 " msr basepri, r0 \n" \
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435 /* Just to avoid compiler warnings. */
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436 ( void ) ulNewMaskValue;
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438 /*-----------------------------------------------------------*/
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440 void xPortPendSVHandler( void )
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442 /* This is a naked function. */
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449 " ldr r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */
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452 " stmdb r0!, {r4-r11} \n" /* Save the remaining registers. */
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453 " str r0, [r2] \n" /* Save the new top of stack into the first member of the TCB. */
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455 " stmdb sp!, {r3, r14} \n"
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457 " msr basepri, r0 \n"
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458 " bl vTaskSwitchContext \n"
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460 " msr basepri, r0 \n"
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461 " ldmia sp!, {r3, r14} \n"
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462 " \n" /* Restore the context, including the critical nesting count. */
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464 " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */
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465 " ldmia r0!, {r4-r11} \n" /* Pop the registers. */
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471 "pxCurrentTCBConst: .word pxCurrentTCB \n"
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472 ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
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475 /*-----------------------------------------------------------*/
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477 void xPortSysTickHandler( void )
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479 /* The SysTick runs at the lowest interrupt priority, so when this interrupt
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480 executes all interrupts must be unmasked. There is therefore no need to
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481 save and then restore the interrupt mask value as its value is already
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483 ( void ) portSET_INTERRUPT_MASK_FROM_ISR();
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485 /* Increment the RTOS tick. */
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486 if( xTaskIncrementTick() != pdFALSE )
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488 /* A context switch is required. Context switching is performed in
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489 the PendSV interrupt. Pend the PendSV interrupt. */
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490 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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493 portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );
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495 /*-----------------------------------------------------------*/
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497 #if configUSE_TICKLESS_IDLE == 1
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499 __attribute__((weak)) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
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501 uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickCTRL;
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502 TickType_t xModifiableIdleTime;
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504 /* Make sure the SysTick reload value does not overflow the counter. */
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505 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
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507 xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
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510 /* Stop the SysTick momentarily. The time the SysTick is stopped for
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511 is accounted for as best it can be, but using the tickless mode will
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512 inevitably result in some tiny drift of the time maintained by the
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513 kernel with respect to calendar time. */
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514 portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
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516 /* Calculate the reload value required to wait xExpectedIdleTime
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517 tick periods. -1 is used because this code will execute part way
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518 through one of the tick periods. */
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519 ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
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520 if( ulReloadValue > ulStoppedTimerCompensation )
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522 ulReloadValue -= ulStoppedTimerCompensation;
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525 /* Enter a critical section but don't use the taskENTER_CRITICAL()
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526 method as that will mask interrupts that should exit sleep mode. */
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527 __asm volatile( "cpsid i" );
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529 /* If a context switch is pending or a task is waiting for the scheduler
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530 to be unsuspended then abandon the low power entry. */
\r
531 if( eTaskConfirmSleepModeStatus() == eAbortSleep )
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533 /* Restart from whatever is left in the count register to complete
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534 this tick period. */
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535 portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
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537 /* Restart SysTick. */
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538 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
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540 /* Reset the reload register to the value required for normal tick
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542 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
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544 /* Re-enable interrupts - see comments above the cpsid instruction()
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546 __asm volatile( "cpsie i" );
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550 /* Set the new reload value. */
\r
551 portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
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553 /* Clear the SysTick count flag and set the count value back to
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555 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
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557 /* Restart SysTick. */
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558 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
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560 /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
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561 set its parameter to 0 to indicate that its implementation contains
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562 its own wait for interrupt or wait for event instruction, and so wfi
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563 should not be executed again. However, the original expected idle
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564 time variable must remain unmodified, so a copy is taken. */
\r
565 xModifiableIdleTime = xExpectedIdleTime;
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566 configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
\r
567 if( xModifiableIdleTime > 0 )
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569 __asm volatile( "dsb" );
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570 __asm volatile( "wfi" );
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571 __asm volatile( "isb" );
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573 configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
\r
575 /* Stop SysTick. Again, the time the SysTick is stopped for is
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576 accounted for as best it can be, but using the tickless mode will
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577 inevitably result in some tiny drift of the time maintained by the
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578 kernel with respect to calendar time. */
\r
579 ulSysTickCTRL = portNVIC_SYSTICK_CTRL_REG;
\r
580 portNVIC_SYSTICK_CTRL_REG = ( ulSysTickCTRL & ~portNVIC_SYSTICK_ENABLE_BIT );
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582 /* Re-enable interrupts - see comments above the cpsid instruction()
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584 __asm volatile( "cpsie i" );
\r
586 if( ( ulSysTickCTRL & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
\r
588 uint32_t ulCalculatedLoadValue;
\r
590 /* The tick interrupt has already executed, and the SysTick
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591 count reloaded with ulReloadValue. Reset the
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592 portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
\r
594 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
\r
596 /* Don't allow a tiny value, or values that have somehow
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597 underflowed because the post sleep hook did something
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598 that took too long. */
\r
599 if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
\r
601 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
\r
604 portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
\r
606 /* The tick interrupt handler will already have pended the tick
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607 processing in the kernel. As the pending tick will be
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608 processed as soon as this function exits, the tick value
\r
609 maintained by the tick is stepped forward by one less than the
\r
610 time spent waiting. */
\r
611 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
\r
615 /* Something other than the tick interrupt ended the sleep.
\r
616 Work out how long the sleep lasted rounded to complete tick
\r
617 periods (not the ulReload value which accounted for part
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619 ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
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621 /* How many complete tick periods passed while the processor
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623 ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
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625 /* The reload value is set to whatever fraction of a single tick
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627 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
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630 /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
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631 again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
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632 value. The critical section is used to ensure the tick interrupt
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633 can only execute once in the case that the reload register is near
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635 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
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636 portENTER_CRITICAL();
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638 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
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639 vTaskStepTick( ulCompleteTickPeriods );
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640 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
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642 portEXIT_CRITICAL();
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646 #endif /* #if configUSE_TICKLESS_IDLE */
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647 /*-----------------------------------------------------------*/
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650 * Setup the systick timer to generate the tick interrupts at the required
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653 __attribute__(( weak )) void vPortSetupTimerInterrupt( void )
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655 /* Calculate the constants required to configure the tick interrupt. */
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656 #if configUSE_TICKLESS_IDLE == 1
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658 ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
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659 xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
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660 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
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662 #endif /* configUSE_TICKLESS_IDLE */
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664 /* Configure SysTick to interrupt at the requested rate. */
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665 portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
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666 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
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668 /*-----------------------------------------------------------*/
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670 #if( configASSERT_DEFINED == 1 )
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672 void vPortValidateInterruptPriority( void )
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674 uint32_t ulCurrentInterrupt;
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675 uint8_t ucCurrentPriority;
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677 /* Obtain the number of the currently executing interrupt. */
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678 __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );
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680 /* Is the interrupt number a user defined interrupt? */
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681 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
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683 /* Look up the interrupt's priority. */
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684 ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
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686 /* The following assertion will fail if a service routine (ISR) for
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687 an interrupt that has been assigned a priority above
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688 configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
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689 function. ISR safe FreeRTOS API functions must *only* be called
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690 from interrupts that have been assigned a priority at or below
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691 configMAX_SYSCALL_INTERRUPT_PRIORITY.
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693 Numerically low interrupt priority numbers represent logically high
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694 interrupt priorities, therefore the priority of the interrupt must
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695 be set to a value equal to or numerically *higher* than
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696 configMAX_SYSCALL_INTERRUPT_PRIORITY.
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698 Interrupts that use the FreeRTOS API must not be left at their
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699 default priority of zero as that is the highest possible priority,
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700 which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
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701 and therefore also guaranteed to be invalid.
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703 FreeRTOS maintains separate thread and ISR API functions to ensure
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704 interrupt entry is as fast and simple as possible.
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706 The following links provide detailed information:
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707 http://www.freertos.org/RTOS-Cortex-M3-M4.html
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708 http://www.freertos.org/FAQHelp.html */
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709 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
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712 /* Priority grouping: The interrupt controller (NVIC) allows the bits
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713 that define each interrupt's priority to be split between bits that
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714 define the interrupt's pre-emption priority bits and bits that define
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715 the interrupt's sub-priority. For simplicity all bits must be defined
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716 to be pre-emption priority bits. The following assertion will fail if
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717 this is not the case (if some bits represent a sub-priority).
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719 If the application only uses CMSIS libraries for interrupt
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720 configuration then the correct setting can be achieved on all Cortex-M
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721 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
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722 scheduler. Note however that some vendor specific peripheral libraries
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723 assume a non-zero priority group setting, in which cases using a value
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724 of zero will result in unpredicable behaviour. */
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725 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
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728 #endif /* configASSERT_DEFINED */
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projects / freertos / blob