git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/ARM_CM3/port.c

   1 /*\r
   2     FreeRTOS V7.4.0 - Copyright (C) 2013 Real Time Engineers Ltd.\r
   3 \r
   4     FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME.  PLEASE VISIT\r
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   6 \r
   7     ***************************************************************************\r
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  24     ***************************************************************************\r
  25 \r
  26 \r
  27     This file is part of the FreeRTOS distribution.\r
  28 \r
  29     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  30     the terms of the GNU General Public License (version 2) as published by the\r
  31     Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
  32 \r
  33     >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
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  35     provide the source code for proprietary components outside of the FreeRTOS\r
  36     kernel.\r
  37 \r
  38     FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
  39     WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
  40     FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more\r
  41     details. You should have received a copy of the GNU General Public License\r
  42     and the FreeRTOS license exception along with FreeRTOS; if not itcan be\r
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  44     writing to Real Time Engineers Ltd., contact details for whom are available\r
  45     on the FreeRTOS WEB site.\r
  46 \r
  47     1 tab == 4 spaces!\r
  48 \r
  49     ***************************************************************************\r
  50      *                                                                       *\r
  51      *    Having a problem?  Start by reading the FAQ "My application does   *\r
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  53      *                                                                       *\r
  54      *    http://www.FreeRTOS.org/FAQHelp.html                               *\r
  55      *                                                                       *\r
  56     ***************************************************************************\r
  57 \r
  58 \r
  59     http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
  60     license and Real Time Engineers Ltd. contact details.\r
  61 \r
  62     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
  63     including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
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  65 \r
  66     http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
  67     Integrity Systems, who sell the code with commercial support,\r
  68     indemnification and middleware, under the OpenRTOS brand.\r
  69 \r
  70     http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
  71     engineered and independently SIL3 certified version for use in safety and\r
  72     mission critical applications that require provable dependability.\r
  73 */\r
  74 \r
  75 /*-----------------------------------------------------------\r
  76  * Implementation of functions defined in portable.h for the ARM CM3 port.\r
  77  *----------------------------------------------------------*/\r
  78 \r
  79 /* Scheduler includes. */\r
  80 #include "FreeRTOS.h"\r
  81 #include "task.h"\r
  82 \r
  83 /* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is\r
  84 defined.  The value should also ensure backward compatibility.\r
  85 FreeRTOS.org versions prior to V4.4.0 did not include this definition. */\r
  86 #ifndef configKERNEL_INTERRUPT_PRIORITY\r
  87         #define configKERNEL_INTERRUPT_PRIORITY 255\r
  88 #endif\r
  89 \r
  90 #ifndef configSYSTICK_CLOCK_HZ\r
  91         #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ\r
  92 #endif\r
  93 \r
  94 /* Constants required to manipulate the core.  Registers first... */\r
  95 #define portNVIC_SYSTICK_CTRL_REG                       ( * ( ( volatile unsigned long * ) 0xe000e010 ) )\r
  96 #define portNVIC_SYSTICK_LOAD_REG                       ( * ( ( volatile unsigned long * ) 0xe000e014 ) )\r
  97 #define portNVIC_SYSTICK_CURRENT_VALUE_REG      ( * ( ( volatile unsigned long * ) 0xe000e018 ) )\r
  98 #define portNVIC_INT_CTRL_REG                           ( * ( ( volatile unsigned long * ) 0xe000ed04 ) )\r
  99 #define portNVIC_SYSPRI2_REG                            ( * ( ( volatile unsigned long * ) 0xe000ed20 ) )\r
 100 /* ...then bits in the registers. */\r
 101 #define portNVIC_SYSTICK_CLK_BIT                        ( 1UL << 2UL )\r
 102 #define portNVIC_SYSTICK_INT_BIT                        ( 1UL << 1UL )\r
 103 #define portNVIC_SYSTICK_ENABLE_BIT                     ( 1UL << 0UL )\r
 104 #define portNVIC_SYSTICK_COUNT_FLAG_BIT         ( 1UL << 16UL )\r
 105 #define portNVIC_PENDSVSET_BIT                          ( 1UL << 28UL )\r
 106 #define portNVIC_PENDSVCLEAR_BIT                        ( 1UL << 27UL )\r
 107 #define portNVIC_PEND_SYSTICK_CLEAR_BIT         ( 1UL << 25UL )\r
 108 \r
 109 #define portNVIC_PENDSV_PRI                             ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
 110 #define portNVIC_SYSTICK_PRI                    ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
 111 \r
 112 /* Constants required to set up the initial stack. */\r
 113 #define portINITIAL_XPSR                        ( 0x01000000 )\r
 114 \r
 115 /* The priority used by the kernel is assigned to a variable to make access\r
 116 from inline assembler easier. */\r
 117 const unsigned long ulKernelPriority = configKERNEL_INTERRUPT_PRIORITY;\r
 118 \r
 119 /* Each task maintains its own interrupt status in the critical nesting\r
 120 variable. */\r
 121 static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;\r
 122 \r
 123 /*\r
 124  * Setup the timer to generate the tick interrupts.  The implementation in this\r
 125  * file is weak to allow application writers to change the timer used to\r
 126  * generate the tick interrupt.\r
 127  */\r
 128 void vPortSetupTimerInterrupt( void );\r
 129 \r
 130 /*\r
 131  * Exception handlers.\r
 132  */\r
 133 void xPortPendSVHandler( void ) __attribute__ (( naked ));\r
 134 void xPortSysTickHandler( void );\r
 135 void vPortSVCHandler( void ) __attribute__ (( naked ));\r
 136 \r
 137 /*\r
 138  * Start first task is a separate function so it can be tested in isolation.\r
 139  */\r
 140 static void prvPortStartFirstTask( void ) __attribute__ (( naked ));\r
 141 \r
 142 /*-----------------------------------------------------------*/\r
 143 \r
 144 /*\r
 145  * The number of SysTick increments that make up one tick period.\r
 146  */\r
 147 #if configUSE_TICKLESS_IDLE == 1\r
 148         static unsigned long ulTimerReloadValueForOneTick = 0;\r
 149 #endif\r
 150 \r
 151 /*\r
 152  * The maximum number of tick periods that can be suppressed is limited by the\r
 153  * 24 bit resolution of the SysTick timer.\r
 154  */\r
 155 #if configUSE_TICKLESS_IDLE == 1\r
 156         static unsigned long xMaximumPossibleSuppressedTicks = 0;\r
 157 #endif /* configUSE_TICKLESS_IDLE */\r
 158 \r
 159 /*\r
 160  * Compensate for the CPU cycles that pass while the SysTick is stopped (low\r
 161  * power functionality only.\r
 162  */\r
 163 #if configUSE_TICKLESS_IDLE == 1\r
 164         static unsigned long ulStoppedTimerCompensation = 0;\r
 165 #endif /* configUSE_TICKLESS_IDLE */\r
 166 \r
 167 /*-----------------------------------------------------------*/\r
 168 \r
 169 /*\r
 170  * See header file for description.\r
 171  */\r
 172 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
 173 {\r
 174         /* Simulate the stack frame as it would be created by a context switch\r
 175         interrupt. */\r
 176         pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
 177         *pxTopOfStack = portINITIAL_XPSR;       /* xPSR */\r
 178         pxTopOfStack--;\r
 179         *pxTopOfStack = ( portSTACK_TYPE ) pxCode;      /* PC */\r
 180         pxTopOfStack--;\r
 181         *pxTopOfStack = 0;      /* LR */\r
 182         pxTopOfStack -= 5;      /* R12, R3, R2 and R1. */\r
 183         *pxTopOfStack = ( portSTACK_TYPE ) pvParameters;        /* R0 */\r
 184         pxTopOfStack -= 8;      /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
 185 \r
 186         return pxTopOfStack;\r
 187 }\r
 188 /*-----------------------------------------------------------*/\r
 189 \r
 190 void vPortSVCHandler( void )\r
 191 {\r
 192         __asm volatile (\r
 193                                         "       ldr     r3, pxCurrentTCBConst2          \n" /* Restore the context. */\r
 194                                         "       ldr r1, [r3]                                    \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */\r
 195                                         "       ldr r0, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
 196                                         "       ldmia r0!, {r4-r11}                             \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */\r
 197                                         "       msr psp, r0                                             \n" /* Restore the task stack pointer. */\r
 198                                         "       mov r0, #0                                              \n"\r
 199                                         "       msr     basepri, r0                                     \n"\r
 200                                         "       orr r14, #0xd                                   \n"\r
 201                                         "       bx r14                                                  \n"\r
 202                                         "                                                                       \n"\r
 203                                         "       .align 2                                                \n"\r
 204                                         "pxCurrentTCBConst2: .word pxCurrentTCB                         \n"\r
 205                                 );\r
 206 }\r
 207 /*-----------------------------------------------------------*/\r
 208 \r
 209 static void prvPortStartFirstTask( void )\r
 210 {\r
 211         __asm volatile(\r
 212                                         " ldr r0, =0xE000ED08   \n" /* Use the NVIC offset register to locate the stack. */\r
 213                                         " ldr r0, [r0]                  \n"\r
 214                                         " ldr r0, [r0]                  \n"\r
 215                                         " msr msp, r0                   \n" /* Set the msp back to the start of the stack. */\r
 216                                         " cpsie i                               \n" /* Globally enable interrupts. */\r
 217                                         " svc 0                                 \n" /* System call to start first task. */\r
 218                                         " nop                                   \n"\r
 219                                 );\r
 220 }\r
 221 /*-----------------------------------------------------------*/\r
 222 \r
 223 /*\r
 224  * See header file for description.\r
 225  */\r
 226 portBASE_TYPE xPortStartScheduler( void )\r
 227 {\r
 228         /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.\r
 229         See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\r
 230         configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );\r
 231 \r
 232         /* Make PendSV, CallSV and SysTick the same priroity as the kernel. */\r
 233         portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;\r
 234         portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;\r
 235 \r
 236         /* Start the timer that generates the tick ISR.  Interrupts are disabled\r
 237         here already. */\r
 238         vPortSetupTimerInterrupt();\r
 239 \r
 240         /* Initialise the critical nesting count ready for the first task. */\r
 241         uxCriticalNesting = 0;\r
 242 \r
 243         /* Start the first task. */\r
 244         prvPortStartFirstTask();\r
 245 \r
 246         /* Should not get here! */\r
 247         return 0;\r
 248 }\r
 249 /*-----------------------------------------------------------*/\r
 250 \r
 251 void vPortEndScheduler( void )\r
 252 {\r
 253         /* It is unlikely that the CM3 port will require this function as there\r
 254         is nothing to return to.  */\r
 255 }\r
 256 /*-----------------------------------------------------------*/\r
 257 \r
 258 void vPortYieldFromISR( void )\r
 259 {\r
 260         /* Set a PendSV to request a context switch. */\r
 261         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 262 \r
 263         /* Barriers are normally not required but do ensure the code is completely\r
 264         within the specified behaviour for the architecture. */\r
 265         __asm volatile( "dsb" );\r
 266         __asm volatile( "isb" );\r
 267 }\r
 268 /*-----------------------------------------------------------*/\r
 269 \r
 270 void vPortEnterCritical( void )\r
 271 {\r
 272         portDISABLE_INTERRUPTS();\r
 273         uxCriticalNesting++;\r
 274         __asm volatile( "dsb" );\r
 275         __asm volatile( "isb" );\r
 276 }\r
 277 /*-----------------------------------------------------------*/\r
 278 \r
 279 void vPortExitCritical( void )\r
 280 {\r
 281         uxCriticalNesting--;\r
 282         if( uxCriticalNesting == 0 )\r
 283         {\r
 284                 portENABLE_INTERRUPTS();\r
 285         }\r
 286 }\r
 287 /*-----------------------------------------------------------*/\r
 288 \r
 289 __attribute__(( naked )) unsigned long ulPortSetInterruptMask( void )\r
 290 {\r
 291         __asm volatile                                                                                                          \\r
 292         (                                                                                                                                       \\r
 293                 "       mrs r0, basepri                                                                                 \n" \\r
 294                 "       mov r1, %0                                                                                              \n"     \\r
 295                 "       msr basepri, r1                                                                                 \n" \\r
 296                 "       bx lr                                                                                                   \n" \\r
 297                 :: "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "r0", "r1"    \\r
 298         );\r
 299 \r
 300         /* This return will not be reached but is necessary to prevent compiler\r
 301         warnings. */\r
 302         return 0;\r
 303 }\r
 304 /*-----------------------------------------------------------*/\r
 305 \r
 306 __attribute__(( naked )) void vPortClearInterruptMask( unsigned long ulNewMaskValue )\r
 307 {\r
 308         __asm volatile                                                                                                  \\r
 309         (                                                                                                                               \\r
 310                 "       msr basepri, r0                                                                         \n"     \\r
 311                 "       bx lr                                                                                           \n" \\r
 312                 :::"r0"                                                                                                         \\r
 313         );\r
 314 \r
 315         /* Just to avoid compiler warnings. */\r
 316         ( void ) ulNewMaskValue;\r
 317 }\r
 318 /*-----------------------------------------------------------*/\r
 319 \r
 320 void xPortPendSVHandler( void )\r
 321 {\r
 322         /* This is a naked function. */\r
 323 \r
 324         __asm volatile\r
 325         (\r
 326         "       mrs r0, psp                                                     \n"\r
 327         "                                                                               \n"\r
 328         "       ldr     r3, pxCurrentTCBConst                   \n" /* Get the location of the current TCB. */\r
 329         "       ldr     r2, [r3]                                                \n"\r
 330         "                                                                               \n"\r
 331         "       stmdb r0!, {r4-r11}                                     \n" /* Save the remaining registers. */\r
 332         "       str r0, [r2]                                            \n" /* Save the new top of stack into the first member of the TCB. */\r
 333         "                                                                               \n"\r
 334         "       stmdb sp!, {r3, r14}                            \n"\r
 335         "       mov r0, %0                                                      \n"\r
 336         "       msr basepri, r0                                         \n"\r
 337         "       bl vTaskSwitchContext                           \n"\r
 338         "       mov r0, #0                                                      \n"\r
 339         "       msr basepri, r0                                         \n"\r
 340         "       ldmia sp!, {r3, r14}                            \n"\r
 341         "                                                                               \n"     /* Restore the context, including the critical nesting count. */\r
 342         "       ldr r1, [r3]                                            \n"\r
 343         "       ldr r0, [r1]                                            \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
 344         "       ldmia r0!, {r4-r11}                                     \n" /* Pop the registers. */\r
 345         "       msr psp, r0                                                     \n"\r
 346         "       bx r14                                                          \n"\r
 347         "                                                                               \n"\r
 348         "       .align 2                                                        \n"\r
 349         "pxCurrentTCBConst: .word pxCurrentTCB  \n"\r
 350         ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)\r
 351         );\r
 352 }\r
 353 /*-----------------------------------------------------------*/\r
 354 \r
 355 void xPortSysTickHandler( void )\r
 356 {\r
 357         /* If using preemption, also force a context switch. */\r
 358         #if configUSE_PREEMPTION == 1\r
 359                 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 360         #endif\r
 361 \r
 362         /* Only reset the systick load register if configUSE_TICKLESS_IDLE is set to\r
 363         1.  If it is set to 0 tickless idle is not being used.  If it is set to a\r
 364         value other than 0 or 1 then a timer other than the SysTick is being used\r
 365         to generate the tick interrupt. */\r
 366         #if configUSE_TICKLESS_IDLE == 1\r
 367                 portNVIC_SYSTICK_LOAD_REG = ulTimerReloadValueForOneTick;\r
 368         #endif\r
 369 \r
 370         ( void ) portSET_INTERRUPT_MASK_FROM_ISR();\r
 371         {\r
 372                 vTaskIncrementTick();\r
 373         }\r
 374         portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );\r
 375 }\r
 376 /*-----------------------------------------------------------*/\r
 377 \r
 378 #if configUSE_TICKLESS_IDLE == 1\r
 379 \r
 380         __attribute__((weak)) void vPortSuppressTicksAndSleep( portTickType xExpectedIdleTime )\r
 381         {\r
 382         unsigned long ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickIncrements;\r
 383         portTickType xModifiableIdleTime;\r
 384 \r
 385                 /* Make sure the SysTick reload value does not overflow the counter. */\r
 386                 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\r
 387                 {\r
 388                         xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\r
 389                 }\r
 390 \r
 391                 /* Calculate the reload value required to wait xExpectedIdleTime\r
 392                 tick periods.  -1 is used because this code will execute part way\r
 393                 through one of the tick periods, and the fraction of a tick period is\r
 394                 accounted for later. */\r
 395                 ulReloadValue = ( ulTimerReloadValueForOneTick * ( xExpectedIdleTime - 1UL ) );\r
 396                 if( ulReloadValue > ulStoppedTimerCompensation )\r
 397                 {\r
 398                         ulReloadValue -= ulStoppedTimerCompensation;\r
 399                 }\r
 400 \r
 401                 /* Stop the SysTick momentarily.  The time the SysTick is stopped for\r
 402                 is accounted for as best it can be, but using the tickless mode will\r
 403                 inevitably result in some tiny drift of the time maintained by the\r
 404                 kernel with respect to calendar time. */\r
 405                 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\r
 406 \r
 407                 /* Adjust the reload value to take into account that the current time\r
 408                 slice is already partially complete. */\r
 409                 ulReloadValue += ( portNVIC_SYSTICK_LOAD_REG - ( portNVIC_SYSTICK_LOAD_REG - portNVIC_SYSTICK_CURRENT_VALUE_REG ) );\r
 410 \r
 411                 /* Enter a critical section but don't use the taskENTER_CRITICAL()\r
 412                 method as that will mask interrupts that should exit sleep mode. */\r
 413                 __asm volatile( "cpsid i" );\r
 414 \r
 415                 /* If a context switch is pending or a task is waiting for the scheduler\r
 416                 to be unsuspended then abandon the low power entry. */\r
 417                 if( eTaskConfirmSleepModeStatus() == eAbortSleep )\r
 418                 {\r
 419                         /* Restart SysTick. */\r
 420                         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 421 \r
 422                         /* Re-enable interrupts - see comments above the cpsid instruction()\r
 423                         above. */\r
 424                         __asm volatile( "cpsie i" );\r
 425                 }\r
 426                 else\r
 427                 {\r
 428                         /* Set the new reload value. */\r
 429                         portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\r
 430 \r
 431                         /* Clear the SysTick count flag and set the count value back to\r
 432                         zero. */\r
 433                         portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
 434 \r
 435                         /* Restart SysTick. */\r
 436                         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 437 \r
 438                         /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can\r
 439                         set its parameter to 0 to indicate that its implementation contains\r
 440                         its own wait for interrupt or wait for event instruction, and so wfi\r
 441                         should not be executed again.  However, the original expected idle\r
 442                         time variable must remain unmodified, so a copy is taken. */\r
 443                         xModifiableIdleTime = xExpectedIdleTime;\r
 444                         configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\r
 445                         if( xModifiableIdleTime > 0 )\r
 446                         {\r
 447                                 __asm volatile( "wfi" );\r
 448                                 __asm volatile( "dsb" );\r
 449                                 __asm volatile( "isb" );\r
 450                         }\r
 451                         configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\r
 452 \r
 453                         /* Stop SysTick.  Again, the time the SysTick is stopped for is\r
 454                         accounted for as best it can be, but using the tickless mode will\r
 455                         inevitably result in some tiny drift of the time maintained by the\r
 456                         kernel with respect to calendar time. */\r
 457                         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\r
 458 \r
 459                         /* Re-enable interrupts - see comments above the cpsid instruction()\r
 460                         above. */\r
 461                         __asm volatile( "cpsie i" );\r
 462 \r
 463                         if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\r
 464                         {\r
 465                                 /* The tick interrupt has already executed, and the SysTick\r
 466                                 count reloaded with the portNVIC_SYSTICK_LOAD_REG value.\r
 467                                 Reset the portNVIC_SYSTICK_LOAD_REG with whatever remains of\r
 468                                 this tick period. */\r
 469                                 portNVIC_SYSTICK_LOAD_REG = ulTimerReloadValueForOneTick - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\r
 470 \r
 471                                 /* The tick interrupt handler will already have pended the tick\r
 472                                 processing in the kernel.  As the pending tick will be\r
 473                                 processed as soon as this function exits, the tick value\r
 474                                 maintained by the tick is stepped forward by one less than the\r
 475                                 time spent waiting. */\r
 476                                 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\r
 477                         }\r
 478                         else\r
 479                         {\r
 480                                 /* Something other than the tick interrupt ended the sleep.\r
 481                                 Work out how long the sleep lasted. */\r
 482                                 ulCompletedSysTickIncrements = ( xExpectedIdleTime * ulTimerReloadValueForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;\r
 483 \r
 484                                 /* How many complete tick periods passed while the processor\r
 485                                 was waiting? */\r
 486                                 ulCompleteTickPeriods = ulCompletedSysTickIncrements / ulTimerReloadValueForOneTick;\r
 487 \r
 488                                 /* The reload value is set to whatever fraction of a single tick\r
 489                                 period remains. */\r
 490                                 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1 ) * ulTimerReloadValueForOneTick ) - ulCompletedSysTickIncrements;\r
 491                         }\r
 492 \r
 493                         /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG\r
 494                         again, then set portNVIC_SYSTICK_LOAD_REG back to its standard\r
 495                         value. */\r
 496                         portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
 497                         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 498 \r
 499                         vTaskStepTick( ulCompleteTickPeriods );\r
 500                 }\r
 501         }\r
 502 \r
 503 #endif /* #if configUSE_TICKLESS_IDLE */\r
 504 /*-----------------------------------------------------------*/\r
 505 \r
 506 /*\r
 507  * Setup the systick timer to generate the tick interrupts at the required\r
 508  * frequency.\r
 509  */\r
 510 __attribute__(( weak )) void vPortSetupTimerInterrupt( void )\r
 511 {\r
 512         /* Calculate the constants required to configure the tick interrupt. */\r
 513         #if configUSE_TICKLESS_IDLE == 1\r
 514         {\r
 515                 ulTimerReloadValueForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
 516                 xMaximumPossibleSuppressedTicks = 0xffffffUL / ( ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL );\r
 517                 ulStoppedTimerCompensation = 45UL / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\r
 518         }\r
 519         #endif /* configUSE_TICKLESS_IDLE */\r
 520 \r
 521         /* Configure SysTick to interrupt at the requested rate. */\r
 522         portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;;\r
 523         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 524 }\r
 525 /*-----------------------------------------------------------*/\r
 526 \r