git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/ARM_CM3/port.c

   1 /*\r
   2     FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
   3 \r
   4     VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
   5 \r
   6     ***************************************************************************\r
   7      *                                                                       *\r
   8      *    FreeRTOS provides completely free yet professionally developed,    *\r
   9      *    robust, strictly quality controlled, supported, and cross          *\r
  10      *    platform software that has become a de facto standard.             *\r
  11      *                                                                       *\r
  12      *    Help yourself get started quickly and support the FreeRTOS         *\r
  13      *    project by purchasing a FreeRTOS tutorial book, reference          *\r
  14      *    manual, or both from: http://www.FreeRTOS.org/Documentation        *\r
  15      *                                                                       *\r
  16      *    Thank you!                                                         *\r
  17      *                                                                       *\r
  18     ***************************************************************************\r
  19 \r
  20     This file is part of the FreeRTOS distribution.\r
  21 \r
  22     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  23     the terms of the GNU General Public License (version 2) as published by the\r
  24     Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
  25 \r
  26     >>! NOTE: The modification to the GPL is included to allow you to distribute\r
  27     >>! a combined work that includes FreeRTOS without being obliged to provide\r
  28     >>! the source code for proprietary components outside of the FreeRTOS\r
  29     >>! kernel.\r
  30 \r
  31     FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
  32     WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
  33     FOR A PARTICULAR PURPOSE.  Full license text is available from the following\r
  34     link: http://www.freertos.org/a00114.html\r
  35 \r
  36     1 tab == 4 spaces!\r
  37 \r
  38     ***************************************************************************\r
  39      *                                                                       *\r
  40      *    Having a problem?  Start by reading the FAQ "My application does   *\r
  41      *    not run, what could be wrong?"                                     *\r
  42      *                                                                       *\r
  43      *    http://www.FreeRTOS.org/FAQHelp.html                               *\r
  44      *                                                                       *\r
  45     ***************************************************************************\r
  46 \r
  47     http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
  48     license and Real Time Engineers Ltd. contact details.\r
  49 \r
  50     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
  51     including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
  52     compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
  53 \r
  54     http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
  55     Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS\r
  56     licenses offer ticketed support, indemnification and middleware.\r
  57 \r
  58     http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
  59     engineered and independently SIL3 certified version for use in safety and\r
  60     mission critical applications that require provable dependability.\r
  61 \r
  62     1 tab == 4 spaces!\r
  63 */\r
  64 \r
  65 /*-----------------------------------------------------------\r
  66  * Implementation of functions defined in portable.h for the ARM CM3 port.\r
  67  *----------------------------------------------------------*/\r
  68 \r
  69 /* Scheduler includes. */\r
  70 #include "FreeRTOS.h"\r
  71 #include "task.h"\r
  72 \r
  73 /* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is\r
  74 defined.  The value should also ensure backward compatibility.\r
  75 FreeRTOS.org versions prior to V4.4.0 did not include this definition. */\r
  76 #ifndef configKERNEL_INTERRUPT_PRIORITY\r
  77         #define configKERNEL_INTERRUPT_PRIORITY 255\r
  78 #endif\r
  79 \r
  80 #ifndef configSYSTICK_CLOCK_HZ\r
  81         #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ\r
  82 #endif\r
  83 \r
  84 /* Constants required to manipulate the core.  Registers first... */\r
  85 #define portNVIC_SYSTICK_CTRL_REG                       ( * ( ( volatile unsigned long * ) 0xe000e010 ) )\r
  86 #define portNVIC_SYSTICK_LOAD_REG                       ( * ( ( volatile unsigned long * ) 0xe000e014 ) )\r
  87 #define portNVIC_SYSTICK_CURRENT_VALUE_REG      ( * ( ( volatile unsigned long * ) 0xe000e018 ) )\r
  88 #define portNVIC_SYSPRI2_REG                            ( * ( ( volatile unsigned long * ) 0xe000ed20 ) )\r
  89 /* ...then bits in the registers. */\r
  90 #define portNVIC_SYSTICK_CLK_BIT                        ( 1UL << 2UL )\r
  91 #define portNVIC_SYSTICK_INT_BIT                        ( 1UL << 1UL )\r
  92 #define portNVIC_SYSTICK_ENABLE_BIT                     ( 1UL << 0UL )\r
  93 #define portNVIC_SYSTICK_COUNT_FLAG_BIT         ( 1UL << 16UL )\r
  94 #define portNVIC_PENDSVCLEAR_BIT                        ( 1UL << 27UL )\r
  95 #define portNVIC_PEND_SYSTICK_CLEAR_BIT         ( 1UL << 25UL )\r
  96 \r
  97 #define portNVIC_PENDSV_PRI                                     ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
  98 #define portNVIC_SYSTICK_PRI                            ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
  99 \r
 100 /* Constants required to check the validity of an interrupt priority. */\r
 101 #define portFIRST_USER_INTERRUPT_NUMBER         ( 16 )\r
 102 #define portNVIC_IP_REGISTERS_OFFSET_16         ( 0xE000E3F0 )\r
 103 #define portAIRCR_REG                                           ( * ( ( volatile unsigned long * ) 0xE000ED0C ) )\r
 104 #define portMAX_8_BIT_VALUE                                     ( ( unsigned char ) 0xff )\r
 105 #define portTOP_BIT_OF_BYTE                                     ( ( unsigned char ) 0x80 )\r
 106 #define portMAX_PRIGROUP_BITS                           ( ( unsigned char ) 7 )\r
 107 #define portPRIORITY_GROUP_MASK                         ( 0x07UL << 8UL )\r
 108 #define portPRIGROUP_SHIFT                                      ( 8UL )\r
 109 \r
 110 /* Constants required to set up the initial stack. */\r
 111 #define portINITIAL_XPSR                                        ( 0x01000000UL )\r
 112 \r
 113 /* The systick is a 24-bit counter. */\r
 114 #define portMAX_24_BIT_NUMBER                           ( 0xffffffUL )\r
 115 \r
 116 /* A fiddle factor to estimate the number of SysTick counts that would have\r
 117 occurred while the SysTick counter is stopped during tickless idle\r
 118 calculations. */\r
 119 #define portMISSED_COUNTS_FACTOR                        ( 45UL )\r
 120 \r
 121 /* Let the user override the pre-loading of the initial LR with the address of\r
 122 prvTaskExitError() in case is messes up unwinding of the stack in the\r
 123 debugger. */\r
 124 #ifdef configTASK_RETURN_ADDRESS\r
 125         #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS\r
 126 #else\r
 127         #define portTASK_RETURN_ADDRESS prvTaskExitError\r
 128 #endif\r
 129 \r
 130 /* Each task maintains its own interrupt status in the critical nesting\r
 131 variable. */\r
 132 static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;\r
 133 \r
 134 /*\r
 135  * Setup the timer to generate the tick interrupts.  The implementation in this\r
 136  * file is weak to allow application writers to change the timer used to\r
 137  * generate the tick interrupt.\r
 138  */\r
 139 void vPortSetupTimerInterrupt( void );\r
 140 \r
 141 /*\r
 142  * Exception handlers.\r
 143  */\r
 144 void xPortPendSVHandler( void ) __attribute__ (( naked ));\r
 145 void xPortSysTickHandler( void );\r
 146 void vPortSVCHandler( void ) __attribute__ (( naked ));\r
 147 \r
 148 /*\r
 149  * Start first task is a separate function so it can be tested in isolation.\r
 150  */\r
 151 static void prvPortStartFirstTask( void ) __attribute__ (( naked ));\r
 152 \r
 153 /*\r
 154  * Used to catch tasks that attempt to return from their implementing function.\r
 155  */\r
 156 static void prvTaskExitError( void );\r
 157 \r
 158 /*-----------------------------------------------------------*/\r
 159 \r
 160 /*\r
 161  * The number of SysTick increments that make up one tick period.\r
 162  */\r
 163 #if configUSE_TICKLESS_IDLE == 1\r
 164         static unsigned long ulTimerCountsForOneTick = 0;\r
 165 #endif /* configUSE_TICKLESS_IDLE */\r
 166 \r
 167 /*\r
 168  * The maximum number of tick periods that can be suppressed is limited by the\r
 169  * 24 bit resolution of the SysTick timer.\r
 170  */\r
 171 #if configUSE_TICKLESS_IDLE == 1\r
 172         static unsigned long xMaximumPossibleSuppressedTicks = 0;\r
 173 #endif /* configUSE_TICKLESS_IDLE */\r
 174 \r
 175 /*\r
 176  * Compensate for the CPU cycles that pass while the SysTick is stopped (low\r
 177  * power functionality only.\r
 178  */\r
 179 #if configUSE_TICKLESS_IDLE == 1\r
 180         static unsigned long ulStoppedTimerCompensation = 0;\r
 181 #endif /* configUSE_TICKLESS_IDLE */\r
 182 \r
 183 /*\r
 184  * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure\r
 185  * FreeRTOS API functions are not called from interrupts that have been assigned\r
 186  * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 187  */\r
 188 #if ( configASSERT_DEFINED == 1 )\r
 189          static unsigned char ucMaxSysCallPriority = 0;\r
 190          static unsigned long ulMaxPRIGROUPValue = 0;\r
 191          static const volatile unsigned char * const pcInterruptPriorityRegisters = ( const volatile unsigned char * const ) portNVIC_IP_REGISTERS_OFFSET_16;\r
 192 #endif /* configASSERT_DEFINED */\r
 193 \r
 194 /*-----------------------------------------------------------*/\r
 195 \r
 196 /*\r
 197  * See header file for description.\r
 198  */\r
 199 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
 200 {\r
 201         /* Simulate the stack frame as it would be created by a context switch\r
 202         interrupt. */\r
 203         pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
 204         *pxTopOfStack = portINITIAL_XPSR;       /* xPSR */\r
 205         pxTopOfStack--;\r
 206         *pxTopOfStack = ( portSTACK_TYPE ) pxCode;      /* PC */\r
 207         pxTopOfStack--;\r
 208         *pxTopOfStack = ( portSTACK_TYPE ) portTASK_RETURN_ADDRESS;     /* LR */\r
 209         pxTopOfStack -= 5;      /* R12, R3, R2 and R1. */\r
 210         *pxTopOfStack = ( portSTACK_TYPE ) pvParameters;        /* R0 */\r
 211         pxTopOfStack -= 8;      /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
 212 \r
 213         return pxTopOfStack;\r
 214 }\r
 215 /*-----------------------------------------------------------*/\r
 216 \r
 217 static void prvTaskExitError( void )\r
 218 {\r
 219         /* A function that implements a task must not exit or attempt to return to\r
 220         its caller as there is nothing to return to.  If a task wants to exit it \r
 221         should instead call vTaskDelete( NULL ).\r
 222         \r
 223         Artificially force an assert() to be triggered if configASSERT() is \r
 224         defined, then stop here so application writers can catch the error. */\r
 225         configASSERT( uxCriticalNesting == ~0UL );\r
 226         portDISABLE_INTERRUPTS();       \r
 227         for( ;; );\r
 228 }\r
 229 /*-----------------------------------------------------------*/\r
 230 \r
 231 void vPortSVCHandler( void )\r
 232 {\r
 233         __asm volatile (\r
 234                                         "       ldr     r3, pxCurrentTCBConst2          \n" /* Restore the context. */\r
 235                                         "       ldr r1, [r3]                                    \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */\r
 236                                         "       ldr r0, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
 237                                         "       ldmia r0!, {r4-r11}                             \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */\r
 238                                         "       msr psp, r0                                             \n" /* Restore the task stack pointer. */\r
 239                                         "       mov r0, #0                                              \n"\r
 240                                         "       msr     basepri, r0                                     \n"\r
 241                                         "       orr r14, #0xd                                   \n"\r
 242                                         "       bx r14                                                  \n"\r
 243                                         "                                                                       \n"\r
 244                                         "       .align 2                                                \n"\r
 245                                         "pxCurrentTCBConst2: .word pxCurrentTCB                         \n"\r
 246                                 );\r
 247 }\r
 248 /*-----------------------------------------------------------*/\r
 249 \r
 250 static void prvPortStartFirstTask( void )\r
 251 {\r
 252         __asm volatile(\r
 253                                         " ldr r0, =0xE000ED08   \n" /* Use the NVIC offset register to locate the stack. */\r
 254                                         " ldr r0, [r0]                  \n"\r
 255                                         " ldr r0, [r0]                  \n"\r
 256                                         " msr msp, r0                   \n" /* Set the msp back to the start of the stack. */\r
 257                                         " cpsie i                               \n" /* Globally enable interrupts. */\r
 258                                         " svc 0                                 \n" /* System call to start first task. */\r
 259                                         " nop                                   \n"\r
 260                                 );\r
 261 }\r
 262 /*-----------------------------------------------------------*/\r
 263 \r
 264 /*\r
 265  * See header file for description.\r
 266  */\r
 267 portBASE_TYPE xPortStartScheduler( void )\r
 268 {\r
 269         /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.\r
 270         See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\r
 271         configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );\r
 272 \r
 273         #if( configASSERT_DEFINED == 1 )\r
 274         {\r
 275                 volatile unsigned long ulOriginalPriority;\r
 276                 volatile char * const pcFirstUserPriorityRegister = ( volatile char * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r
 277                 volatile unsigned char ucMaxPriorityValue;\r
 278 \r
 279                 /* Determine the maximum priority from which ISR safe FreeRTOS API\r
 280                 functions can be called.  ISR safe functions are those that end in\r
 281                 "FromISR".  FreeRTOS maintains separate thread and ISR API functions to\r
 282                 ensure interrupt entry is as fast and simple as possible.\r
 283 \r
 284                 Save the interrupt priority value that is about to be clobbered. */\r
 285                 ulOriginalPriority = *pcFirstUserPriorityRegister;\r
 286 \r
 287                 /* Determine the number of priority bits available.  First write to all\r
 288                 possible bits. */\r
 289                 *pcFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\r
 290 \r
 291                 /* Read the value back to see how many bits stuck. */\r
 292                 ucMaxPriorityValue = *pcFirstUserPriorityRegister;\r
 293 \r
 294                 /* Use the same mask on the maximum system call priority. */\r
 295                 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\r
 296 \r
 297                 /* Calculate the maximum acceptable priority group value for the number\r
 298                 of bits read back. */\r
 299                 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;\r
 300                 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\r
 301                 {\r
 302                         ulMaxPRIGROUPValue--;\r
 303                         ucMaxPriorityValue <<= ( unsigned char ) 0x01;\r
 304                 }\r
 305 \r
 306                 /* Shift the priority group value back to its position within the AIRCR\r
 307                 register. */\r
 308                 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\r
 309                 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;\r
 310 \r
 311                 /* Restore the clobbered interrupt priority register to its original\r
 312                 value. */\r
 313                 *pcFirstUserPriorityRegister = ulOriginalPriority;\r
 314         }\r
 315         #endif /* conifgASSERT_DEFINED */\r
 316 \r
 317         /* Make PendSV and SysTick the lowest priority interrupts. */\r
 318         portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;\r
 319         portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;\r
 320 \r
 321         /* Start the timer that generates the tick ISR.  Interrupts are disabled\r
 322         here already. */\r
 323         vPortSetupTimerInterrupt();\r
 324 \r
 325         /* Initialise the critical nesting count ready for the first task. */\r
 326         uxCriticalNesting = 0;\r
 327 \r
 328         /* Start the first task. */\r
 329         prvPortStartFirstTask();\r
 330 \r
 331         /* Should not get here! */\r
 332         return 0;\r
 333 }\r
 334 /*-----------------------------------------------------------*/\r
 335 \r
 336 void vPortEndScheduler( void )\r
 337 {\r
 338         /* It is unlikely that the CM3 port will require this function as there\r
 339         is nothing to return to.  */\r
 340 }\r
 341 /*-----------------------------------------------------------*/\r
 342 \r
 343 void vPortYield( void )\r
 344 {\r
 345         /* Set a PendSV to request a context switch. */\r
 346         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 347 \r
 348         /* Barriers are normally not required but do ensure the code is completely\r
 349         within the specified behaviour for the architecture. */\r
 350         __asm volatile( "dsb" );\r
 351         __asm volatile( "isb" );\r
 352 }\r
 353 /*-----------------------------------------------------------*/\r
 354 \r
 355 void vPortEnterCritical( void )\r
 356 {\r
 357         portDISABLE_INTERRUPTS();\r
 358         uxCriticalNesting++;\r
 359         __asm volatile( "dsb" );\r
 360         __asm volatile( "isb" );\r
 361 }\r
 362 /*-----------------------------------------------------------*/\r
 363 \r
 364 void vPortExitCritical( void )\r
 365 {\r
 366         uxCriticalNesting--;\r
 367         if( uxCriticalNesting == 0 )\r
 368         {\r
 369                 portENABLE_INTERRUPTS();\r
 370         }\r
 371 }\r
 372 /*-----------------------------------------------------------*/\r
 373 \r
 374 __attribute__(( naked )) unsigned long ulPortSetInterruptMask( void )\r
 375 {\r
 376         __asm volatile                                                                                                          \\r
 377         (                                                                                                                                       \\r
 378                 "       mrs r0, basepri                                                                                 \n" \\r
 379                 "       mov r1, %0                                                                                              \n"     \\r
 380                 "       msr basepri, r1                                                                                 \n" \\r
 381                 "       bx lr                                                                                                   \n" \\r
 382                 :: "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "r0", "r1"    \\r
 383         );\r
 384 \r
 385         /* This return will not be reached but is necessary to prevent compiler\r
 386         warnings. */\r
 387         return 0;\r
 388 }\r
 389 /*-----------------------------------------------------------*/\r
 390 \r
 391 __attribute__(( naked )) void vPortClearInterruptMask( unsigned long ulNewMaskValue )\r
 392 {\r
 393         __asm volatile                                                                                                  \\r
 394         (                                                                                                                               \\r
 395                 "       msr basepri, r0                                                                         \n"     \\r
 396                 "       bx lr                                                                                           \n" \\r
 397                 :::"r0"                                                                                                         \\r
 398         );\r
 399 \r
 400         /* Just to avoid compiler warnings. */\r
 401         ( void ) ulNewMaskValue;\r
 402 }\r
 403 /*-----------------------------------------------------------*/\r
 404 \r
 405 void xPortPendSVHandler( void )\r
 406 {\r
 407         /* This is a naked function. */\r
 408 \r
 409         __asm volatile\r
 410         (\r
 411         "       mrs r0, psp                                                     \n"\r
 412         "                                                                               \n"\r
 413         "       ldr     r3, pxCurrentTCBConst                   \n" /* Get the location of the current TCB. */\r
 414         "       ldr     r2, [r3]                                                \n"\r
 415         "                                                                               \n"\r
 416         "       stmdb r0!, {r4-r11}                                     \n" /* Save the remaining registers. */\r
 417         "       str r0, [r2]                                            \n" /* Save the new top of stack into the first member of the TCB. */\r
 418         "                                                                               \n"\r
 419         "       stmdb sp!, {r3, r14}                            \n"\r
 420         "       mov r0, %0                                                      \n"\r
 421         "       msr basepri, r0                                         \n"\r
 422         "       bl vTaskSwitchContext                           \n"\r
 423         "       mov r0, #0                                                      \n"\r
 424         "       msr basepri, r0                                         \n"\r
 425         "       ldmia sp!, {r3, r14}                            \n"\r
 426         "                                                                               \n"     /* Restore the context, including the critical nesting count. */\r
 427         "       ldr r1, [r3]                                            \n"\r
 428         "       ldr r0, [r1]                                            \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
 429         "       ldmia r0!, {r4-r11}                                     \n" /* Pop the registers. */\r
 430         "       msr psp, r0                                                     \n"\r
 431         "       bx r14                                                          \n"\r
 432         "                                                                               \n"\r
 433         "       .align 2                                                        \n"\r
 434         "pxCurrentTCBConst: .word pxCurrentTCB  \n"\r
 435         ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)\r
 436         );\r
 437 }\r
 438 /*-----------------------------------------------------------*/\r
 439 \r
 440 void xPortSysTickHandler( void )\r
 441 {\r
 442         /* The SysTick runs at the lowest interrupt priority, so when this interrupt\r
 443         executes all interrupts must be unmasked.  There is therefore no need to\r
 444         save and then restore the interrupt mask value as its value is already\r
 445         known. */\r
 446         ( void ) portSET_INTERRUPT_MASK_FROM_ISR();\r
 447         {\r
 448                 /* Increment the RTOS tick. */\r
 449                 if( xTaskIncrementTick() != pdFALSE )\r
 450                 {\r
 451                         /* A context switch is required.  Context switching is performed in\r
 452                         the PendSV interrupt.  Pend the PendSV interrupt. */\r
 453                         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 454                 }\r
 455         }\r
 456         portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );\r
 457 }\r
 458 /*-----------------------------------------------------------*/\r
 459 \r
 460 #if configUSE_TICKLESS_IDLE == 1\r
 461 \r
 462         __attribute__((weak)) void vPortSuppressTicksAndSleep( portTickType xExpectedIdleTime )\r
 463         {\r
 464         unsigned long ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;\r
 465         portTickType xModifiableIdleTime;\r
 466 \r
 467                 /* Make sure the SysTick reload value does not overflow the counter. */\r
 468                 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\r
 469                 {\r
 470                         xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\r
 471                 }\r
 472 \r
 473                 /* Stop the SysTick momentarily.  The time the SysTick is stopped for\r
 474                 is accounted for as best it can be, but using the tickless mode will\r
 475                 inevitably result in some tiny drift of the time maintained by the\r
 476                 kernel with respect to calendar time. */\r
 477                 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\r
 478 \r
 479                 /* Calculate the reload value required to wait xExpectedIdleTime\r
 480                 tick periods.  -1 is used because this code will execute part way\r
 481                 through one of the tick periods. */\r
 482                 ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\r
 483                 if( ulReloadValue > ulStoppedTimerCompensation )\r
 484                 {\r
 485                         ulReloadValue -= ulStoppedTimerCompensation;\r
 486                 }\r
 487 \r
 488                 /* Enter a critical section but don't use the taskENTER_CRITICAL()\r
 489                 method as that will mask interrupts that should exit sleep mode. */\r
 490                 __asm volatile( "cpsid i" );\r
 491 \r
 492                 /* If a context switch is pending or a task is waiting for the scheduler\r
 493                 to be unsuspended then abandon the low power entry. */\r
 494                 if( eTaskConfirmSleepModeStatus() == eAbortSleep )\r
 495                 {\r
 496                         /* Restart from whatever is left in the count register to complete\r
 497                         this tick period. */\r
 498                         portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;\r
 499                         \r
 500                         /* Restart SysTick. */\r
 501                         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 502                         \r
 503                         /* Reset the reload register to the value required for normal tick\r
 504                         periods. */\r
 505                         portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\r
 506 \r
 507                         /* Re-enable interrupts - see comments above the cpsid instruction()\r
 508                         above. */\r
 509                         __asm volatile( "cpsie i" );\r
 510                 }\r
 511                 else\r
 512                 {\r
 513                         /* Set the new reload value. */\r
 514                         portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\r
 515 \r
 516                         /* Clear the SysTick count flag and set the count value back to\r
 517                         zero. */\r
 518                         portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
 519 \r
 520                         /* Restart SysTick. */\r
 521                         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 522 \r
 523                         /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can\r
 524                         set its parameter to 0 to indicate that its implementation contains\r
 525                         its own wait for interrupt or wait for event instruction, and so wfi\r
 526                         should not be executed again.  However, the original expected idle\r
 527                         time variable must remain unmodified, so a copy is taken. */\r
 528                         xModifiableIdleTime = xExpectedIdleTime;\r
 529                         configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\r
 530                         if( xModifiableIdleTime > 0 )\r
 531                         {\r
 532                                 __asm volatile( "dsb" );\r
 533                                 __asm volatile( "wfi" );\r
 534                                 __asm volatile( "isb" );\r
 535                         }\r
 536                         configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\r
 537 \r
 538                         /* Stop SysTick.  Again, the time the SysTick is stopped for is\r
 539                         accounted for as best it can be, but using the tickless mode will\r
 540                         inevitably result in some tiny drift of the time maintained by the\r
 541                         kernel with respect to calendar time. */\r
 542                         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\r
 543 \r
 544                         /* Re-enable interrupts - see comments above the cpsid instruction()\r
 545                         above. */\r
 546                         __asm volatile( "cpsie i" );\r
 547 \r
 548                         if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\r
 549                         {\r
 550                                 /* The tick interrupt has already executed, and the SysTick\r
 551                                 count reloaded with ulReloadValue.  Reset the\r
 552                                 portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick\r
 553                                 period. */\r
 554                                 portNVIC_SYSTICK_LOAD_REG = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\r
 555 \r
 556                                 /* The tick interrupt handler will already have pended the tick\r
 557                                 processing in the kernel.  As the pending tick will be\r
 558                                 processed as soon as this function exits, the tick value\r
 559                                 maintained by the tick is stepped forward by one less than the\r
 560                                 time spent waiting. */\r
 561                                 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\r
 562                         }\r
 563                         else\r
 564                         {\r
 565                                 /* Something other than the tick interrupt ended the sleep.\r
 566                                 Work out how long the sleep lasted rounded to complete tick\r
 567                                 periods (not the ulReload value which accounted for part\r
 568                                 ticks). */\r
 569                                 ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;\r
 570 \r
 571                                 /* How many complete tick periods passed while the processor\r
 572                                 was waiting? */\r
 573                                 ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\r
 574 \r
 575                                 /* The reload value is set to whatever fraction of a single tick\r
 576                                 period remains. */\r
 577                                 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1 ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\r
 578                         }\r
 579 \r
 580                         /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG\r
 581                         again, then set portNVIC_SYSTICK_LOAD_REG back to its standard\r
 582                         value.  The critical section is used to ensure the tick interrupt\r
 583                         can only execute once in the case that the reload register is near\r
 584                         zero. */\r
 585                         portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
 586                         portENTER_CRITICAL();\r
 587                         {\r
 588                                 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 589                                 vTaskStepTick( ulCompleteTickPeriods );\r
 590                                 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\r
 591                         }\r
 592                         portEXIT_CRITICAL();\r
 593                 }\r
 594         }\r
 595 \r
 596 #endif /* #if configUSE_TICKLESS_IDLE */\r
 597 /*-----------------------------------------------------------*/\r
 598 \r
 599 /*\r
 600  * Setup the systick timer to generate the tick interrupts at the required\r
 601  * frequency.\r
 602  */\r
 603 __attribute__(( weak )) void vPortSetupTimerInterrupt( void )\r
 604 {\r
 605         /* Calculate the constants required to configure the tick interrupt. */\r
 606         #if configUSE_TICKLESS_IDLE == 1\r
 607         {\r
 608                 ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\r
 609                 xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\r
 610                 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\r
 611         }\r
 612         #endif /* configUSE_TICKLESS_IDLE */\r
 613 \r
 614         /* Configure SysTick to interrupt at the requested rate. */\r
 615         portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;;\r
 616         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 617 }\r
 618 /*-----------------------------------------------------------*/\r
 619 \r
 620 #if( configASSERT_DEFINED == 1 )\r
 621 \r
 622         void vPortValidateInterruptPriority( void )\r
 623         {\r
 624         unsigned long ulCurrentInterrupt;\r
 625         unsigned char ucCurrentPriority;\r
 626 \r
 627                 /* Obtain the number of the currently executing interrupt. */\r
 628                 __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );\r
 629 \r
 630                 /* Is the interrupt number a user defined interrupt? */\r
 631                 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\r
 632                 {\r
 633                         /* Look up the interrupt's priority. */\r
 634                         ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\r
 635 \r
 636                         /* The following assertion will fail if a service routine (ISR) for\r
 637                         an interrupt that has been assigned a priority above\r
 638                         configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\r
 639                         function.  ISR safe FreeRTOS API functions must *only* be called\r
 640                         from interrupts that have been assigned a priority at or below\r
 641                         configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 642 \r
 643                         Numerically low interrupt priority numbers represent logically high\r
 644                         interrupt priorities, therefore the priority of the interrupt must\r
 645                         be set to a value equal to or numerically *higher* than\r
 646                         configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 647 \r
 648                         Interrupts that use the FreeRTOS API must not be left at their\r
 649                         default priority of     zero as that is the highest possible priority,\r
 650                         which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,\r
 651                         and     therefore also guaranteed to be invalid.\r
 652 \r
 653                         FreeRTOS maintains separate thread and ISR API functions to ensure\r
 654                         interrupt entry is as fast and simple as possible.\r
 655 \r
 656                         The following links provide detailed information:\r
 657                         http://www.freertos.org/RTOS-Cortex-M3-M4.html\r
 658                         http://www.freertos.org/FAQHelp.html */\r
 659                         configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\r
 660                 }\r
 661 \r
 662                 /* Priority grouping:  The interrupt controller (NVIC) allows the bits\r
 663                 that define each interrupt's priority to be split between bits that\r
 664                 define the interrupt's pre-emption priority bits and bits that define\r
 665                 the interrupt's sub-priority.  For simplicity all bits must be defined\r
 666                 to be pre-emption priority bits.  The following assertion will fail if\r
 667                 this is not the case (if some bits represent a sub-priority).\r
 668 \r
 669                 If the application only uses CMSIS libraries for interrupt\r
 670                 configuration then the correct setting can be achieved on all Cortex-M\r
 671                 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\r
 672                 scheduler.  Note however that some vendor specific peripheral libraries\r
 673                 assume a non-zero priority group setting, in which cases using a value\r
 674                 of zero will result in unpredicable behaviour. */\r
 675                 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );\r
 676         }\r
 677 \r
 678 #endif /* configASSERT_DEFINED */\r
 679 \r
 680 \r
 681 \r
 682 \r
 683 \r
 684 \r
 685 \r
 686 \r
 687 \r
 688 \r
 689 \r
 690 \r
 691 \r
 692 \r
 693 \r
 694 \r
 695 \r
 696 \r
 697 \r
 698 \r
 699 \r